DE102004006676A1 - Dynamische Speicherzelle - Google Patents

Dynamische Speicherzelle Download PDF

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Publication number
DE102004006676A1
DE102004006676A1 DE102004006676A DE102004006676A DE102004006676A1 DE 102004006676 A1 DE102004006676 A1 DE 102004006676A1 DE 102004006676 A DE102004006676 A DE 102004006676A DE 102004006676 A DE102004006676 A DE 102004006676A DE 102004006676 A1 DE102004006676 A1 DE 102004006676A1
Authority
DE
Germany
Prior art keywords
channel region
storage cell
charge carriers
structured
arranged directly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE102004006676A
Other languages
English (en)
Inventor
Martin Verhoeven
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE102004006676A priority Critical patent/DE102004006676A1/de
Publication of DE102004006676A1 publication Critical patent/DE102004006676A1/de
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H01L29/42352—Gate electrodes for transistors with charge trapping gate insulator with the gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)

Abstract

Die Erfindung betrifft eine Speicherzelle mit einem Auswahltransistor, der einen ersten Anschluss (3), einen zweiten Anschluss (5), einen zwischen dem ersten Anschluss (3) und dem zweiten Anschluss (5) ausgebildeten Kanalbereich (2) und einen benachbart zum Kanalbereich (2) angeordneten Steueranschluss (1) aufweist, um abhängig von der Ansteuerung des Steueranschlusses (1) einen leitenden Kanal zwischen dem ersten und dem zweiten Anschluss (3, 5) im Kanal auszubilden, und mit einem an dem Auswahltransistor angeschlossenen Speicherelement (6), um Ladungsträger aus dem Kanalbereich (2) zu speichern, wobei das Speicherelement (6) unmittelbar an dem Kanalbereich (2) angeordnet ist, um je nach Ansteuerung des Steueranschlusses (1) die Ladungsträger einzuspeichern oder abzugeben.
DE102004006676A 2004-02-11 2004-02-11 Dynamische Speicherzelle Ceased DE102004006676A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE102004006676A DE102004006676A1 (de) 2004-02-11 2004-02-11 Dynamische Speicherzelle

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102004006676A DE102004006676A1 (de) 2004-02-11 2004-02-11 Dynamische Speicherzelle

Publications (1)

Publication Number Publication Date
DE102004006676A1 true DE102004006676A1 (de) 2005-05-04

Family

ID=34399812

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102004006676A Ceased DE102004006676A1 (de) 2004-02-11 2004-02-11 Dynamische Speicherzelle

Country Status (1)

Country Link
DE (1) DE102004006676A1 (de)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1951787A1 (de) * 1968-10-14 1970-04-30 Sperry Rand Corp Speicherelement
DE10130765A1 (de) * 2001-06-26 2003-01-09 Infineon Technologies Ag Transistor-Anordnung, Verfahren zum Betreiben einer Transistor-Anordnung als Datenspeicher und Verfahren zum Herstellen einer Transistor-Anordnung

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1951787A1 (de) * 1968-10-14 1970-04-30 Sperry Rand Corp Speicherelement
DE10130765A1 (de) * 2001-06-26 2003-01-09 Infineon Technologies Ag Transistor-Anordnung, Verfahren zum Betreiben einer Transistor-Anordnung als Datenspeicher und Verfahren zum Herstellen einer Transistor-Anordnung

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Legal Events

Date Code Title Description
OAV Publication of unexamined application with consent of applicant
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection