DE10158374C1 - HF oscillation prevention circuit for power semiconductor module uses inductors and capacitors for de-tuning oscillator provided by parallel semiconductors - Google Patents
HF oscillation prevention circuit for power semiconductor module uses inductors and capacitors for de-tuning oscillator provided by parallel semiconductorsInfo
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- DE10158374C1 DE10158374C1 DE10158374A DE10158374A DE10158374C1 DE 10158374 C1 DE10158374 C1 DE 10158374C1 DE 10158374 A DE10158374 A DE 10158374A DE 10158374 A DE10158374 A DE 10158374A DE 10158374 C1 DE10158374 C1 DE 10158374C1
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Abstract
Description
Die Erfindung beschreibt eine Schaltungsanordnung für Leistungshalbleitermodulen wobei PETT-Schwingungen wirkungsvoll unterdrückt werden. Derartige Leistungshalbleitermodule bestehen aus mindestens einem Leistungsschalter, einem isolierenden Substrat und einem Gehäuse, wobei ein Leistungsschalter bei den meisten Leistungshalbleitermodulen nach dem Stand der Technik aus mehreren Leistungstransistoren besteht. Die Leistungsschalter bestehen beispielsweise aus einer Parallelschaltung von mehreren IGBTs mit einer oder mehreren antiparallel dazu geschalteten Leistungsdioden.The invention describes a circuit arrangement for power semiconductor modules PETT vibrations are effectively suppressed. Such power semiconductor modules consist of at least one circuit breaker, one insulating substrate and one Housing, with a circuit breaker for most power semiconductor modules the prior art consists of several power transistors. The circuit breakers consist for example of a parallel connection of several IGBTs with one or several power diodes connected antiparallel to it.
Nach dem Abschalten eines aus mindestens zwei Halbleiterbauelementen gebildeten Leistungsschalters können im Emitter-Kollektorkreis hochfrequente Schwingungen mit einer Frequenz von einigen Hundert Megahertz auftreten. Diese sog. PETT-Schwingungen (PETT = plasma extraction transit time) führen zu einem abgestrahlten elekro-magnetischen Feld, das als Störsignal z. B. in EMV-Messungen detektiert werden kann.After switching off one formed from at least two semiconductor components Circuit breakers can emit high-frequency vibrations in the emitter collector circuit Frequency of several hundred megahertz occur. These so-called PETT vibrations (PETT = plasma extraction transit time) lead to a radiated electro-magnetic Field that as a noise signal z. B. can be detected in EMC measurements.
Beispielsweise können derartige PETT-Schwingungen bei folgenden Konstellationen
auftreten:
Nach dem Abschalten mehrerer parallel geschalteter IGBTs (insulated gate bipolar
transistor) klingt der Strom durch die IGBTs langsam auf Null ab. In diesem "Tailstrom"
genannten Stromabfall treten Mikrosekunden nach dem Abschalten die PETT-
Schwingungen mit einer Frequenz von einigen hundert Megahertz und einer Zeitdauer von
einigen Mikrosekunden auf. Diese ist beschrieben in Proceedings of the 31th European Solid-
State Device Research Conference 2001, Seite 255-258.For example, such PETT vibrations can occur in the following constellations:
After switching off several IGBTs (insulated gate bipolar transistor) connected in parallel, the current through the IGBTs slowly decays to zero. In this current drop called "tail current", microseconds after switching off the PETT oscillations occur with a frequency of a few hundred megahertz and a period of a few microseconds. This is described in Proceedings of the 31 th European Solid-State Device Research Conference 2001 , pages 255-258.
Am Ende der Diodenrückstromspitze wurden ebenfalls PETT-Schwingungen im gleichen Frequenzbereich mit einer vergleichbaren Zeitdauer festgestellt. At the end of the diode reverse current peak, PETT oscillations were also in the same Frequency range with a comparable duration determined.
Bisher sind ausschließlich Lösungsansätze zur Vermeidung von PETT-Schwingungen bei Leistungstransistoren bekannt, speziell Leistungsdioden wurden im Zusammenhang mit PETT-Schwingungen bisher nicht untersucht.So far, only approaches to avoid PETT vibrations have been included Power transistors are known, specifically power diodes have been associated with So far, PETT vibrations have not been investigated.
Aus der DE 195 49 011 ist mindestens eine zusätzliche Verbindungsleitung bekannt, die die Emitterkontakte zweier direkt benachbarter IGBT-Bauelemente elektrisch miteinander verbindet. Auf diese Weise ändert sich die Induktivität der Verbindung der beiden IGBT- Bauelemente. Die Änderung der Induktivität zieht eine Änderung der Resonanzfrequenz des aus der Kapazität der Bauelemente bzw. des Substrates und der Induktivität der Verbindungen gebildeten Schwingkreises nach sich. Durch diese Änderung fällt diese Resonanzfrequenz nicht mehr mit der Frequenz der laufzeitbedingten Ausräumvorgänge des p-n Übergangs zusammen und es entsteht keine PETT-Schwingung.From DE 195 49 011 at least one additional connecting line is known, the Emitter contacts of two directly adjacent IGBT components are electrically connected to one another combines. In this way, the inductance of the connection between the two IGBT Components. The change in inductance pulls a change in the resonant frequency of the from the capacitance of the components or the substrate and the inductance of the Connections formed resonant circuit after itself. With this change, it falls Resonance frequency no longer with the frequency of the time-related clearing operations of the p-n transition together and there is no PETT vibration.
Die DE 199 38 302 stellt eine Schaltungsanordnung für Leistungshalbleitermodule vor, bei der die Kupferkaschierung des Substrates im Bereich der Emitter und/oder im Bereich des Kollektors eines IGBT-Bauelements mindestens eine unkaschierte Stelle aufweist und bei der die IGBT-Bauelemente eng benachbart angeordnet sind. Die unkaschierten Stellen führen zu einer Veränderung des Ohmschen Widerstandes und induzieren auf der Rückseite des Substrates Wirbelströme, die dem ursprünglichen Magnetfeld der parasitären Induktivität entgegengerichtet sind.DE 199 38 302 presents a circuit arrangement for power semiconductor modules the copper cladding of the substrate in the area of the emitter and / or in the area of the Collector of an IGBT component has at least one unclad and at which the IGBT components are arranged in close proximity. The uncovered areas lead to a change in the ohmic resistance and induce on the back of the substrate eddy currents, the original magnetic field of parasitic inductance are opposed.
Nachteilig an dieser Lösung ist, dass für jede geometrische Anordnung der Bauelemente auf dem Substrat die Lage der unkaschierten Stellen neu bestimmt werden muss. Auch in der DE 199 38 302 wird nicht näher auf Leistungsdioden eingegangen.The disadvantage of this solution is that for every geometric arrangement of the components the position of the unclad spots must be redetermined on the substrate. Also in the DE 199 38 302 does not deal in detail with power diodes.
Ausgangspunkt der Erfindung sind Leistungshalbleitermodule bzw. Teile derartiger Module mit einer Schaltungsanordnung in Halbbrückentopologie.The starting point of the invention are power semiconductor modules or parts of such modules with a circuit arrangement in half-bridge topology.
Die vorliegende Erfindung hat die Aufgabe eine Schaltungsanordnung vorzustellen, die PETT-Schwingungen zwischen verschiedenen Leistungshalbleiterbauelementen, also zwischen mindestens zwei Transistoren, zwischen mindestens zwei Dioden oder zwischen mindestens einem Transistor und einer Diode, zu verhindern.The object of the present invention is to present a circuit arrangement which PETT vibrations between different power semiconductor components, so between at least two transistors, between at least two diodes or between to prevent at least one transistor and one diode.
Die Aufgabe wird gelöst durch die Maßnahmen des Anspruchs 1. Weitere vorteilhafte Ausgestaltungen sind in den Unteransprüchen genannt.The object is achieved by the measures of claim 1. Further advantageous Refinements are mentioned in the subclaims.
PETT-Schwingungen entstehen indem Löcher aus dem noch im abgeschalteten Halbleiterbauelement vorhanden Plasma extrahiert werden und mit einer gewissen Verzögerung durch die Raumladungszone laufen. Diese Verzögerung liegt in der Größenordnung von einer bis wenigen Nanosekunden. Hierdurch wird das elektrische Feld moduliert und damit die Spannungsänderung über dem p-n-Übergang verzögert. Dies führt zu einem negativen Widerstand, der, falls er groß genug ist, die hochfrequente PETT- Schwingung anregt. Dieser Mechanismus ist im Wesentlichen identisch sowohl in Transistoren als auch in Dioden, wobei es sich jeweils um einen bipolaren Effekt handelt, bei dem ein Plasma aus Elektronen und Löchern im Halbleiterbauelement vorhanden ist. Allerdings sind ausschließlich die Löcher für den Ladungstransport durch die Raumladungszone verantwortlich. In diesem Betriebszustand gibt es keine Stoßionisation.PETT vibrations arise in the holes from the still switched off Semiconductor device present and extracted with a certain plasma Run delay through the space charge zone. This delay lies in the On the order of one to a few nanoseconds. This will make the electric field modulated and thus delayed the voltage change across the p-n junction. this leads to to a negative resistance, which, if large enough, the high-frequency PETT Excites vibration. This mechanism is essentially identical in both Transistors as well as in diodes, each of which is a bipolar effect which is a plasma of electrons and holes in the semiconductor device. However, only the holes for the charge transport through the Space charge zone responsible. There is no impact ionization in this operating state.
PETT-Schwingungen sind unterdrückbar durch eine starke Erhöhung oder Verringerung der Induktivitäten zwischen den Halbleiterbauelementen. Eine Erhöhung der Induktivität ist allerdings nicht sinnvoll, da dies die Abschaltüberspannungen stark erhöhen würde.PETT vibrations can be suppressed by a strong increase or decrease in the Inductors between the semiconductor devices. There is an increase in inductance However, this does not make sense, as this would greatly increase the shutdown overvoltages.
Eine Parallelschaltung von mehreren Halbleiterbauelementen bildet einen Schwingkreis. Falls die Periodendauer dieser Schwingkreisresonanz mit der Löcherlaufzeit durch die Raumladungszone korrespondiert bildet sich die PETT-Schwingung aus. Dies kann verhindert werden durch geeignetes Verstimmen diese Schwingkreises, d. h. durch eine Änderung seiner Resonanzfrequenz mittels zusätzlich in die Schaltungsanordnung eingebrachter Induktivitäten oder durch zusätzliche Induktivitäten und damit geeignet verschalteten Kapazitäten.A parallel connection of several semiconductor components forms a resonant circuit. If the period of this resonant circuit resonance with the hole propagation time through the Correspondingly, the space charge zone forms the PETT oscillation. This can are prevented by suitable detuning of this resonant circuit, d. H. by a Change in its resonance frequency by means of additional in the circuit arrangement introduced inductors or by additional inductors and thus suitable interconnected capacities.
Dies kann durch drei unterschiedliche Anordnungen realisiert werden, wobei auch Mischformen möglich sind.This can be achieved by three different arrangements, and also Mixed forms are possible.
- - Mindestens zwei Halbleiterbauelemente weisen jeweils eine zusätzliche parallele Beschaltung durch eine Serienschaltung einer sehr geringe Induktivität und einer weiteren Kapazität auf.- At least two semiconductor components each have an additional parallel one Wiring through a series connection of a very low inductance and one further capacity.
- - Mindestens zwei Halbleiterbauelemente weisen eine Verbindung pro Halbleiterbauelement sehr geringer Induktivität auf, wobei diese Verbindung zusätzlich mindestens eine weitere Kapazität parallel zu den Halbleiterbauelementen aufweist.- At least two semiconductor components have one connection per Semiconductor component of very low inductance, this connection additionally has at least one further capacitance parallel to the semiconductor components.
- - Mindestens zwei Halbleiterbauelemente weisen eine zusätzliche Verbindung mit sehr geringer Induktivität zwischen einander auf.- At least two semiconductor components have an additional connection with very low inductance between each other.
Die erfinderische Lösung wird an Hand der Fig. 1 bis 7 weiter erläutert.The inventive solution is further explained with reference to FIGS. 1 to 7.
Fig. 1 zeigt eine Schaltungsanordnung in Halbbrückentopologie nach dem Stand der Technik. Fig. 1 shows a circuit arrangement in half-bridge topology according to prior art.
Fig. 2 zeigt die Anordnung eines Halbleiterbauelements auf einem beidseitig metallkaschierten Substrat. Fig. 2 shows the arrangement of a semiconductor device on a both sides metal-clad substrate.
Fig. 3 zeigt ein Ersatzschaltbild einer Parallelschaltung zweier Halbleiterbauelemente Fig. 3 is an equivalent circuit diagram showing a parallel circuit of two semiconductor components
Fig. 4 und 5 zeigen verschiedene erfinderische Lösungen zur Verstimmung des durch zwei Halbleiterbauelemente gebildeten Schwingkreises. Die Verallgemeinerung auf beliebig viele Halbleiterbauelemente ergibt sich analog. FIGS. 4 and 5 show various inventive solutions for detuning the resonant circuit formed by two semiconductor components. The generalization to any number of semiconductor components is analogous.
Fig. 6 zeigt eine an sich bekannte Lösung Fig. 6 shows a known solution
Fig. 7 zeigt eine Messung einer PETT-Schwingung erzeugt durch die Diodenrückstromspitze. Fig. 7 shows a measurement of a PETT vibration generated by the diode reverse current peak.
Fig. 1 zeigt eine Schaltungsanordnung in Halbbrückentopologie nach dem Stand der Technik. Diese besteht aus einem positiven und einem negativen Anschluss an den Zwischenkreis, einem durch mindestens einen Transistor TT in TOP-Position und mindestens einer dazu antiparallel geschalteten Freilaufdiode DT gebildeten TOP-Schalter, einem durch mindestens einen Transistor TB in BOT-Position und mindestens einer dazu antiparallel geschalteten Freilaufdiode DB, gebildeten BOT-Schalter sowie einem Wechselstromanschluss. Beim Abschalten der Transistoren eines der beiden Schalter sind die antiparallel dazu verschalteten Dioden nicht aktiv, und wirken daher als parallel zu den Transistoren geschaltete Kapazitäten. Diese Kapazitäten können nun zur Verstimmung des Schwingkreises herangezogen werden, indem diese sehr niederinduktiv mit den die PETT- Schwingungen verursachenden Halbleiterbauelementen verschaltet werden. Dies geschieht vorzugsweise mittels Bonddrähten. Fig. 1 shows a circuit arrangement in half-bridge topology according to prior art. This consists of a positive and a negative connection to the intermediate circuit, a TOP switch formed by at least one transistor T T in the TOP position and at least one free-wheeling diode D T connected antiparallel to it, one by at least one transistor T B in the BOT position and at least one freewheeling diode D B connected antiparallel to this, formed BOT switches and an AC connection. When the transistors of one of the two switches are switched off, the diodes connected in antiparallel to them are not active and therefore act as capacitors connected in parallel with the transistors. These capacities can now be used to detune the resonant circuit by interconnecting them very low-inductively with the semiconductor components causing the PETT oscillations. This is preferably done using bond wires.
Fig. 2 zeigt die Anordnung eines Halbleiterbauelements (H) auf einem beidseitig metallkaschierten Substrat. Hier bei sind die Kapazitäten (Cb1, Cb2), die durch die Metallkaschierungen (M1, M2) bzw. die Rückseitenmetallisierung (M) der beiden Seiten des Substrates sowie dem Substrat (S) selbst als Dielektrikum gebildet werden, gezeigt. Die Bondverbindungen stellen die Induktivitäten (Lx, Lb) der Schaltungsanordnung dar. Die Induktivitäten des Substrates (S) sind gegenüber den Induktivitäten der Bondverbindungen sehr gering und damit vernachlässigbar. Fig. 2 shows the arrangement of a semiconductor device (H) on both sides on a metal-clad substrate. The capacitances (C b1 , C b2 ), which are formed by the metal claddings (M 1 , M 2 ) or the rear side metallization (M) of the two sides of the substrate and the substrate (S) itself as a dielectric, are shown here. The bond connections represent the inductivities (L x , L b ) of the circuit arrangement. The inductivities of the substrate (S) are very small compared to the inductivities of the bond connections and are therefore negligible.
Fig. 3 zeigt ein Ersatzschaltbild einer Parallelschaltung zweier Halbleiterbauelemente. Diese Anordnungen stellt den die PETT-Schwingungen erzeugenden Schwingkreis dar. Lx stellt hierbei die Induktivität der Bonddrähte zum Halbleiterbauelement dar. Rx ist der Hochfrequenzwiderstand des Substrats und der Bondverbindungen aufgrund des Skin- Effekts. -R ist der interne negative Widerstand des Halbleiterbauelements und CH dessen interne Kapazität. Fig. 3 is an equivalent circuit diagram showing a parallel circuit of two semiconductor devices. These arrangements represent the resonant circuit which generates the PETT oscillations. L x represents the inductance of the bond wires to the semiconductor component. R x is the high-frequency resistance of the substrate and the bond connections due to the skin effect. -R is the internal negative resistance of the semiconductor device and C H is its internal capacitance.
Fig. 4 zeigt eine erfinderische Lösung zur Verstimmung des durch die Halbleiterbauelemente gebildeten Schwingkreises, indem jedem Halbleiterbauelement eine Serienschaltung aus der geringen Induktivität Lb und der Kapazität Cb parallel geschaltet wird. Die Kapazität Cb wird hierbei gebildet aus der Serienschaltung der Kapazitäten Cb1 und Cb2 (vgl. Fig. 2). Zur Realisierung dieser Lösung ist z. B. je Diode eine zusätzliche zu den umgebenden Metallkaschierungen isolierte metallkaschierte Fläche auf dem Substrat vorzusehen, die mit der rückseitigen Metallkaschierung des Substrates die Kapazität Cb2 bildet und mittels Bondverbindungen mit den Kathoden der jeweiligen Freilaufdiode des jeweiligen Schalters sehr niederinduktiv mittels Bonddraht verbunden ist. FIG. 4 shows an inventive solution for detuning the resonant circuit formed by the semiconductor components, in that each semiconductor component is connected in parallel with a series circuit comprising the low inductance L b and the capacitance C b . The capacitance C b is formed from the series connection of the capacitances C b1 and C b2 (cf. FIG. 2). To implement this solution, for. B. for each diode to provide an additional metal-clad surface insulated from the surrounding metal cladding, which forms the capacitance C b2 with the back metal cladding of the substrate and is connected by means of bond connections to the cathodes of the respective freewheeling diode of the respective switch in a very low-inductance manner by means of bonding wire.
Fig. 5 zeigt eine weitere erfinderische Lösung zur Verstimmung des durch die Halbleiterbauelemente gebildeten Schwingkreises, indem zwei Halbleiterbauelemente durch eine Verbindung miteinander mit pro Halbleiterbauelement einer sehr geringer Induktivität Lb' verschaltet sind, wobei diese Verbindung in ihrem Mittelpunkt eine weitere Kapazität Cb' parallel zu den Halbleiterbauelementen aufweist. Zur Realisierung dieser Lösung ist z. B. eine zusätzliche zu den umgebenden Metallkaschierungen isolierte metallkaschierte Fläche auf dem Substrat vorzusehen, die mit der rückseitigen Metallkaschierung des Substrates die Kapazität Cb' bildet und mittels Bondverbindungen mit den Kathoden der jeweiligen Freilaufdioden des jeweiligen Schalters sehr niederinduktiv mittels Bonddraht verbunden ist. Fig. 5 shows a further inventive solution for detuning the oscillating circuit formed by the semiconductor devices by using two semiconductor components b through a connection with each other with per semiconductor device of a very low inductance L 'are connected, this connection at its center a further capacitance C b' parallel to the semiconductor components. To implement this solution, for. B. to provide an additional to the surrounding metal cladding insulated metal-clad surface on the substrate, which forms the capacitance C b 'with the back metal cladding of the substrate and is connected by means of bond connections to the cathodes of the respective free-wheeling diodes of the respective switch in a very low-inductance manner by means of bond wire.
Fig. 6 zeigt eine an sich bekannte Lösung zur Verstimmung des durch die Halbleiterbauelemente gebildeten Schwingkreises, indem zwei Halbleiterbauelemente mittels einer zusätzlichen Verbindung mit sehr geringer Induktivität Lb" direkt verbunden sind. Die einfachste Realisierung dieser Lösung bildet nach dem Stand der Technik (DE 199 38 302) eine direkte Bondverbindung z. B. zwischen den Kathoden der Freilaufdioden. Fig. 6 shows a known solution for detuning the oscillating circuit formed by the semiconductor devices by using two semiconductor components b means of an additional compound with very low inductance L are "directly connected. The simplest realization of this solution is formed by the prior art (DE 199 38 302) a direct bond connection, e.g. between the cathodes of the freewheeling diodes.
Fig. 7 zeigt eine Messung einer PETT-Schwingung erzeugt durch die Diodenrückstromspitze. Es ist der zeitliche Verlauf nach dem Einschaltens eines IGBTs gezeigt. VCE stellt den Spannungsabfall über dem IGBT (Kollektor-Emitter) dar. Die PETT- Schwingung ist ein Teil des Signalverlaufes der Kurve HF. Die PETT-Schwingung entsteht kurz vor dem vollständigen Abklingen des Diodenrückstromes, der in Summation mit dem Laststrom IC + IRR gezeigt. Die PETT-Schwingung ist hierbei über eine Antenne gemessen, deren Signal durch die Kurve HF beschrieben ist. Fig. 7 shows a measurement of a PETT vibration generated by the diode reverse current peak. The time course after switching on an IGBT is shown. VCE represents the voltage drop across the IGBT (collector-emitter). The PETT oscillation is part of the waveform of the HF curve. The PETT oscillation occurs shortly before the diode reverse current completely decays, which is shown in summation with the load current IC + IRR. The PETT vibration is measured via an antenna, the signal of which is described by the curve HF.
Claims (4)
mindestens zwei parallelgeschalteten Halbleiterbauelementen, die jeweils eine zusätzliche parallele Beschaltung durch eine Serienschaltung einer geringen Induktivität (Lb) und einer Kapazität (Cb) aufweisen und/oder
mindestens zwei parallelgeschalteten Halbleiterbauelementen, die durch eine Verbindung mit pro Halbleiterbauelement einer geringer Induktivität (Lb') verschaltet sind, wobei diese Verbindung in ihrem Mittelpunkt mindestens eine weitere Kapazität (Cb') parallel zu diesen Halbleiterbauelementen aufweist.1. Circuit arrangement for avoiding high-frequency vibrations in power semiconductor modules, the resonant circuit formed by the power semiconductor components being detuned by means of
at least two semiconductor components connected in parallel, each having an additional parallel connection by means of a series connection of a low inductance (L b ) and a capacitance (C b ) and / or
at least two semiconductor components connected in parallel, which are connected by a connection to each semiconductor component having a low inductance (L b '), this connection having at least one further capacitance (C b ') parallel to these semiconductor components at its center.
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DE10158374A DE10158374C1 (en) | 2001-11-28 | 2001-11-28 | HF oscillation prevention circuit for power semiconductor module uses inductors and capacitors for de-tuning oscillator provided by parallel semiconductors |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011058720A1 (en) * | 2009-11-11 | 2011-05-19 | Canon Kabushiki Kaisha | Semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5455757A (en) * | 1994-01-28 | 1995-10-03 | Compaq Computer Corp. | Power converter having regeneration circuit for reducing oscillations |
DE19549011A1 (en) * | 1995-12-28 | 1997-07-03 | Eupec Gmbh & Co Kg | Power semiconductor module with parallel IGBT chips |
DE29823619U1 (en) * | 1998-08-21 | 1999-09-30 | Semikron Elektronik Gmbh | Power semiconductor circuit arrangement with vibration-damped parallel connection |
-
2001
- 2001-11-28 DE DE10158374A patent/DE10158374C1/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5455757A (en) * | 1994-01-28 | 1995-10-03 | Compaq Computer Corp. | Power converter having regeneration circuit for reducing oscillations |
DE19549011A1 (en) * | 1995-12-28 | 1997-07-03 | Eupec Gmbh & Co Kg | Power semiconductor module with parallel IGBT chips |
DE29823619U1 (en) * | 1998-08-21 | 1999-09-30 | Semikron Elektronik Gmbh | Power semiconductor circuit arrangement with vibration-damped parallel connection |
DE19938302A1 (en) * | 1998-08-21 | 2000-03-02 | Semikron Elektronik Gmbh | Power semiconductor circuit with oscillation damped parallel circuit of IGBT power switches |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011058720A1 (en) * | 2009-11-11 | 2011-05-19 | Canon Kabushiki Kaisha | Semiconductor device |
US8786071B2 (en) | 2009-11-11 | 2014-07-22 | Canon Kabushiki Kaisha | Wiring pattern having a stub wire |
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