DE10154279A1 - Transferring STM1 signals between electronic components within unit or in different units in system involves bit-wise multiplexing SMT1 signals with time offset relative to each other - Google Patents

Abstract

The method involves arranging individual STM1 signals in frames consisting of overhead data with an identity word and useful data, multiplexing the signals in the individual main channels onto a faster serial communications channel and demultiplexing at the receiver end. The SMT1 signals of the relevant main channels are bit-wise multiplexed with a potential time offset with respect to each other. AN Independent claim is also included for the following: an electronic component, preferably an ASIC, FBGA, semi- or fully-customer specific component, with a circuit core for communicating with other components.

Description

Method for the transmission of n STM1 signals between electronic components within an assembly or between electronic components on different Assemblies within a system.

The invention relates to a method for transmitting n STM1 signals according to the preamble of the first Process claim and suitable electronic components according to the preamble of the first device claim.

It is known for the communication of SDH / SONET signals between electronic components and assemblies, especially between ASICs and FBGAs, signals in the same known STMn format to use, which consists of n aligned STM1 signals are multiplexed together. The well-known STM1 Format integrates the information to be transmitted into one binary frame consisting of 9 lines each 270-byte columns, each row with 9 bytes overhead and 261 bytes Useful information is included. The first line of an STM1 Signals contains a 6-byte long, defined Frame alignment. If there are several in one ASIC / FBGA at the same time STM1 sinals, for example of different ones Functional units of the ASIC / FBGA or parallel data streams Functional units, you multiplex n STM1 signals by byte at a time to an STMn signal, which is then serial and with corresponding high transmission rate (n.155 Mbps) is communicated. For this purpose, n STM1 signals are temporarily stored and then aligned with each other in a predetermined Sequence byte multiplexed and serial as STMn signal (e.g. STM4, STM16, STM64 or STM256 signal). The intermediate storage is necessary for a Perform synchronization between the n STM1 signals. This means, when multiplexing, the first byte of the first STM1 Signal, then the first byte of the second STM1 signal, etc. strung together until the second byte of the first STM1 signal etc. follows.

A major disadvantage of this method is that a lot of storage space for the temporary storage of the STM1 Signals is required and on the other hand also a Delay on the cached signal that occurs not with a signal path through several ASIC's / FBGA's add up negligibly.

It is therefore an object of the invention to provide a method for Transmission of n STM1 signals, which without one Buffer comes out and a time delay in the serial Avoids finding STM1 signals. Accordingly, a method for this inventive method suitable, electronic circuit arrangement (= partial circuit, or Module in the ASIC / FBGA).

This task is accomplished by a process with the characteristics of first procedural claim and an electronic Circuit arrangement with the features of the first Device claim solved.

Accordingly, the inventor suggests that which is known per se Method for serial transmission of a large number of parallel STM1 signals occurring on n main channels between sending and receiving modules (transmitter and receiver) in electronic components, in which the individual STM1 signals in Frames are arranged that consist of overhead and user data exist, and the overhead contains a frame password, and the STM1 signals of the individual main channels as binary Total signal sequence on a serial that is at least n times faster Communication channel multiplexed on the transmitter side and be demultiplexed at the receiver end to improve that at Multiplex the STM1 signals of the respective main channels possible temporal offset in the overall signal multiplexed bit by bit, transmitted serially and then at Receiver demultiplexed and the STM1 signals the main channels be assigned.

In a special implementation of the method suggested that in overhead each STM1 signal from the transmitter alongside the frame password an identification code (MID) for everyone Main channel added, i.e. H. in the existing and in his Structure unchanged frame is inserted, whereupon the Receiver assigns each STM1 signal to the main channel based on the identification code.

For security reasons, the validity can be verified the identification code due to the redundancy of the Codes are made, including a verification of validity the identification code due to its disjunctivity, that is, the uniqueness of the identification code can be d. H. no code value may be sent to the Main channels have been assigned. There is also the possibility of Validity of the identification code based on the order check the STM1 signals. Here the code values Awarded continuously, e.g. B.. , ., 0, 1, 2, 3, 0, 1,. , , According to the invention, only every nth STM1- Signal, e.g. B. the first STM1 signal of the main channel No. 0, in addition to the frame password, an identification code (MID) for get the main channel, then assigning the others STM1 signals is determined based on their order.

Furthermore, the method can also provide that before the Multiplexing the STM1 signals only scrambling the useful information and overhead parts, but not the Frame password and the identification code MID, and after the demultiplexing is a descrambling of these parts.

It is also proposed that the electronic Circuit received STM1 signals inside the module parallel signal buses word by word (e.g. 8 bits = 1 byte) per STM1- Signal and sequentially through the n STM1 signals (= Roller signal) first over a preceding one Reel signal resolution interface are routed and the over the Communication line received incoming STM1 signals after processing according to one of the above Process via a downstream roller signal generation Interface to be routed to a reel signal to be made available within the module. This Roll signal resolution or roll signal formation can also happen unilaterally, so only in the electronic transmitter element or only in the electronic receiver element.

In a special embodiment of the method, the Data of each main channel on m, preferably on 2, parallel ones Side channels can be divided. The ASIC / FGBA internal Processing speed is thus advantageously reduced the factor 1 / m per main channel.

The method described can advantageously be used if sending and receiving electronic Circuit arrangements in components (e.g. ASIC's / FBGA's) on one common circuit board or on different circuit boards (Boards) of an SDH / SONET system are arranged.

Strike according to the basic idea of the invention the inventors also proposed an electronic component, preferably ASIC or FBGA, with a circuit core from one Numerous networked internal functional units, which with Help of STM1 signals with other electronic Components, preferably ASICs or FBGAs, via a transmitter Strand and a receiver strand communicate, the STM1 signals occur in parallel and are numbered n per line (= sorted) internal main channels (transmitter / receiver ports) are assigned, multiplexers for the serial too sending STM1 signals from n main channels and demultiplexers are provided for the serial received STM1 signals, the STM1 signals being in frames consisting of overhead and User data exist, are arranged and the overhead one Framework password contains to further develop that on the multiplexer for the STM1 signals are designed so that the respective main channels with temporal offset to each other in the overall signal multiplexed bit by bit the demultiplexers for the STM1 signals are designed such that the received signals are demultiplexed bit by bit and a means for Assignment of the received STM1 signals to the main channels is provided.

According to an advantageous embodiment of the invention electronic component can also the main channels each of m, preferably 2, parallel secondary channels consist. As a result, the data rate per main channel is corresponding multiplied, or the ASIC / FBGA internal Processing speed is therefore advantageously reduced by Factor 1 / m per main channel.

In a further training it is provided that in means for at least one main channel of the transmitter strand Insert an identification code (MID) in the overhead of the these STM1 signals running at least one main channel is present and in at least one main channel of the Receiver strand a means for detection of the identification code (MID) in the overhead of this at least one main channel current STM1 signals.

In addition, a means for Insert (transmitter line) or for detection (Receiver line) of an identification code (MID) in the overhead the STM1- running over this at least one main channel Signals are provided. Accordingly, also in Receiver string an mx (nxn) switch with a controller (MID Control) should be provided, which is the assignment of the incoming STM1 signals to the correct main channels along with the n Modules MID detection and at the same time the correctness of the MID codes in the n STM1 signals monitored.

To with long continuous "0" or continuous "1" sequences Freedom from sampling synchronization error ("bit slip" avoidance) can also be reached in the main channels of the transmitter Srangs a scrambler and in the main channels of the receiver A descrambler can be interposed, whereby only the useful information and the overhead parts without Frame password and MID code of the STM1 signals scrambled and be descrambled.

Another embodiment of the electronic according to the invention Component provides that in the transmitter strand "Roll data to dual data" interface upstream and in the receiver Strand a "dual data to roll data" interface is connected downstream. Each dual data interface then corresponds to this a main channel, each consisting of m (e.g. 2) secondary channels.

It should be noted that the above Variable n preferably values of n = 4, 16, 64, 256, etc. can assume, however, any other integers are not excluded.

Further features of the invention result from the Subclaims and the following description of the Embodiments with reference to the drawings.

The invention will be described in more detail below with reference to the drawings described, specifically an ISDH4 signal (n = 4) between is transferred to the building blocks:

FIG. 1 shows architecture of a ISDH4 interface;

FIG. 2 shows architecture of a ISDH4 interface with roll data terminal to the core of the ASIC;

Fig. 3 architecture of an ISDH4 interface in roller technology.

For a better understanding of the invention, in particular the shown examples, first the structure of the serial ISDH4 signal transmitted between the blocks explained.

The ISDH4 signal is a structured signal that has four Contains STM1 single signals which are bit-wise, i. H. interleaved, are multiplexed. That means they are not byte by byte multiplexed as is the case in a standardized STM4 signal. In the ISDH4 signal, the four STM1 signals are usually frame or byte not aligned with each other, whereby random alignment is not excluded, as is the case with Example when connecting a measuring device can occur.

The four STM1 single signals contained in the ISDH4 signal are structured in a known manner as follows: the user data are packed in frames. These frames start with the 6th Byte long password RKW. Each frame is in 9 lines divided into 270 bytes each, each line begins with a 9 Byte-long overhead portion. Here is just the first overhead Line of importance, the rest of the frame is not here further notice, it is called "payload" transferred and treated.

According to the invention, a logical ISDH identifier is identified MID (multiple identifier detector) at least in every first of the four SDH overheads, each channel is unique. At the transmitter the channels are numbered, i. H. the MID code will used so that the channels are recognized again at the receiver and in the same sequence (= channel order) for the Transfer to the ASIC core can be arranged.

In the examples shown there is an accompanying measure, here from 78 to 622 MHz is provided, which also, e.g. B. with couplings can be omitted via the rear wall. Becomes an accompanying measure used, it is advantageous that the signal jitter of the transmitting PLL is directly coupled into the receive PLL, which can react quickly and compensate for this jitter.

Another advantage of direct coupling via one The accompanying measure is that in the event of a transfer of a unscrambled data stream that contains no signal changes (e.g. for AlS or UNEQUIPed), the receive PLL and the Phase aligners do not lose their phase alignment.

An accompanying cycle with a frequency of is advantageous here 311 MHz, since this then has the same spectral components than the 622 Mbps data signals used here. As a result, the clock signal characteristic is identical to that of the Data, and the signal difference between the data and the Clock is reduced.

When using an accompanying measure, the Scrambling of the useful information is eliminated.

For signal connections via the rear wall, a PLL Coupling also advantageous, but there would be many Accompanying clocks and additional receive PLLs required.

The sender and receiver PLL are not without an accompanying clock coupled with each other. To prevent that in the data stream no signal change for sequences of thousands of bits occurs, the data must be scrambled. Otherwise the receive PLL and the phase aligner can Lose phase alignment when a data stream is transmitted that contains no transitions (e.g. with AlS or UNEQUIPed).

As the well-known 622 Mbps receiver macros from the ASIC manufacturers a limit on the maximum allowable transfer of Continuous "0" - or - "1" sequences of e.g. B. have 60 bits, if there is no accompanying measure, here is one Scrambling necessary.

Fig. 1 shows the architecture, that is a module structure, an electronic component according to the invention, more precisely an ASIC regarding his communication interface with a transmitter-receiver strand 2 and strand 1 and the connected thereto core 14 of the ASIC.

Four (n = 4) STM1 signals formed in the ASIC core are processed for transmission from the bottom right and transmitted as an ISDH4 signal by an ASIC transmitter of the Core 14 at the bottom left. In return, an ISDH4 signal is created at the top left of the ASIC receiver, processed and then transferred to the ASIC core as 4 STM1 signals. The dual data connections and the clock feed are shown in the picture. Control signals accompanying the data and from the modules are not entered, with the exception of the MID control module.

A variant of the embodiment according to the invention from FIG. 1 is shown in FIG. 2, in which adapter modules 21 , 22 are inserted between the ASIC core 14 and the ISDH4 interface, which insert the ASIC core roller signal to be transmitted into the Adapt the dual data format and adapt the dual data format back into an ASIC core roller signal on the receiving side.

The two adaptation modules "roller interface to dual data" 22 and "dual data to roller interface" 21 of FIG. 2 can within their transmitter and receiver line between the ASIC core and the transmitter macro 24 or receive macro 3 can be moved as desired. The interface modules to the right of the adaptation modules are then to be switched to the roller mode of operation, the ones to the left are not. Which position is favorable or unfavorable depends on how well or badly the interface modules can be converted to roller technology.

Correspondingly, a variant is shown in FIG. 3, which internally largely transmits its data using roller technology. The method according to the invention can also be used here.

For system-internal data transmission between different ASICs each become four STM1 signals to form an ISDH4 signal summarized and serial together as a mixed signal transfer. The four STM1 signals, each sorted as one 78 MHz dual data signal, are sorted by their static given port number.

The four STM1 signals of an ISDH4 packet consist of one Frame with overhead and the payload. The overhead consists of a subset of the full SDH overhead, d. H. he is just as long, but is only partially or even filled with others. This is quite compliant.

Each individual STM1 frame begins with the frame password RKW, according to the SDH standard, a 6-byte fixed date. The immediately following 3 bytes of the overhead part of the First frame line are used for unique identification of the respective STM1 signal used. These positions are well suited for the MID code, basically suitable however, other positions within the SDH overhead. On Frame start pulse for an auxiliary counter (control signal) in the Scrambler can accompany any dual data signal are included. Instead of this, a MID byte enable Signal together with the 2 least significant digits of the dual Data bit frame counter are given. This saves you look at the parallel formation of the control signals in the Scrambler.

So the ISDH4 signal is a structured signal, the four Contains STM1 single signals, the so-called channels are allocated. These channels must be on the core of his Reception side again in the same order as you have been discontinued on the transmitter side, i.e. without being exchanged. Around to enable this must be in each or at least one STM1- Single signal a clear differentiator - one Code - to be inserted.

Such a logical ISDH identification code becomes MID (multiple identifier) called and identified in each of the four SDH overheads unique to each channel. Be at the transmitter the channels z. B. numbered (i.e. the MID code is used), at the receiver the channels can be the same sequence (= channel order) for the transfer the core are arranged. Alternatively, MID marks one Channel, e.g. B. channel 0, clear and the rest are so determined by the order.

The MID code to be inserted per channel is normally one Constant. Instead, the value could be from one of from the software loadable register. So that could here a channel switch function very easily and almost for free between these four channels. The software must then ensure that the content of these four MID Code registers always different and the values also valid are.

The MID code must not be scrambled. Therefore, it can only be shown in each STM1 single signal in the 3 bytes after the RKW and before the scrambled payload in the first line of the frame, i.e. in the byte position 7 , 8 or 9 of the STM1 signal, if scrambled becomes. If, on the other hand, you do not scramble, it could also be located elsewhere in the SDH overhead.

Each of the three byte positions mentioned above is basically logically equivalent. However, positioning can have an impact on implementation. A possibly necessary signal buffering may require shorter FIFOs if the first possible byte 7 is used. Therefore, byte 7 is preferably used as the MID position.

The currently used MID detection architecture and its Time behavior does not require buffering, however for future changes in behavior of this module there are no disadvantages. ASICs / FBGAs developed today can be easier with one later maybe modified ISDH4 architecture generation work together.

The values 0 to 3 are preferably used for the MID code uses the addressing of the 4 channels. But that's still does not determine the binary coding of these four values.

The four transmitter channels of the ISDH4 signal are now content completely formed. Before they can be sent, your Payload still to be scrambled.

In the implementation of the method according to the invention described here, the (m = 2) dual data signals of the four STM1 channels are XOR-linked independently of one another in a scrambler process in a 2-bit manner. The scrambler must therefore advance in the 2-bit parallel step. The 2-bit parallel scrambler required for this works in accordance with the serial scrambler according to ITU G70x, 6.5. The scrambler polynomial used is: 1 + x ⁶ + x ⁷ .

The 622 Mbps receiver macros from the ASIC manufacturers have a limit with regard to the maximum permissible transmission of continuous "0" or "1" sequences, e.g. B. 60 bits. You need edges in the data signal to readjust the receive clock generator for correct data clocking. Such sequences occur again and again in operation with AIS (continuous "1" sequence) and UNEQUIPED (continuous "0" sequence). Without regular edges in the input signal and without an accompanying clock, the receiver PLL does not come into play, for example, from a 60 bit continuous "0" or "1" sequence, the phase aligner cannot be readjusted, bit slips are then to be expected , This is the reason why the payload part of the frames has to be scrambled. Strictly speaking, after the first 9 frame bytes, the entire rest of the frame is scrambled and only the overhead in the first frame line remains excluded. With these first 9 bytes of the beginning of the frame, care must be taken to ensure that there are no long duration "0" or "1" sequences that have more than 15 bits. The following applies to the maximum permissible length 15 : if the 4 STM1 signals are unfavorably arranged, i.e. aligned with each other, then they add up to 4 times 15 equal to the limit of the permitted 60 bits.

However, an ISDH4 signal / ISDH4 signal bundle is included provided an accompanying clock, then the receiver PLL can use it be synchronized. A receive data stream can then be closed stay in phase for a very long time in its phase aligner cycle Transmission of 80,000 bits (exactly 77,760 bits ISDH4 frame length - 288 bits for overhead part) Permanent "0" or - "1" should cause no problems. Scrambling is one Accompanying measure is not necessary, but it does no harm.

For example, one can be implemented for each channel 2-bit parallel, non-blanket scrambler can be used.

The ISDH4 signal is now processed accordingly, it will the parallel / serial converter of the transmitter macro of the Appropriately supplied by the manufacturer and is then from this module sent out to the ASIC. The 4 dual data signals are in the 4-way distance to connect to the P / S port.

By means of a frequency multiplication (PLL circuit) generates an internal 622 MHz signal which is used to send the ISDH4 signal data stream is used. This generated 622 MHz clock signal can be divided down (usually by a power of two m) and can then be assigned to the 622 Mbps signal Bundles are given as accompanying clock signal. With help of the accompanying clock signal, the receiver PLL can be very sync well.

The board- or system-local symmetrical-electrical ISDH4- Signal with 622 Mbps is from an LVDS receiver (LVDS = Low Voltage Differential Signal) received and in one prepared manufacturer-specific macro. These macros included usually a phase aligner, a PLL, an S / P- Converters and can still use bit and frame aligners etc. include. It will refer to the extensive manufacturer literature directed.

This becomes serial in the internal S / P module of the receiver incoming ISDH4 signal converted to an 8-bit bundle, i.e. H. parallelized by a factor of 8, its data with a supplied clock of 78 MHz are to be adopted. The frequency of 78 MHz leaves a relative for the following modules problem-free circuit synthesis too.

In the ISDH4 signal receiver macro, the edges of the ISDH4 data signal the clock recovered if no Accompaniment clock is available and comes from a PLL circuit. This is why this clock is not seen in short-term terms extremely stable, in contrast to the long-term Frequency mean, which is normally based on a cesium normal based. The PLL clock "breathes" around the target frequency of 622 MHz and can have a maximum phase shift stroke of one Have multiples of a 622 MHz clock period. That beat is reduced by a factor of 8 and then forms the suitable, "floating" accompanying clock to the 4 × 2-bit date.

To adapt the data from the receiver module - the in sync with the 78 MHz clock supplied with the receiver module run and are derived from the receiver PLL - to the ASIC-internal system clock basis is a FIFO buffer memory for Equalization inserted. The necessary depth of this The buffer memory is dependent on the maximum Phase shift stroke of the received signal and the caused thereby maximum clock phase difference in the supplied clock.

The buffer depth depends on the selected ASIC Manufacturer and the physical parameters of the PCB, as well as the dimensioning parameters (e.g. Conductor width, layer thickness, etc.) and is also influenced from the connector choice.

During commissioning and every new one The ring buffer used must be re-synchronized to the STM1 frame be adjusted to the center position. For test purposes and special Applications can bridge this buffer function, so logically switched off, be executed. According to the ISDH4 Interface the date of a so-called pointer machine fed, d. H. the date is entered in a memory, then this module can be omitted completely, it must then Receiver clock from the PLL of the receiver macro for everyone Modules of the ISDH4 interface can be used.

The FAS module (Frame Align Sequence Module) searches the incoming dual data stream on the frame password (RKW). There the random phasing in of the receiving module (bit orientation between send byte to receive byte from sender to Receive macro) is initially unknown, the dual data stream be checked in parallel twice for the RKW, namely once not offset, i.e. starting on the first bit of the Dual data stream, and at the same time offset, i.e. starting on the second bit of the dual data stream. For the output dual Data stream is the offset data stream using a buffering element aligned.

• a) Man detektiert das Auftreten von 2 Bytes (A1, A2) im Datenstrom, meist mit Suchfenster, um Miss-Hits zu reduzieren;
• b) Man detektiert das Auftreten von 4 Bytes (A1, A1, A2, A2) im Datenstrom;
• c) Man detektiert 6 Bytes (A1, A1, A1, A2, A2, A2) im Datenstrom.

The frame password RKW for the STM1 data streams of the ISDH4 signals is composed of 6 bytes (A1, A1, A1, A2, A2, A2). Three methods a), b) and c) are preferred for synchronizing to the frame, but more are possible:

• a) One detects the occurrence of 2 bytes (A1, A2) in the data stream, usually with a search window, in order to reduce miss hits;
• b) The occurrence of 4 bytes (A1, A1, A2, A2) is detected in the data stream;
• c) 6 bytes (A1, A1, A1, A2, A2, A2) are detected in the data stream.

In the example described, the detection is at 78 MHz performed the dual data stream.

The RKW search of the FAS module found the beginning of the frame and is "locked", then the phase position in the 2-bit 78 MHz data stream known. So this can Dual data stream can now be aligned. This is still happening within of the FAS module by a downstream so-called 2: 2 Multiplexer (2 inputs: 2 outputs) in 2 ways.

A "normal" multiplexer would make the inputs simple Switch "straight" to the outputs or the inputs "via Connect the cross "to the outputs. This is not the case here. Here the 2-bit width input data is one 3-bit width register on the second and third bit positions fed, the output of the third register bit is in the first register bit shifted. The so-called" Multiplexing consists of the function that either the first and second or the second and third register bit tapped becomes. This is the original assignment of the sequence restored.

The following modules "MID-Detection" and "DeScr" must so that it does not have a double structure, for the following switch module "Mux" is submitted doubled 4: 4 multiplexer, so it's not a full 8: 8 Multiplexer more required, which also has the m = 2 channel bits could swap. In total, the multiplexer effort is for the four 2: 2 and the 2 × 4: 4 multiplexers are the same, only that through this division, the effort for the MID detection approximately is halved.

The task of MID detection (MID detection) is to read the MID code from the data stream of the channel, check this code for correctness and with the ensures correct MID code then the data stream of this input Channel in the subsequent channel switch module Mux see above switch through that all channels the core in the correct Sequence {0, 1, 2, 3} can be supplied.

The comes from the frame alignment sequence module FAS aligned channel dual data stream to the MID detection module. The FAS also delivers a control signal MID Enable, with which the MID code read into a 2-bit parallel shift register can be. This signal is closely related to RKW detection coupled.

The MID code is generated from the data stream in the MID detection module read out, checked for each channel and if necessary in the channel-associated MID code register.

In addition to the channel-specific checks, you can also parent tests for disjunctivity (i.e., is not a MID code Assigned multiple times, each value only occurs exactly once) MID codes of all four channels and on the cyclical order the same are carried out. However, if the channel Switch function (see channel switch module) is installed, then the cyclical check must be switched off be to enable free interconnection. this will accomplished in the MID control module. In case of an error there will be an interrupt signal is activated. From one of these module types MID detection or MID control then the channel Switch module controlled.

The following happens in the MID detection module: The MID enable Signal is active for 4 cycles and causes the clocking in of 4 × 2 bits of the corresponding channel dual data stream in one Shift register MID-Shift-Reg. The MID shift reg is 8 bits long and contains the so-called MID code from the Current frame, which indicates which channel number this Receive channel (and also originally as a send Channel, if not the channel switch function is installed).

The content of the MID shift reg is based on a suitable one Procedures in the 4-bit wide MID code reg are adopted. This is the actual register for storing the MID Codes with the value of this channel in the subsequent switch is switched through.

The functions of the MID detection module are such designed that in the MID code reg only a secured value with which the subsequent switch module and the MID control module can be controlled reliably. The in-depth discussion of these functions forms the basis of one separate registration of this item.

Have all four channels found their MID code, i. H. there are all four MID code reg with an apparently valid value then the four MID codes for disjunctivity and if necessary, checked for cyclical arrangement. Are these both requirements are not given, which in one proper detection but must be met, then a maskable MID alarm triggered.

With proper MID detection either none or all of the MID codes correctly recognized and inserted into the MID Code reg's of the four MID detection modules entered. The Checks whether all active channels are disjoint to each other and whether they are cyclical Order are loaded correctly, these control tasks can Quite easy from any two active channels be performed. However, after you can assume that "always" all four channels appear at the same time is one more complex partial controllability not necessarily required.

• - Alle Kanäle sind aktiv
• - Alle Kanäle sind disjunkt
• - Alle Kanäle sind zyklisch angeordnet
• - Generierung des MID-Alarm-Signals.

The following alarm situations are limited to the essential situation: "All four or none!". The following messages can thus be output:

• - All channels are active
• - All channels are disjoint
• - All channels are arranged cyclically
• - Generation of the MID alarm signal.

The four STM1 channels, implemented by two aligned 78 MHz data signals, regarding channel sorting can be received in any position. But these channels are sorted by module: d. that is, channel # 0 can be on everyone Input position, but they are cyclical to each other sorted. The input channel number assignment results by: input position channel i = (input position of Channel 0 + i) modulo 4 ℼ i ∈ {0,. , ., 3}

The channel switch must be installed twice for the data paths, for each group of the two aligned 78 MHz data signals one is required. The channel-specific Frame reference signals - generated by the FAS module - must use the dual Data carried and thus also multiplexed become.

The easiest way to do this is with a simple 4-way 4: 4 multiplexer - a multiplexer with 4 inputs and 4 outputs - used become. It consists of four individual multiplexers (4: 1, each with an exit), each of which relates to each of the four possible inputs directly, i.e. via 4 Entrance ways.

As shown above, the Payload of the four STM1 signals must be scrambled. In addition, the scrambling is channel-specific handle. A good place to get the recipient Scrambling of the transmitted signal again channel-specific Undo is after the switch, i.e. H. after Channel sorting.

This statement that the space behind the switch is optimal is selected, however, only applies if the channel numbers are static according to the order of the four channels should. Usually this is meaningless if all four STM1 signals contain a correct MID code. in the Not an error, however.

Assuming that an STM1 signal with an incorrect one MID code was provided and with this also the starting value for this channel-specific scrambler has been selected, then a different starting value due to the current static definition used and the payload is thus scrambled back incorrectly. But once you have decided on this method, then it is this solution and position for the DeScr module is therefore optimal chosen because then for each DeScr module the MID code and so that the starting value is also calculated statically, i.e. as Constant value can be synthesized in the circuit. The Probability of a channel despite an incorrect MID code scrambled back correctly is so much bigger.

Another favorable position of the DeScr module can also immediately after the MID detection modules, so still in front of the channel switch module. The big difference is in that the actually detected MID code is easy here can be used for descrambling. He wouldn't have to can also be carried as a variable via the switch. This would double its implementation effort. The starting value for the descrambler is of course in this case with help of the MID code.

The advantage of this solution can be seen as follows: Was in that Incorrect MID code inserted in the data signal or the signal incorrectly sorted in the ISDH4 signal and the data stream included scrambled exactly this MID code when starting value formation, then it will now return to the correct data signal zurückgescrambled. This channel is controlled by the MID control logic now on a "free", so to speak. H. in the event of an error otherwise unused channel switched through, then comes immediately a properly descrambled signal - with the first solution would do so if using an incorrect seed send a nonsensical signal.

In the example shown there is a 2-bit parallel, non-gaping descrambler used. The descrambler is largely identical to the scrambler, since the scrambler Function (= XOR) is symmetrical.

The ISDH4 input signal is now processed and ready Core is now available in its original form again Form of four STM1 signals, each as a sorted 78 MHz Data signal pair. The channels are sorted by their Channel numbers, i.e. H. according to their MID codes. They appear here now just like the transmitter ASIC.

Another variant in complete roller technology is shown in FIG. 3. Here, an ISDH4 roller signal formed in the ASIC core is prepared for transmission from the bottom right and sent out as an ISDH4 signal by the ASIC transmitter. In return, an ISDH4 signal is applied to the top left of the ASIC receiver, processed and then transferred to the ASIC core. An additional TX-Buf module is required for ISDH4 transmit signal formation. In principle, it is necessary on the receiver side, a RX-Buf module must be inserted here. This RX-Buf function can also be integrated into the taktan module. Moving the RX_Buf module behind taktan would have the advantage that the time-critical clock jitter is kept away from RX_Buf. A jitter simulation can then be omitted, since it has already been tested on a tactical basis.

For system-internal data transmission between different ASICs are each four independent, so not necessarily aligned STM1 signals to an ISDH4 roller Signal summarized and transmitted. Contains this signal cyclically each 8 bits of a channel, these channel bytes are transmitted sequentially multiplexed at 78 MHz. concomitant at least one frame start pulse signal is provided, a would be an additional MID enable and payload signal desirable.

The four independent STM1 signals contained in the roller signal each consist of a frame with overhead and the payload, usually a VC ₄ container. The overhead consists of a subset of the complete SDH overhead, ie it is just as long, but is only partially or even externally filled. Each frame begins with the RKW, according to the SDH standard, a 6 byte long date. The immediately following 3 bytes of the overhead part of the first frame line later contain the MID code.

The following MID insertion module must add the channel number know each data byte, so there must be 2 channel number signals be given.

Once the ISDH4 input signal has been processed, it is again available to the ASIC core in its initial form in the form of four STM1 signals, each as a multiplexed data byte in the 78 MHz roller data signal. The channels are sorted according to their channel numbers, ie according to their MID codes. They now appear here just as they were sent to the transmitter ASIC. In the examples shown here, the 4 STM1 signals are transmitted in parallel as a sequence of octets, an octet 8 forming bits of the ISDH4 signal immediately following one another in time and in the transmitting or receiving module, of which the first in time ( 1st . 4 ) and the last 4 ( 5 ... 8 ) are each assigned to exactly one separate channel, in the order of the first and second 4 bits each to the same channel.

In the descrambler process, a clock offset becomes automatic taken into account because the RKW detections of the affected channels in the FAS module then also be offset by one cycle and the "bit offset" is also recognized, the Descrambler accordingly synchronously, also by 1 clock moved, started and the 2: 2 multiplexer in the FAS module controlled accordingly. The channel-specific Frame reference signals - generated by the FAS module - stand for each STM1 channel Entrance available.

Overall, a method and an electronic component or circuit arrangement for the serial transmission of STM1 signals are proposed, the STM1 signals being arranged in frames which consist of overhead and user data, and the overhead contains a frame password, and the individual main channels as binary Total signal sequence on an n times faster serial communication channel are multiplexed on the transmitter side and demultiplexed on the receiver side. According to the invention, in the case of multiplexing, the STM1 signals of the respective main channels are multiplexed bit by bit, serially transmitted and then demultiplexed at the receiver, with the possible time offset in the overall signal, and the STM1 signals are assigned to the main channels. Reference Signs List 1 receiver strand
2 transmitter line
3 receive macro (manufacturer-specific)
4 receiver PLL
5 phase aligners
6 serial / parallel converters
7 bar divider
8 tactan (buffer memory, FIFO)
9 FAS (+2: 2 multiplexer)
10 MID detection
11 MID control
12 multiplexers 2 × 4: 4
13 Descrambler
14 core of the ASIC
15 78 MHz internal clock line T0x / T0y
16 transmitter PLL
17 clock divider
18 parallel / serial converter
19 Scrambler
20 MID inserters
21 Dual data / roller interface converter
22 reel / dual data interface converter
23 receive buffer
24 transmit buffers
25 transmitter macro (manufacturer-specific)

Claims (18)

1. Method for the serial transmission of a plurality of STM1 signals occurring in parallel on n main channels between transmitting and receiving modules ( 2 , 1 ) in electronic components, wherein
the individual STM1 signals are arranged in frames, which consist of overhead and user data, and the overhead contains a frame password,
the STM1 signals of the individual main channels being multiplexed as a binary total signal sequence onto an at least n times faster serial communication channel on the transmitter side and demultiplexed on the receiver side,
characterized by
that when multiplexing, the STM1 signals of the respective main channels are multiplexed bit by bit, serially transmitted and then demultiplexed at the receiver ( 1 ) with a possible time offset in the overall signal, and the STM1 signals are assigned to the main channels. 2. The method according to the preceding claim 1, characterized in that in the overhead of each STM1 signal from the transmitter ( 2 ) in addition to the frame password, an identification code (MID) is inserted for each main channel and the assignment of each STM1 signal to the receiver ( 2 ) Main channel based on the identification code. 3. The method according to claim 2 above, characterized, that a verification of the validity of the Identification codes based on redundant codes. 4. The method according to any one of the preceding claims 2-3, characterized, that a verification of the validity of the Identification codes due to the disjunctivity of the identification code he follows. 5. The method according to any one of the preceding claims 2-4, characterized, that a verification of the validity of the Identification codes are made based on the order of the STM1 signals. 6. The method according to the preceding claim 1, characterized, that in the overhead only every nth STM1 signal next to the Frame password an identification code (MID) for the main channel receives and the assignment of the other STM1 signals based on their order is determined. 7. The method according to any one of the preceding claims 1-6, characterized, that the data of each main channel on m, preferably 2, parallel secondary channels can be divided. 8. The method according to any one of the preceding claims 1-7, characterized, that scrambling before multiplexing the STM1 signals excluding the useful information and the overhead parts, but not the frame password and the identification code MID, and after demultiplexing, descrambling these parts he follows. 9. The method according to any one of the preceding claims 1-8, characterized, that the STM1- received by the electronic circuit Signals inside the block in word bus in parallel signal buses (e.g. 8 bits = 1 byte) per STM1 signal and sequentially through the n STM1 signals (= roller signal) initially via Roller signal resolution interface and the incoming STM1 signals after processing according to one of the above-mentioned method via a roller signal generation Interface to be routed to a reel signal to be made available within the module. 10. The method according to any one of the preceding claims 1-9, characterized in that the sending and receiving electronic circuit arrangements ( 2 , 1 ) in components (z. B. ASIC's / FBGA's) are arranged on a common circuit board. 11. The method according to any one of the preceding claims 1-9, characterized in that the sending and receiving electronic circuit arrangements ( 2 , 1 ) are arranged in components on different circuit boards (boards) of an SDH / SONET system. 12. Electronic component, preferably ASIC, FBGA, semi- or fully customer-specific component, with a circuit core ( 14 ) made up of a large number of networked internal functional units, which with the aid of STM1 signals with other electronic components, preferably ASICs or FBGAs, communicate via a transmitter line ( 2 ) and a receiver line ( 1 ),
where the STM1 signals occur in parallel and are assigned n numbered (= sorted) internal main channels (transmitter / receiver ports) per line, furthermore multiplexers ( 18 ) for the serial STM1 signals to be sent from n main channels and demultiplexers ( 6 ) for the serially received STM1 signals are provided,
wherein the STM1 signals are arranged in frames consisting of overhead and user data and the overhead contains a frame password, characterized in that
that the multiplexers ( 18 ) for the STM1 signals are configured on the transmitter line ( 2 ) in such a way that the respective main channels are multiplexed bit by bit in the overall signal with a possible time offset, and
on the receiver line ( 1 ), the demultiplexers ( 6 ) for the STM1 signals are designed in such a way that the received signals are bit-demultiplexed and a means ( 10-12 ) is provided for assigning the received STM1 signals to the main channels. 13. Electronic component according to the above Claim 12, characterized, that the main channels each consist of m, preferably 2, parallel secondary channels exist. 14. Electronic component according to one of the preceding claims 12-13, characterized in that in at least one main channel of the transmitter line ( 2 ) means for inserting an identification code (MID) ( 20 ) in the overhead of the STM1 running over this at least one main channel - Signals is provided and in at least one main channel of the receiver line ( 1 ) a means for detecting the identification code (MID) ( 10 ) is provided in the overhead of the STM1 signals running over this at least one main channel. 15. Electronic component according to the preceding claim 14, characterized in that a means for inserting or for detecting an identification code (MID) ( 20 ) is provided in the overhead of the STM1 signals running over these main channels in each of the main channels. 16. Electronic component according to one of the preceding claims 12-15, characterized in that in the ( 1 ) a px (nxn) switch ( 12 ) with a control (MID control) ( 11 ) is provided, which the assignment of the incoming Carries out STM1 signals to the correct main channels together with the n modules MID detection ( 10 ) and at the same time monitors the correctness of the MID codes in the n STM1 signals, the variable p> = m. 17. Electronic component according to one of the preceding claims 12-16, characterized in that in the main channels of the transmitter line ( 2 ) scrambler ( 19 ) and in the main channels of the receiver line ( 1 ) descrambler ( 13 ) are provided, wherein only the user information and the overhead parts without frame password and MID code of the STM1 signals are treated. 18. Electronic component according to one of the preceding claims 12-17, characterized in that a "roller data to dual data" interface ( 22 ) is connected upstream in the transmitter line ( 2 ) and / or an "in the receiver line ( 1 )" Dual data to roller data "interface ( 21 ) is connected downstream.