DE10149938A1 - Circuit arrangement for contactless chip card has charge pump circuit with amplifier stages with pump nodes, charge reservoir circuit with coupling nodes coupled pump nodes - Google Patents

Abstract

The circuit arrangement has a first charge pump circuit with a first amplifier stage with a first pump node, a second amplifier stage with a second pump node and a charge reservoir circuit with a first coupling node coupled to the first pump node and a second coupling code coupled to the second pump node. The pump nodes store excess charge carrier. AN Independent claim is also included for the following: a contactless chip card with an inventive circuit arrangement.

Description

The invention relates to a circuit arrangement and a contactless chip card.

The conventional silicon microelectronics continues at progressive reduction reach their limits. In particular, the development of increasingly smaller and denser ones arranged transistors of several hundred million Transistors per chip will be in the next ten years be exposed to fundamental physical problems. If Structural dimensions of 80 nm are undercut the components are affected by quantum effects and dominated below dimensions of about 30 nm. In particular, the increasing integration density of Components on a chip lead to a dramatic increase in Waste heat.

A concept to reduce the energy consumption of one Circuit for the successive supply or discharge of electrical charge carriers on electrical nodes of the Circuitry is the concept of adiabatic Circuit technology, by means of compared to conventional Circuits the power consumption is reduced. A Provide an overview of the adiabatic circuit technology for example [1] and [2].

A basic idea of adiabatic circuit technology exists in it on an electrically charged circuit node stored electrical energy when unloading the node not to dissipate, but instead in one so-called power clock and store it in one subsequent switching cycle at least partially in feed the circuit. A power clock can for example based on an LC circuit in which the potential energy contained in the circuit node can be saved, and at a later date the Circuit nodes can be provided again. This Principle of adiabatic circuit technology respectively the adiabatic dynamic logic is for example in [3] or described in [4].

A significant part of that from a conventional circuit consumed energy requirements is "on-chip" provided circuits for generating one opposite a supply voltage increased output voltage consumed. Such voltage amplifiers to increase one Supply voltage are in many integrated circuits required. For example, voltage amplifiers occur Increase a supply voltage by approximately four to six times in EEPROMs and flash memories. For example electrical voltages are significantly higher than those on Circuits usually provided Supply voltages required to program EEPROMs or delete.

In particular, so-called charge pumps are used to Increase supply voltages.

Referring to Fig. 1A, Fig. 1B is a boosted charge pump is described below as it is known for example from [5], [6].

The boosted charge pump 100 has a first input 101 to which an input voltage V _{0 is} applied and has an output 102 to which an output voltage V _{1 is} provided. Furthermore, the boosted charge pump 100 has a second input 103 to which a first electrical pump pulse p1 can be applied and has a third input 104 to which a second electrical pump pulse p2 can be applied. The boosted charge pump 100 also has a fourth input 105 , to which a first electrical switching pulse n1 can be applied. A second electrical switching pulse n2 can be applied to a fifth input 106 . The first switching pulse n1 is also applied to a sixth input 107 , and the second switching pulse n2 is applied to a seventh input 108 . Furthermore, the boosted landing pump 100 has a first pump capacitor 109 , a second pump capacitor 110 , a third pump capacitor 111 and a fourth pump capacitor 112 . The first pump capacitor 109 and the third pump capacitor 111 are coupled to the second input 103 , to which the first pump pulse p1 is applied, whereas the second pump capacitor 110 and the fourth pump capacitor 112 are coupled to the second input 104 , to which the second pump pulse p2 is applied. In addition, the boosted charge pump 100 has a first switching capacitor 113 , a second switching capacitor 114 , a third switching capacitor 115 and a fourth switching capacitor 116 . The first switching capacitor 113 is coupled to the fourth input 105 , the second switching capacitor 114 is coupled to the fifth input 109 , the third switching capacitor 115 is coupled to the sixth input 107 , and the fourth switching capacitor 116 is coupled to the seventh input 108 . The first pump capacitor 109 is coupled to the gate region of a first switching transistor 117 via a first storage node 121 . The second pump capacitor 110 is coupled to the gate region of a second switching transistor 118 via a second storage node 122 . The third pump capacitor 111 is coupled via a third storage node 123 to the gate region of a third switching transistor 119 , and the fourth pump capacitor 112 is connected to the gate region of a fourth switching via a fourth storage node 124 -Transistor 120 coupled. The first source / drain region of the first switching transistor 117 is coupled to the first input 101 , and the second source / drain region of the first switching transistor 117 is connected to the gate region of a first control transistor 125 and coupled to the first switching capacitor 113 . The first source / drain region of the first control transistor 125 is coupled to the first input 101 , and the second source / drain terminal of the first control transistor 125 is coupled to the first memory node 121 . Furthermore, the first storage node 121 is coupled to the first source / drain region of a second control transistor 126 , the gate region of which is connected to the second switching capacitor 114 and to the second source / drain region of the second switching transistor Transistor 118 is coupled. The first source / drain region of the second switching transistor 118 is coupled to the first storage node 121 . The second source / drain region of the second control transistor 126 is coupled to the second memory node 122 , which is further coupled to the first source / drain region of the third switching transistor 119 . Furthermore, the second storage node 122 is coupled to the first source / drain region of a third control transistor 127 , the gate region of which is connected to the second source / drain region of the third switching transistor 119 and to the third switching transistor Capacitor 115 is coupled. Furthermore, the second source / drain region of the third control transistor 127 is coupled to the third memory node 123 , which is furthermore connected to the first source / drain region of the fourth switching transistor 120 and to the first source / drain Region of a fourth control transistor 128 is coupled. The gate region of the fourth control transistor 128 is coupled to the second source / drain region of the fourth switching transistor 120 and to the fourth switching capacitor 116 . The second source / drain region of the fourth control transistor 128 is coupled to the fourth memory node 124 , which is furthermore coupled to the first source / drain region of an auxiliary transistor 129 and to the gate region of the Auxiliary transistor 129 is coupled. The second source / drain region of the auxiliary transistor 129 is coupled to the output 102 .

The boosted charge pump 100 shown in FIG. 1A has the functionality to provide an output voltage V ₁ amplified in four amplifier stages compared to the input voltage V _{0 present} at the first input 101 at the output 102 . These four stages are shown schematically in the circuit diagram of FIG. 1A as first amplifier stage 130 , second amplifier stage 131 , third amplifier stage 132 and fourth amplifier stage 133 .

The operation of the boosted charge pump 100 from FIG. 1A is described in detail below.

In Fig. 1B, a timeline 140 is shown, along which is shown p2, the time dependence of the switching pulses n1, n2 and the pump pulses p1.

At a time t ₁ , which is illustrated along the time axis 140 from FIG. 1B, the first pump pulse p1 goes from a logic value "0" to a logic value "1", and the first switching pulse n1 goes from a logic value "0 "to a logical value" 1 ". Since the first pump pulse p1 goes to a logic value "1", the first storage node 121 is brought to an increased electrical potential via the first pump capacitor 109 , and the first switching transistor 117 becomes conductive. Since the first switching transistor 117 is conductive, an electrical current flow between the first source / drain region of the first switching transistor 117 and the second source / drain region of the first switching transistor 117 is made possible, so that the gate Region of the first control transistor 125 is at the potential V ₀ . Therefore, both the first source / drain region and the gate region of the first control transistor 125 are at an electrical potential V ₀ . The first pump pulse p1 applied to the first storage node 121 therefore causes an electrical current to flow between the first source / drain region of the first control transistor 125 and the second source / drain region of the first control transistor 125 . ie according to the illustration of FIG. 1A is from left to right, possible. In other words, the first control transistor 125 functions as a diode, which only allows a current to flow from the first input 101 to the first storage node 121 , whereas an electrical current flow from the first storage node 121 to the first input 101 does not is possible. Therefore, the first storage node 121 is at an electrical potential of approximately V ₀ . During the charge exchange along the conductive channel of the first control transistor 125 , the first switching pulse n1 is also at a logic value "1", so that the electrical potential of the gate region of the first control transistor 125 is increased compared to the electrical potential V ₀ , As a result, the electrical resistance in the case of an electrical current flowing between the first source / drain region and the second source / drain region of the first control transistor 125 is reduced, so that the voltage drop across the first control transistor 125 is reduced , In other words, the gate voltage of the first control transistor 125 is increased by means of the first switching pulse n1 and thereby reducing the voltage drop at the first control transistor 125th Therefore, the first storage node 121 is brought approximately to the electrical potential V ₀ when the voltage drop across the first control transistor 125 is negligibly small.

At time t ₂ shown in FIG. 1B, the switching pulse n1 is brought from a logic value "1" to a logic value "0", whereas the first pump pulse p1 remains at the logic value "1" and therefore the first pump capacitor 109 remains charged.

The pump pulse p1 lying at the logic value "1" has the effect that the electrical potential at the first storage node 121 is brought to a value which is higher than the value V ₀ . Since the first control transistor 125, which acts like a diode, does not allow a current to flow from left to right in accordance with FIG. 1A, the electrical charge additionally applied to the first storage node 121 does not flow out via the first control transistor 125 . In other words, at the end of the first amplifier stage 130 of the boosted charge pump 100, the electrical potential at the first storage node 121 is increased compared to the electrical potential V ₀ applied at the input 101 .

The functionality of the second amplifier stage 131 , the third amplifier stage 132 and the fourth amplifier stage 133 of the boosted charge pump 100 corresponds to the functionality of the first amplifier stage 130 . In other words, the electrical voltage present at the respective electrical storage node 121 , 122 , 123 , 124 is successively increased from amplifier stage to amplifier stage, so that the electrical voltage V ₁ provided at the output 102 compared to that at the first Input provided voltage V _{0 is} increased in several stages. In order to clearly shift the electrical potential according to FIG. 1A from left to right and to increase it successively, the pump capacitors 109 , 110 , 111 , 112 are periodically charged and discharged, as can be seen from the time dependence of the pulses from FIG. 1B is.

The boosted charge pump 100 shown in FIG. 1A generates a boosted electrical voltage with a positive sign. The generation of an amplified electrical voltage with a negative sign is known in an analogous manner from the prior art.

The boosted charge pump 100 shown in FIG. 1A requires the complex four-phase timing scheme of the switching pulses n1, n2 and the pump pulses p1, p2, which is shown in FIG. 1B. A complex logic circuit is required to generate this clock pattern.

In FIG. 2 a well-known from the prior art driver circuit 200 is shown for generating a pumping pulse p1. A clock signal φ is applied to an input 201 of the driver circuit 200 . This passes through a first inverter stage 202 and a second inverter stage 203 and then arrives at a first electrical node 204 . The first electrical node 204 is coupled to the gate region of a p-MOS transistor 205 and is coupled to the gate region of an n-MOS transistor 206 . The first source / drain region of the p-MOS transistor 205 is at the electrical potential of a supply voltage V _dd 207. The second source / drain region of the p-MOS transistor 205 is coupled to a second electrical node 208 . The second electrical node 208 is coupled to the first source / drain region of the n-MOS transistor 206 , the second source / drain region of which is at a ground potential (0 volt) 209 . Furthermore, the second electrical node 208 is coupled to the input node 103 a shown in FIG. 1A, at which a pump pulse p1, as shown in FIG. 1B, is provided by means of the driver circuit 200 .

The reference to Fig. 1A, Fig. 1B, Fig. 2 described boosted charge pump 100 and the space required to generate the requisite pulse driver circuit 200 have a number of disadvantages. The logic for generating the pump pulses or the four-phase clock scheme is very complex. Furthermore, the charge pump 100 in combination with the driver circuit 200 has a relatively low efficiency. The efficiency of charge pumps known from the prior art, driven by a driver circuit, is approximately 45%, taking into account the losses for clock generation and the driver circuit. For example, since approximately 30% to 40% of the power is used to generate electrical voltages which are higher than the supply voltage in the case of flash EEPROMs, poor efficiency of the charge pumps and the circuits connected to them has a negative effect on the overall required energy consumption of the chip. This is particularly disadvantageous for battery-operated devices.

The losses of a boosted charge pump 100 together with the driver circuit 200 are made up of the losses of the clock generation, the driver circuit 200 and the boosted charge pump 100 . The losses of the driver circuit 200 are often dominant, since large transistors with high capacitances are present therein. These capacities have to be loaded and unloaded periodically.

In order to increase the efficiency of a boosted charge pump driven by a driver circuit, the so-called charge sharing concept is described in [7]. This concept is described by way of example with reference to FIG. 1B. The time t ₃ shown in FIG. 1B corresponds to a scenario in which the first pump capacitor 109 is discharged (p1 goes from a logic value "1" to a logic value "0"), whereas the second pump capacitor 110 is charged becomes (p2 goes from a logic value "0" to a logic value "1"). According to the principle of charge sharing between the pump capacitors 109 and 110 , the first pump capacitor 109 which is still charged is not discharged against ground potential as in the pump principle described above, but the charge stored thereon is transferred to the second pump via a switching element. Brought capacitor 110 . If the first pump capacitor 109 was previously at an electrical potential V _dd and the second pump capacitor 110 was at an electrical potential 0 volts, then after the coupling of the two capacitors, both are at the potential of half the supply voltage V _dd / 2. Therefore, the second pump capacitor 110 can only be charged from V _dd / 2 to V _dd , which saves part of the electrical energy required for charging.

However, the concept of charge sharing described in [7] requires a very complex timing scheme, and half of the electrical energy stored on the first pump capacitor 109 is lost. Therefore, the efficiency of a boosted charge pump with driver circuit that works according to the charge sharing principle is not sufficiently high.

An improved charge pump based on the principle of charge sharing is known from [8]. The concept described therein is based on combining the idea of charge sharing with a two-stage charging of the pump capacitors. If the electrical voltage V _dd to be applied to a pump capacitor is increased in two _stages starting from a value of 0 volt, ie for example from 0 volt to V _dd / 2 and then from V _dd / 2 to V _dd , the electrical energy required for this is lower than with a one-step raising of the electrical potential from 0 volts to a potential V _dd . Furthermore, the concept described in [8] aims to reduce the disturbing influence of parasitic current peaks, which can occur during pumping.

However, the charge pump described in [8] also shows a number of disadvantages. So here too part of the on one according to the charge sharing principle with the second Pump capacitor connectable first pump capacitor stored charge amount lost. Besides, that is described concept is relatively complex.

In addition to the disadvantage described that according to the batch Sharing concept at most 50% of the energy on a charged Node can be recycled, the batch Sharing concept just an increase in efficiency with regard to the charge pump itself. Losses in the Clock generation and the driver circuits remain and cannot be reduced according to the charge sharing concept become.

The invention is based on the problem of a circuit Arrangement for generating a versus an input voltage provide increased output voltage that a improved efficiency compared to the prior art having.

The problem is compounded by a circuit arrangement and a contactless chip card with the features according to independent claims solved.

The circuit arrangement of the invention has a first one Charge pump circuit with one input to one Input voltage can be applied, with an output at which a increased compared to an applied input voltage Output voltage is provided, one with the input coupled first amplifier stage with a first pump Node and a second amplifier coupled to the output Level up with a second pump node. Furthermore, the Circuit arrangement on a charge reservoir circuit with a first coupling node that is connected to the first pump Is coupled and with a second coupling node, which is coupled to the second pump node. The Charge reservoir circuitry is arranged to be excess charge carriers in a first operating state buffered by the first pump node and this the provides second pump node and in a second Operating state excess charge carriers from the second Pump nodes temporarily stored and this the first pump Provides nodes.

With the circuit arrangement described, it is possible to basically the whole on one knot recycle cached electrical energy. An illustration on the first charge pump circuit arranged electrical node with one on it electrical charge present is not discharged to ground, but this electrical charge is transferred via the coupling Charge reservoir circuit knot this provided, the charge reservoir circuit these Charge another node of the charge pump circuit provides. This is the circuit arrangement generated waste heat is reduced and the efficiency is increased. By reducing the energy consumption of the circuit arrangement problems are avoided that result from the waste heat of a Circuit result. For example, one Liquid gas cooling of supercomputers can be dispensed with or less elaborate if the waste heat is reduced is.

One aspect of the invention can be clearly seen therein be that required by the prior art complex driver circuit which, as described above, often has low efficiency and high circuitry required by a simple and inexpensive resonance circuit (Charge reservoir circuit) which is the entire electrical in an electrical circuit Energy does not dissipate towards a mass potential, but rather other nodes to be charged.

Furthermore, according to the invention, all nodes of the circuit Arrangement in the recycling process on the nodes stored electrical charge carriers included, in particular, the charge reservoir circuit is in the Recycling process included.

Consequently, with the circuit arrangement according to the invention, which provide the generation of an output compared to an input voltage present at an input increased output voltage enables efficiency elevated. Therefore, with a fixed number of amplifier A higher output voltage can be reached or one fixed output voltage with a smaller number of Amplifier levels attainable.

Clearly, a basic idea of the invention is that energy contained on charged circuit nodes Unload the node not to dissipate, but with help the charge reservoir circuit (also in the literature "Power-Clock") and store it next Clock cycle to the corresponding nodes of the next level to relocate.

According to an advantageous development of the invention the first amplifier stage further comprises a first switching node which is coupled to the second coupling node, and the second amplifier stage has a second switching node on, which is coupled to the first coupling node. The Charge reservoir circuitry is arranged to be in the first operating state excess charge carriers from caches the second switching node and this the first switching node or the second pump node provides. Furthermore, the charge reservoir circuit set up in accordance with the further training described, that he has excess in the second operating state Charge carriers from the first switching node are temporarily stored and this to the second switching node or the first pumping Provides nodes.

In other words, it is realized according to the invention, even compared to simple designs of charge pumps, improved charge pumps having a large number of nodes for pulses to be applied (such as the boosted charge pump 100 shown in FIG. 1A, which apart from the second and third inputs 103 , 104 have further inputs 105 , 106 , 107 , 108 ) to be used. The nodes of the charge pump circuit additionally occurring as a result are also included in the concept of the invention, so that electrical charge carriers located thereon, which are usually discharged to ground, are temporarily stored in the charge reservoir circuit and made available elsewhere in the circuit arrangement. This further increases the efficiency.

Furthermore, the first charge pump circuit can be one between the second amplifier stage and the output arranged another first amplifier stage with another first Have pump nodes with the second amplifier stage and the output is coupled, and the other first Pump node is coupled to the first coupling node. In addition, the further first amplifier stage can further have a further first switching node, which with the second coupling node is coupled.

Furthermore, the first charge pump circuit can be one between the further first amplifier stage and the output arranged another second amplifier stage with a have another second pump node, which with the other first amplifier stage is coupled to the output, and whose further second pump node with the second coupling Node is coupled. Preferably, the further second Amplifier stage further a further second switching node on, which is coupled to the first coupling node.

In addition, the first charge pump circuit can be a or have several further amplifier stages which between the further second amplifier stage and the Output is / are arranged, the further amplifier (s) Steps alternately with the charge reservoir Circuitry is / are like either the first or the second amplifier stage.

The circuit arrangement according to the invention for multi-stage Increase an input voltage to an amplified one Output voltage can be generated at any number can be expanded by amplifier stages. The invention realized coupling between the charge pump circuit with the amplifier stages and the Charge reservoir circuitry is flexible and easy on any number of amplifier stages can be set. In particular, there is only one for all amplifier stages Charge reservoir circuit required, resulting in savings causes.

The circuit arrangement can have one or more second ones Charge pump circuits, the one or those with the Charge reservoir circuit is or are coupled.

Often, several charge pumps are installed on one chip different output voltages and loads. In in this case it is possible with the invention Circuit arrangement the charge reservoir circuit only train once, and this with a plurality of identical or different charge pump circuits with the desired properties to couple. In other words only one charge reservoir circuit to power multiple Charge pump circuits used. Since only one Charge reservoir circuit for such an application is required is the space required for this low on a chip. Such a circuit arrangement is inexpensive and inexpensive to manufacture.

In particular, the first charge pump circuit and the second charge pump circuit (or any Number of additional charge pump circuits) one different number of amplifier stages and / or have different output voltages.

The circuit arrangement according to the invention is therefore flexible to the special needs of anyone, with increased Voltages can be designed for the supply circuit to be supplied.

According to a further advantageous embodiment of the Circuit arrangement according to the invention has one adiabatic logic circuit based on at least one of the coupling nodes with the charge reservoir Circuit is coupled.

The use of the circuit arrangement according to the invention is particularly advantageous for integrated circuits that use work resonant energy. An adiabatic logic Circuit, as for example in [3], [4], [9] is proposed, has an essential element "Power clock" on (this corresponds to the here as Charge reservoir circuit designated device). The needed for the adiabatic logic circuit Charge reservoir circuit can then be used for the charge pump Circuit of the circuit arrangement according to the invention be used, which effects rationalization, d. that is, for circuits according to the adiabatic dynamic logic or partially adiabatic Circuit architecture the existing for logic areas "Power clock" can be used for the charge pumps.

The charge reservoir circuit is preferably such set up that the signals on the first and on the second coupling node two mutually inverse clock signals are.

The input voltage that is on the input of the charge pump Circuit is present, a supply voltage of Circuit arrangement. Preferably the Supply voltage also to a supply input of the Charge reservoir circuit can be applied.

According to the configuration of the Circuit arrangement according to the invention are the Charge pump circuit and the charge reservoir circuit operated with the same supply voltage that on the Circuit arrangement is provided anyway. thats why an additional voltage source to supply the Charge reservoir circuit or for coupling to the Charge pump circuit input saved. The Manufacturing the circuit arrangement is therefore inexpensive.

The charge reservoir circuit preferably has one "Blip" circuit as described, for example, in [9] is described.

According to a preferred embodiment, the charge pump circuit is a boosted charge pump circuit such as, for example, the boosted charge pump 100 shown in FIG. 1A.

At least part of the elements of the circuit arrangement can be designed as an integrated circuit.

The circuit arrangement can then be miniaturized trainable and with inexpensive standardized Semiconductor technology processes can be produced.

According to the invention, a contactless chip card is also included a circuit arrangement with those described above Features provided.

A contactless smart card is a smart card that is made over Coupling elements (capacitive or inductive) with the outside world communicates, and in which a direct mechanical Coupling with a chip card terminal is unnecessary. Contactless chip cards are also for heavily soiled Suitable environments. They are also for larger ones Distances up to about 50 cm between card and one Smart card terminal that receives the signals that are in the card can be coupled in, sends out, suitable. In a contactless Chip cards are often one or more coupling coils integrated inductively with a chip card terminal communicate. The supply voltage of a contactless Chip card can be from the signal of the chip card terminal be obtained, in particular by means of inductive coupling electromagnetic waves. Contactless chip cards have to not to be inserted into a slot to be read to be able to, but can be led past the recipient or, for example, within the purse of a Be read by the user.

Contactless smart cards are an interesting one Application example for the circuit Arrangement. He plays with contactless chip cards Power consumption a dominant role because the electrical energy of a contactless chip card inductively from a chip card terminal in the contactless chip card is coupled. Contactless smart cards contain as Permanent storage is often an EEPROM memory, which is a Series of charge pumps needed. By putting them in one Chip card fed energy by means of the inventive Principle recovered when reloading electrical nodes the problem of energy supply is one contactless chip card reduced according to the invention. For Embodiments of the charge reservoir circuit can at least one coil may be required. Such coils can be used as an external element on the contactless chip card be accommodated.

Embodiments of the invention are in the figures are shown and explained in more detail below.

Show it:

Fig. 1A is a circuit diagram of a boosted charge pump according to the prior art,

Fig. 1B time courses of the pulse trains which are applied to the in Fig. Boosted charge pump shown 1A according to the prior art,

Fig. 2 shows a driver circuit for a boosted charge pump according to the prior art,

Fig. 3 is a schematic view of a circuit arrangement according to a first embodiment of the invention,

FIG. 4A is a detailed circuit diagram showing a circuit arrangement according to the first embodiment of the invention,

FIG. 4B pulse sequences according to the shown in Fig. 4A circuit arrangement according to the first embodiment of the invention,

Fig. 5 is a circuit diagram of a circuit arrangement according to a second embodiment of the invention,

Fig. 6 is a circuit diagram of a circuit arrangement according to a third embodiment of the invention,

FIG. 7A is a diagram schematically showing the output current output voltage characteristic shows the circuit arrangement of the invention or of charge pumps according to the prior art,

FIG. 7B is a diagram schematically showing the dependence of the efficiency of the output current of the inventive circuit arrangement and of the charge pump according to the prior art.

A first preferred exemplary embodiment of the circuit arrangement according to the invention is described below with reference to FIG. 3.

The circuit arrangement 300 shown in FIG. 3 has a charge pump circuit 301 with an input 302 to which an input voltage V ₀ can be applied, with an output 303 at which an output voltage V ₁ > V which is higher than the applied input voltage V _{0 0 is} provided, with a first amplifier stage 304 coupled to the input 302 with a first pump node 305 and with a second amplifier stage 306 with a second pump node 307 . Furthermore, the circuit arrangement 300 has a charge reservoir circuit 308 with a first coupling node 309 , which is coupled to the first pump node 305 and with a second coupling node 310 , which is coupled to the second pump node 307 , on. The charge reservoir circuit 308 is set up in such a way that it temporarily stores excess charge carriers from the first pump node 305 in a first operating state and makes them available to the second pump node 307 . Furthermore, the charge reservoir circuit 308 is set up in such a way that it temporarily stores excess charge carriers from the second pump node 307 in a second operating state and makes them available to the first pump node 305 .

An input voltage V ₀ is clearly coupled into the circuit arrangement 300 via the input 302 into the first amplifier stage 304 . Via the first pump node 305 of the first amplifier stage 304 , which is coupled to the first coupling node 309 , an electrical signal is made available to the first amplifier stage 304 by the charge reservoir circuit 308 , through which the first pump node 305 is charged electrically. According to the functionality of an amplifier stage of a charge pump circuit, an electrical voltage is provided at the end of the first amplifier stage 304 (not shown in FIG. 3), which is increased compared to the input voltage V ₀ . This voltage is provided to the second amplifier stage 306 of the charge pump circuit 301 . Via a second pump node 307 , the second amplifier stage 306 is coupled to the second coupling node 310 of the charge reservoir circuit 308 , which supplies the second amplifier stage 306 with electrical charge as required via the second pump node 307 . As a result, an electrical voltage provided to the second amplifier stage 306 by the first amplifier stage 304 is further increased. Two further amplifier stages, which are not shown in FIG. 3 and which are described below with reference to FIG. 4A, provide further amplification, so that an electrical voltage V _{1 is} obtained at the output 303 of the charge pump circuit 301 , which is increased compared to the input voltage V ₀ applied to the input 302 .

As described above, it is essential for the functionality of a charge pump circuit that the signals provided at the first and second pump nodes 305 , 307 are pulses with a suitable time dependency. According to the invention, the charged first pump node 305 of the charge pump circuit 301 is discharged in that the charged first pump node 305 is not discharged to ground, but rather by coupling the electrical charge thereon into the charge reservoir circuit 308 and the charge reservoir Circuit 308 makes this charge available to the second pump node 307 of the charge pump circuit 301 to be charged. Due to the functionality of the charge reservoir circuit 308 , this electrical charge is provided via the second coupling node 310 to the second pump node 307 , which is thereby brought from a logic value "0" to a logic value "1". As a result, the electrical charge located at the nodes to be discharged and the electrical energy contained therein are not uselessly lost, but rather are coupled into the charge reservoir circuit 308 in order to be recycled from there.

The first exemplary embodiment is described in detail below with reference to FIG. 4A.

As shown in FIG. 4A, but not in FIG. 3, the charge pump circuit 301 has a third amplifier stage 411 connected behind the second amplifier stage 306 with a third pump node 412 , that with the second amplifier stage 306 is coupled, and the third pump node 412 is coupled to the first coupling node 309 . Furthermore, the charge pump circuit 301 has a fourth amplifier stage 413 , which is arranged between the third amplifier stage 412 and the output 303 and has a fourth pump node 414 , which is coupled to the third amplifier stage 411 and the output 303 and the like fourth pump node 414 is coupled to the second coupling node 310 .

The structure of the charge pump circuit 301 is described in detail below.

The first pump node 305 of the first amplifier stage 304 is coupled to a first pump capacitor 415 . The second pump node 307 of the second amplifier stage 306 is coupled to a second pump capacitor 416 . The third pump node 412 of the third amplifier stage 411 is coupled to a third pump capacitor 417 , and the fourth pump node 414 of the fourth amplifier stage 413 is coupled to a fourth pump capacitor 418 . Furthermore, the first pump capacitor 415 is coupled to the second source / drain region of a first control transistor 419 . The second pump capacitor 416 is coupled to the second source / drain region of a second control transistor 420 . The third pump capacitor 417 is coupled to the second source / drain region of a third control transistor 421 . The fourth pump capacitor 418 is coupled to the second source / drain region of a fourth control transistor 422 . The input 302 is coupled to the first source / drain region of the first control transistor 419 . Furthermore, the input 302 is coupled to the gate region of the first control transistor 419 . Furthermore, the first pump capacitor 415 is coupled to the first source / drain region and to the gate region of the second control transistor 420 . The second pump capacitor 416 is coupled to the first source / drain region and to the gate region of the third control transistor 421 . The third pump capacitor 417 is coupled to the first source / drain region and to the gate region of the fourth control transistor 422 . Furthermore, the fourth pump capacitor 418 is coupled to the gate region and the first source / drain region of a first auxiliary transistor 423 . The second source / drain region of the auxiliary transistor 423 is coupled to the one terminal of an auxiliary capacitor 424 , the other terminal of which is grounded. Furthermore, the second source / drain region of the first auxiliary transistor 423 is coupled to the output 303 , at which the output voltage V _{1 is} provided.

The structure of the charge reservoir circuit 308 is described below.

The charge reservoir circuit 308 shown in FIG. 4A has a so-called "blip" circuit, which is known from [9], [10]. This "blip" circuit is suitable for providing the periodic pulse sequence 460 from FIG. 4B at the first coupling node 309 and the periodic pulse sequence 461 , which is opposite to the periodic pulse sequence 460 , at the second coupling node 310 , In the phases in which the pulse train 460 and 461 differ from zero, their pulse shape is sinusoidal. The charge reservoir circuit 308 , which has the “blip” circuit, is set up in such a way that the signals at the first and second coupling nodes 309 , 310 are two clock signals 460 , 461 that are essentially inverse to one another.

The first coupling node 309 is coupled to a first coil 430 and is coupled to the first connection of the first capacitance 431 . The second coupling node 310 is coupled to a second coil 432 and to the second connection of the first capacitance 431 . The input voltage V _{0 is applied} as a supply voltage to the first coil 430 and to the second coil 432 via a supply input 433 . In other words, the supply voltage V _{0 of} the circuit arrangement 300 is applied both to the input 302 of the charge pump circuit 301 and to the first and second coils 430 , 432 . The first coupling node 309 is further coupled to the first terminal of a second capacitance 433 , the other terminal of which is grounded. Furthermore, the second coupling node 310 is coupled to the first connection of a third capacitance 434 , the other connection of which is grounded. In addition, the first coupling node 309 is coupled to the first source / drain region of a second auxiliary transistor 435 and is coupled to the gate region of a third auxiliary transistor 436 . The other source / drain region of the second auxiliary transistor 435 is grounded. Furthermore, the gate region of the first auxiliary transistor 435 is coupled to the first source / drain region of the third auxiliary transistor 436 , the second source / drain region of which is grounded.

The functionality of the circuit arrangement 300 is described below.

At a point in time t ₁ (see FIG. 4B), the first pulse signal 460 is at a logic value "0", ie at ground potential. The first pulse signal 460 is present at the first pump node 305 of the first amplifier stage 304 of the charge pump circuit 301 . The ground potential is therefore at the second source / drain connection (ie at the right source / drain connection according to FIG. 4A) of the first control transistor 419 . In contrast, the first source / drain region and the gate region of the first control transistor 419 are at an electrical potential V ₀ . Due to its circuit configuration, the first control transistor 419 perceives the functionality of a diode, ie it enables an electrical current to flow from its first source / drain region to its second source / drain region, whereas an electrical current flow in the opposite Direction is not possible. This makes it possible for the first auxiliary node 440 to be brought to an electrical potential of approximately V ₀ . It should be noted that due to the electrical resistance of the channel region of the first control transistor 419, a voltage drop occurs at the first control transistor 419 , whereby the potential at the first auxiliary node 440 is slightly less than V ₀ .

At a second point in time t ₂ (see FIG. 4B), the first pulse signal 460 , which is applied to the first pump node 305 , is at a logic value "1", so that the first pump capacitor 415 and therefore the first auxiliary Nodes 440 are brought to an electrical potential that is higher than the electrical potential V ₀ . Since current flow across the channel region of the first control transistor 419 from its second source / drain region to its first source / drain region is not possible, an electrical charge can flow away from the first auxiliary node 440 avoided back to input 302 . In other words, as shown in FIG. 4B, at time t _2, the first pulse signal 460 is brought to a logic value "1", which brings additional electrical charge to the first auxiliary node 440 . As a result, the first auxiliary node 440 reaches an electrical potential that is higher than the input voltage V _{0 present} at the input 302 . As a result, at the end of the first amplifier stage 304 of the charge pump circuit 301, the electrical potential is increased compared to the input voltage V ₀ . In accordance with the functionality described, the electrical potential when passing through the second amplifier stage 306 at the second auxiliary node 441 , when passing through the third amplifier stage 411 at the third auxiliary node 442 and when passing through the fourth amplifier stage 413 at that fourth auxiliary node 443 successively increased from auxiliary node to auxiliary node. Provided that the first auxiliary transistor 423 is conductive, an electrical voltage V _{1 is} generated at the output 303 which is higher than the input voltage V ₀ applied to the input 302 .

The functionality of the charge reservoir circuit 308 shown in FIG. 4A is to receive electrical charge from charged pump nodes 305 and 412 or 307 and 414 coupled to one of the coupling nodes 309 and 310, respectively, and this electrical charge over the other To provide coupling nodes 310 and 309 to other pump nodes 307 and 414 and 305 and 412, respectively.

In the following, the time t ₂ from FIG. 4B is considered as an example. At this time, the first pulse signal 460 is at the maximum electrical potential, so that the first coupling node 309 supplies the first pumping node 305 and the third pumping node 412 with electrical charge in accordance with the coupling shown in FIG. 4A. As shown in FIG. 4B, the electrical potential of the first pulse signal 460 is to be reduced after the time t ₂ and the electrical potential of the second pulse signal 461 is to be increased. For this purpose, the second coupling node 310 , to which the second pulse signal 461 is applied, must be provided with electrical charge. The electrical charge present on the first pump node 305 and on the third pump node 412 is therefore coupled into the charge reservoir circuit 308 via the first coupling node 309 . The associated electrical energy is clearly stored in the resonance circuit consisting of coils and capacitors.

According to the functionality of the charge reservoir circuit 308 , which is essentially designed as a “blip” circuit, this electrical charge is applied to the second pump node 307 and the fourth pump node 414 via the second coupling node 310 from a time t ₃ provided. As a result, the electrical potential at the second coupling node 310 increases successively from the time t ₃ until it reaches the maximum value at the time t ₄ shown in FIG. 4B.

In other words, the charge reservoir circuit 308 is suitable for generating two only slightly overlapping, substantially sinusoidal clock signals (see FIG. 4B), so that it is possible to drive the charge pump circuit 301 directly as a result. Ideally, all of the charge stored on the nodes is reused. In this view, the losses that occur inevitably in each circuit, for example ohmic losses, are neglected.

In the simplified charge pump circuit 301 from FIG. 4A, the voltage drop across the respective control transistor is lost at each amplifier stage. These losses can be reduced further if the principle of the boosted charge pump (cf. FIG. 1A) is integrated into the circuit arrangement according to the invention. A corresponding second exemplary embodiment is shown in FIG. 5 and is explained below.

The circuit arrangement 500 has a boosted charge pump 501 as a charge pump circuit. The boosted charge pump 501 has an input 502 to which an input voltage V _{0 is} applied and an output 503 to which an output voltage V _{1 which} is higher than the applied input voltage 502 is provided. Furthermore, the boosted charge pump 501 has a first amplifier stage 504 coupled to the input 502 with a first pump node 505 and has a second amplifier stage 506 with a second pump node 507 .

Furthermore, the circuit arrangement 500 has a charge reservoir circuit 508 , which is configured identically to the charge reservoir circuit 308 from FIG. 4A. Therefore, the structure of the charge reservoir circuit 508 will not be explained again below. The components of the charge reservoir circuit 508 are provided with the same reference numerals as the corresponding components in the charge reservoir circuit 308 .

The charge reservoir circuit 508 has a first coupling node 509 , which is coupled to the first pump node 505 and a second coupling node 510 , which is coupled to the second pump node 507 . The charge reservoir circuit 508 is set up in such a way that it temporarily stores excess charge carriers from the first pump nodes 505 in a first operating state and makes them available to the second pump node 507 . Furthermore, the first amplifier stage 504 has a first switching node 511 , which is coupled to the second coupling node 510 , and the second amplifier stage 506 has a second switching node 512 , which is connected to the first coupling node 509 is coupled. The charge reservoir circuit 508 is set up in such a way that it temporarily stores excess charge carriers from the second switching nodes 512 in the first operating state and makes them available to the first switching node 511 or the second pump node 507 . The charge reservoir circuit is also set up such that it temporarily stores excess charge carriers from the first switching node 511 in the second operating state and makes them available to the second switching node 512 or the first pump node 505 .

Furthermore, the boosted charge pump 501 has a third amplifier stage 513 connected behind the second amplifier stage 506 with a third pump node 514 , which is coupled to the second amplifier stage 506 , and its third pump node 514 to the first Coupling node 509 is coupled. Furthermore, the third amplifier stage 513 has a third switching node 515 , which is coupled to the second coupling node 510 . In addition, the boosted charge pump 501 has a fourth amplifier stage 516 , which is arranged between the third amplifier stage 513 and the output 503 and has a fourth pump node 517 , which is coupled to the third amplifier stage 513 and the output 503 and the like fourth pump node 517 is coupled to the second coupling node 510 . The fourth amplifier stage 516 also has a fourth switching node 518 , which is coupled to the first coupling node 509 .

The exact structure of the boosted charge pump 501 is described below.

The boosted charge pump 501 has a first pump capacitor 519 , which is coupled to the first pump node 505 , has a second pump capacitor 520 , which is coupled to the second pump node 507 , and has a third pump capacitor 521 , which is coupled to the third pump node 514 and has a fourth pump capacitor 522 , which is coupled to the fourth pump node 517 . The first switching node 511 is coupled to a first switching capacitor 523 . The second switching node 512 is coupled to a second switching capacitor 524 . The third switching node 515 is coupled to a third switching capacitor 525 , and the fourth switching node 518 is coupled to a fourth switching capacitor 526 . The first pump capacitor 519 is coupled to the gate region of a first switching transistor 527 . The second pump capacitor 520 is coupled to the gate region of a second switching transistor 528 . The third pump capacitor 521 is coupled to the gate region of a third switching transistor 529 . The fourth pump capacitor 522 is coupled to the gate region of a fourth switching transistor 530 . The input 502 is coupled to the first source / drain region of the first switching transistor 527 , furthermore the input 502 is coupled to the first source / drain region of a first control transistor 531 . The other source / drain region of the first switching transistor 527 is coupled to the first switching capacitor 523 and to the gate region of the first control transistor 531 . Furthermore, the second source / drain region of the first control transistor 531 is coupled to the first source / drain region of a second control transistor 532 , the gate region of which is connected to the second switching capacitor 524 and to the second source / Drain region of the second switching transistor 528 is coupled. The first source / drain region of the second switching transistor 528 is coupled to the second source / drain region of the first control transistor 531 . The second source / drain region of the second control transistor 532 is coupled to the first source / drain region of the third control transistor 533 , the gate region of which is connected to the third switching capacitor 525 and to the second source / Drain region of the third switching transistor 529 is coupled. The first source / drain region of the third switching transistor 529 is coupled to the second source / drain region of the second control transistor 532 . The second source / drain region of the third control transistor 533 is coupled to the first source / drain region of a fourth control transistor 534 whose gate region is coupled to the fourth switching capacitor 526 and whose gate Region is coupled to the second source / drain terminal of the fourth switching transistor 530 . The first source / drain terminal of the fourth switching transistor 530 is coupled to the second source / drain terminal of the third control transistor 533 . Furthermore, the second source / drain terminal of the fourth control transistor 534 is coupled to the gate region and the first source / drain region of a first auxiliary transistor 535 . The second source / drain region of the first auxiliary transistor 535 is coupled to the one terminal of a first auxiliary capacitor 536 , the other terminal of which is grounded. Furthermore, the second source / drain region of the first auxiliary transistor 535 is coupled to the output 503 , at which the output voltage V _{1 is} provided.

The functionality of the circuit arrangement 500 is described below.

The principle of operation of the boosted charge pump 501 based on the operating principle of the reference to Fig. 1A, Fig. 1B boosted charge pump 100 described. However, the pump nodes 505 , 507 , 514 , 517 of the four amplifier stages 504 , 506 , 513 , 516 are provided with pulses which are generated by the charge reservoir circuit 508 and which essentially have the shape of the first pulse signal 460 and the second, respectively having the pulse signal 461 in Fig. 4B. The first pulse signal 460 generated at the first coupling node 509 is simultaneously provided to the first and third pump nodes 505 , 514 and the second and fourth switching nodes 512 , 518 . The second pulse signal 461 generated at the second coupling node 510 is simultaneously provided to the second and fourth pump nodes 507 , 517 and the first and third switching nodes 511 , 515 . As a result, a total of only two pulse signals 460 , 461 are required in order to generate an output voltage V ₁ by means of the circuit arrangement 500, which output voltage is increased compared to an input voltage V ₀ . Furthermore, the electrical charge located on all nodes of the circuit arrangement 500 can be recycled by providing this electrical charge to other nodes that are to be electrically charged.

If the times t ₁ , t ₂ , t ₃ , t ₄ and t ₅ shown in FIG. 4B are considered, the functionality of the circuit arrangement 500 can be illustrated as follows.

At time t ₁ , the first pulse signal 460 provided by the first coupling node 509 to the first pump node 505 is at the electrical ground potential. Therefore, switching transistor 427 is not conductive.

At the later time t ₂ , the first pulse signal 460 is brought to a maximum electrical potential, so that the first pump capacitor 519 is charged and the first switching transistor 527 thereby becomes conductive. This enables a current to flow between the input 502 and the gate region of the first control transistor 531 , so that, like the first source / drain region of the first control transistor 531, it is at an electrical potential of approximately V ₀ , The first control transistor 531 functions as a diode and allows a current to flow in front of the input 502 via its first and second source / drain regions up to a first auxiliary node 537 , but not in the opposite direction. As a result, the first auxiliary node 537 reaches a potential V ₀ minus the voltage drop along the channel region of the first control transistor 531 .

The voltage drop across the first control transistor 531 can be reduced by applying additional electrical charge to the gate region of the first control transistor 531 via the first switching node 511 in accordance with the principle of the boosted charge pump, so that the electrical resistance of the channel region of the first control transistor 531 is reduced. First, the time t _{3 is} considered. At this point in time, both pulse signals 460 , 461 are approximately at the ground potential. As a result, the first switching transistor 527 is non-conductive, so that the charge located on the gate region of the first control transistor 531 is protected against draining off. At time t ₄ , the second pulse signal 461 is at the maximum potential, as a result of which additional electrical charge reaches the already precharged gate region of the first control transistor 531 via the first switching capacitor 523 . As a result, the electrical conductivity of the channel region of the first control transistor 531 , which is controlled by means of the electrical potential of the gate region, is increased, so that the current flow from the first to the second source / drain region of the first control - transistor 531 falling voltage is reduced. This brings the first auxiliary node 537 to an electrical potential of approximately V ₀ .

At a point in time t ₅ , the first pulse signal 460 is again at the maximum potential, so that electrical charge flows from the first coupling node 509 to the first pump capacitor 519 , as a result of which the first auxiliary node 537 switches to an electrical voltage which is higher than V ₀ Potential is brought.

Therefore, the principle of the boosted charge pump can be used advantageously for the invention. According to the principle described, the electrical potential present on the respective auxiliary nodes 537 , 538 , 539 , 540 is successively increased from amplifier stage to amplifier stage, so that the external voltage V ₁ present at the output 503 compared to that at the input 505 applied input voltage V ₀ is increased several times.

The circuit diagram shown in FIG. 6, which shows a circuit arrangement 600 according to a third exemplary embodiment of the invention, is described in more detail below.

The functional blocks or the nodes from FIG. 5 which are important for a clear understanding of the functionality are likewise shown in FIG. 6 and provided with the same reference numbers.

The structure of the circuit arrangement 600 shown in FIG. 6 is described below.

The input 502 , to which the supply voltage V _{dd is} applied, is coupled to the first source / drain region of a first transistor 601 and is coupled to the first source / drain region of a second transistor 602 . The second source / drain region of the first transistor 601 is coupled to the gate region of the second transistor 602 . Furthermore, the gate region of the second transistor 602 is coupled to a first capacitor 603 . The gate region of the first transistor 601 is coupled to the second source / drain region of the second transistor 602 and is coupled to the first source / drain region of a third transistor 604 . The first source / drain region of the third transistor 604 is further coupled to the first connection of the second capacitor 605 . The second connection of the second capacitor 605 is coupled to the second source / drain region of the third transistor 604 . Furthermore, the second source / drain region of the second transistor 602 is coupled to the first source / drain region of a fourth transistor 606 . The second source / drain region of the third transistor 604 and the gate region of the fourth transistor 606 are coupled to the one connection of a third capacitor 607 . The second source / drain region of the fourth transistor 606 is coupled to the gate region of the third transistor 604 and is coupled to the first source / drain region of a fifth transistor 608 and a sixth transistor 609 . Furthermore, the second source / drain region of the fourth transistor 606 is coupled to the one terminal of a fourth capacitor 610 . The other terminal of the fourth transistor 610 is connected to the gate region of the fifth transistor 608 and is coupled to the second source / drain region of the sixth transistor 609 . Furthermore, the gate region of the fifth transistor 608 is coupled to the one terminal of a fifth capacitor 611 . The second source / drain region of the fifth transistor 608 is coupled to the first source / drain region of a seventh transistor 612 , to the first terminal of a sixth capacitor 613 and to the first source / drain region of an eighth transistor 614 , In addition, the gate region of the eighth transistor 614 is coupled to the second connection of the sixth capacitor 613 and the second source / drain region of the seventh transistor 612 . Furthermore, the second source / drain region of the seventh transistor 612 is coupled to the first terminal of a seventh capacitor 615 . The second source / drain region of the eighth transistor 614 is coupled to the first source / drain region and to the gate region of a ninth transistor 616 . The second source / drain region of the ninth transistor 616 is coupled to the one connection of the eighth capacitor 617 and to the output 603 , at which the output voltage V _{out is} provided. The second connection of the eighth capacitor 617 is grounded. The gate region of the sixth transistor 609 is coupled to the first source / drain region of the seventh transistor 612 , the gate region of which is connected to the second source / drain region of the eighth transistor 614 and to the first connection of a ninth capacitor 618 is coupled. The second terminal of the ninth capacitor 618 is further coupled to the first terminal of the tenth capacitor 619 , to the other terminal of the fifth capacitor 611 and to the other terminal of the first capacitor 603 . Furthermore, the second connection of the ninth capacitor 618 is coupled to the second coupling node 510 . The first coupling node 509 is coupled to the first terminal of an eleventh capacitor 620 and to the first terminal of a twelfth capacitor 621 . The first coupling node 509 is further coupled to the second connections of the third capacitor 607 and the seventh capacitor 615 . The second terminal of the eleventh capacitor 620 is coupled to the second source / drain region of the second transistor 602 . The second connection of the tenth capacitor 619 is coupled to the second source / drain region of the fourth transistor 606 . The second connection of the twelfth capacitor 621 is coupled to the second source / drain region of the fifth transistor 608 . Furthermore, the first coupling node 509 is coupled to a first coil 622 . The first coil 622 is coupled to a supply input 623 , to which the supply voltage V _{dd is} applied. Furthermore, the first coil 622 is coupled to a second coil 624 . In addition, the first coil 622 is coupled to the first terminal of a thirteenth capacitor 625 . The second connection of the thirteenth capacitor 625 is coupled to the second source / drain region of a tenth transistor 626 , the first source / drain region of which is coupled to the first coil 622 . The first source / drain region of the tenth transistor 626 is also coupled to the one terminal of a fourteenth capacitor 627 . The gate region of the tenth transistor 626 is coupled to the second terminal of the fourteenth capacitor 627 and is coupled to the first source / drain region of an eleventh transistor 628 . The second source / drain region of the eleventh transistor 628 is coupled to the second source / drain region of the tenth transistor 626 and to the first terminal of a fifteenth capacitor 629 . The second coil 624 is also coupled to the first source / drain region of the eleventh transistor 628 and is coupled to the other terminal of the fifteenth capacitor 629 . The gate region of the eleventh transistor 628 is coupled to the first coil 622 . Coil 624 is coupled to second coupling node 510 .

In Fig. 7A, Fig. 7B diagrams 700, 710 serve to illustrate the functionality of the shown in Fig. Circuit arrangement 6600. For the circuit arrangement 600 , simulations were carried out with parameters for a 0.25 μm CMOS process. The obtained output characteristic curves of the simulations with the circuit arrangement 600 are shown in FIG. 7A as curve 701 and in FIG. 7B as curve 711 and are compared with results obtained for a conventional, boosted charge source or for a charge pump with charge sharing become. The characteristics of the conventional, boosted charge pump are shown as curve 702 in FIG. 7A and as curve 712 in FIG. 7B. The characteristics of a charge pump with charge sharing are shown as curve 703 in FIG. 7A and as curve 713 in diagram 710 from FIG. 7B. The characteristics for the conventional, boosted charge pump and for a charge pump according to the charge sharing concept are taken from [8]. All compared charge pumps have four amplifier stages and work with a supply voltage V _dd = 2.5 volts.

The dependence of the output voltage (in volts) on the output current (in μA) of the three compared charge pumps is compared in FIG. 7A.

As shown in FIG. 7A, the output characteristic curve 701 of the circuit arrangement 600 shows an output voltage which is significantly increased compared to the characteristic curve 702 . This effect is based on the resonance increase of the charge reservoir circuit, also referred to as the "power clock". The half-wave output pulses of the power clock peak more than double the supply voltage than the concepts known from the prior art. Therefore, the circuit arrangement according to the invention is more powerful than the known charge pumps, especially at low supply voltages.

In diagram 710 from FIG. 7B, curves 711 for the circuit arrangement 600 , 712 for the conventional, boosted charge pump and 713 for the charge pump according to the charge sharing concept are compared with one another.

In diagram 710 the efficiency p (dimensionless) is plotted as a function of the output current (in µA). As shown in FIG. 7B, the efficiency of the circuit arrangement according to the invention reaches 80% and more at the top, compared with a maximum of 65% for the charge pump according to the charge sharing concept or just over 40% for the conventional, boosted charge pump. Of great practical importance is the fact that the efficiency of the circuit arrangement according to the invention drops significantly more slowly with increasing load, that is to say with increasing output current strengths, than in the case of the charge pump according to the charge sharing concept or in the conventional, boosted charge pump. As a result, the usable load range of the circuit arrangement for generating an output voltage which is higher than an input voltage is significantly increased compared to the concepts from the prior art. In other words, the usable load range of the pump circuits is improved compared to the prior art, since the efficiency of the circuit arrangement of the invention drops much more slowly as the load on the charge pump increases.

The following publications are cited in this document:
[1] Athas, WC et al. ( 1994 ) "Low Power Digital Systems Based on Adiabatic Switching Principles", IEEE Trans VLSI 2 : 398-406
[2] Dickinson, A et al. ( 1995 ) "Adiabatic Dynamic Logic," IEEE J Sol State Circuits 30 : 311-315
[3] Denker, SJ ( 1994 ) "A Review of Adiabatic Computing", Symposium on Low Power Electronics Proc. 1994, pp. 94-97
[4] U.S. Patent 5,459,414
[5] Bloch, M et al. ( 1998 ) "High Efficiency Charge Pump Circuit for Negative High Voltage Generation at 2 V Supply Voltage", Proc. of 24th ESSCIRC, pp. 100-103
[6] Nozoe, A et al. ( 1995 ) "A 3.3 V High Density AND Flash Memory with 1 ms / 512b Erase & Program Time", ISSCC Digist of Technical Papers, pp. 124-125
[7] U.S. Patent 5,818,289
[8] Lauterbach, C et al. ( 2000 ) "Charge Sharing Concept and New Clocking Scheme for Power Efficiency and Electromagnetic Emission Improvement of Boosted Charge Pumps" IEEE Journal of Solid-State Circuits 35 ( 5 ): 719-723
[9] Athas, WC et al. ( 1996 ) "A resonant signal driver for two phase, almost non-overlapping clocks", IEEE Int. Symp. On circuits and systems, pp. 129-132
[10] US Patent 5,559,478 reference numeral 100 boost charge pump
101 first entrance
102 output
103 second entrance
103 a input node
104 third entrance
105 fourth entrance
106 fifth entrance
107 sixth entrance
108 seventh entrance
109 first pump capacitor
110 second pump capacitor
111 third pump capacitor
112 fourth pump capacitor
113 first switching capacitor
114 second switching capacitor
115 third switching capacitor
116 fourth switching capacitor
117 first switching transistor
118 second switching transistor
119 third switching transistor
120 fourth switching transistor
121 first storage node
122 second storage node
123 third storage node
124 fourth storage node
125 first control transistor
126 second control transistor
127 third control transistor
128 fourth control transistor
129 auxiliary transistor
130 first amplifier stage
131 second amplifier stage
132 third amplifier stage
133 fourth amplifier stage
140 timeline
200 driver circuit
201 entrance
202 first inverter stage
203 second inverter stage
204 first electrical node
205 p-MOS transistor
206 n-MOS transistor
207 supply voltage
208 second electrical node
209 ground potential
300 circuit arrangement
301 charge pump circuit
302 entrance
303 output
304 first amplifier stage
305 first pump node
306 second amplifier stage
307 second pump node
308 charge reservoir circuit
309 first coupling node
310 second coupling node
411 third amplifier stage
412 third pump node
413 fourth amplifier stage
414 fourth pump node
415 first pump capacitor
416 second pump capacitor
417 third pump capacitor
418 fourth pump capacitor
419 first control transistor
420 second control transistor
421 third control transistor
422 fourth control transistor
423 first auxiliary transistor
424 auxiliary capacitor
430 first coil
431 first capacity
432 second coil
433 second capacity
434 third capacity
435 second auxiliary transistor
436 third auxiliary transistor
440 first auxiliary node
441 second auxiliary node
442 third auxiliary node
443 fourth auxiliary node
460 first pulse signal
461 second pulse signal
500 circuit arrangement
501 boosted charge pump
502 entrance
503 output
504 first amplifier stage
505 first pump node
506 second amplifier stage
507 second pump node
508 charge reservoir circuit
509 first coupling node
510 second coupling node
511 first switching node
512 second switching nodes
513 third amplifier stage
514 third pump node
515 third switching node
516 fourth amplifier stage
517 fourth pump node
518 fourth switching node
519 first pump capacitor
520 second pump capacitor
521 third pump capacitor
522 fourth pump capacitor
523 first switching capacitor
524 second switching capacitor
525 third switching capacitor
526 fourth switching capacitor
527 first switching transistor
528 second switching transistor
529 third switching transistor
530 fourth switching transistor
531 first control transistor
532 second control transistor
533 third control transistor
534 fourth control transistor
535 first auxiliary transistor
536 first auxiliary capacitor
537 first auxiliary node
538 second auxiliary node
539 third auxiliary node
540 fourth auxiliary knot
600 circuit arrangement
601 first transistor
602 second transistor
603 first capacitor
604 third transistor
605 second capacitor
606 fourth transistor
607 third capacitor
608 fifth transistor
609 sixth transistor
610 fourth capacitor
611 fifth capacitor
612 seventh transistor
613 sixth capacitor
614 eighth transistor
615 seventh capacitor
616 ninth transistor
617 eighth capacitor
618 ninth capacitor
619 tenth capacitor
620 eleventh capacitor
621 twelfth capacitor
622 first coil
623 supply input
624 second coil
625 thirteenth capacitor
626 tenth transistor
627 fourteenth capacitor
628 eleventh transistor
629 fifteenth capacitor
700 diagram
701 curve for circuit arrangement 600
702 curve for conventional, boosted charge pump
703 curve for charge pump with charge sharing
710 diagram
711 curve for circuit arrangement 600
712 curve for conventional, boosted charge pump
713 curve for charge pump with charge sharing

Claims (17)

1. circuit arrangement,
which has:
a first charge pump circuit
with an input to which an input voltage can be applied;
with an output at which an increased output voltage compared to an applied input voltage is provided;
with a first amplifier stage coupled to the input and having a first pump node;
with a second amplifier stage coupled to the output and having a second pump node;
a charge reservoir circuit
with a first coupling node, which is coupled to the first pump node, and with a second coupling node, which is coupled to the second pump node;
wherein the charge reservoir circuit is arranged such that it
in a first operating state, excess charge carriers from the first pump node are buffered and made available to the second pump node;
in a second operating state, excess charge carriers from the second pump node are buffered and made available to the first pump node. 2. Circuit arrangement according to claim 1,
in which the first amplifier stage further has a first switching node which is coupled to the second coupling node, and in which the second amplifier stage has a second switching node which is coupled to the first coupling node, and wherein the charge reservoir circuit is configured to
in the first operating state, excess charge carriers are temporarily stored by the second switching node and made available to the first switching node or the second pumping node;
in the second operating state, excess charge carriers are temporarily stored by the first switching node and made available to the second switching node or the first pump node. 3. Circuit arrangement according to claim 1 or 2, in which the first charge pump circuit has a between the second amplifier stage and the output arranged another first amplifier stage with another first Has pump node with the second amplifier stage and the output is coupled, and the other first Pump node is coupled to the first coupling node. 4. Circuit arrangement according to claim 3, in which the further first amplifier stage also one has another first switching node, which with the second Coupling node is coupled. 5. Circuit arrangement according to claim 3 or 4, in which the first charge pump circuit has a between the further first amplifier stage and the output arranged another second amplifier stage with a has another second pump node, which with the other first amplifier stage and the output is coupled, and whose further second pump node with the second coupling Node is coupled. 6. Circuit arrangement according to claim 5, in which the further second amplifier stage also one has another second switching node, which with the first Coupling node is coupled. 7. Circuit arrangement according to claim 5 or 6, in which the first charge pump circuit is one or has several additional amplifier stages between the arranged another second amplifier stage and the output is / are, the further amplifier stages alternating thus coupled to the charge reservoir circuit is / are like either the first or the second amplifier Step. 8. Circuit arrangement according to one of claims 1 to 7, which has a second charge pump circuit which with is coupled to the charge reservoir circuit. 9. Circuit arrangement according to claim 8, in which the second charge pump circuit and the first Charge pump circuit a different number of Amplifier levels and / or different Have output voltages. 10. Circuit arrangement according to one of claims 1 to 9, which also has an adiabatic logic circuit, the via at least one of the coupling nodes with the Charge reservoir circuit is coupled. 11. Circuit arrangement according to one of claims 1 to 10, in which the charge reservoir circuit is such is set up that the signals on the first and on the second coupling node two mutually inverse clock signals are. 12. Circuit arrangement according to one of claims 1 to 11, where the input voltage is a supply voltage of the Circuit arrangement is. 13. Circuit arrangement according to claim 12, at which to a supply input of the Charge reservoir circuit the supply voltage is created. 14. Circuit arrangement according to one of claims 1 to 13, where the charge reservoir circuit "blips" Circuit. 15. Circuit arrangement according to one of claims 1 to 14, where the charge pump circuit is a boosted one Charge pump circuit is. 16. Circuit arrangement according to one of claims 1 to 15, the at least partially as an integrated circuit is trained. 17. Contactless chip card with a circuit arrangement according to one of claims 1 to 16th