DE102004024612B4 - Voltage generating circuit - Google Patents

Voltage generating circuit Download PDF

Info

Publication number
DE102004024612B4
DE102004024612B4 DE102004024612.2A DE102004024612A DE102004024612B4 DE 102004024612 B4 DE102004024612 B4 DE 102004024612B4 DE 102004024612 A DE102004024612 A DE 102004024612A DE 102004024612 B4 DE102004024612 B4 DE 102004024612B4
Authority
DE
Germany
Prior art keywords
voltage
node
level
control signal
vcc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE102004024612.2A
Other languages
German (de)
Other versions
DE102004024612A1 (en
Inventor
Youichi Tobita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2003140079 priority Critical
Priority to JP2003/140079 priority
Priority to JP2003/419716 priority
Priority to JP2003419716A priority patent/JP4393182B2/en
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE102004024612A1 publication Critical patent/DE102004024612A1/en
Application granted granted Critical
Publication of DE102004024612B4 publication Critical patent/DE102004024612B4/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by G11C11/00
    • G11C5/14Power supply arrangements, e.g. Power down/chip (de)selection, layout of wiring/power grids, multiple supply levels
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0214Particular design considerations for integrated circuits for internal polarisation, e.g. I2L

Abstract

Voltage generating circuit comprising: a first transistor (NQQ1; PQQ1) which is connected between a precharge voltage supply node (NDD2; NDD12) providing a precharge voltage and a first internal node (ND2; ND12), and the one with a second internal node (NDD1; NDD13) connected control electrode; a first capacitance element (CQ1; CQ13) connected between a first input signal (S32; S52) receiving a first control signal for precharging and the second internal node; a second transistor (NQQ2; PQQ2) connected between the the first and second internal nodes, and which has a control electrode which receives a second control signal (ΦP; ΦPZ) controlling the charge accumulation; a third transistor (NQ1; PQ11) which is connected between the first internal node and an output node (OD1; OD11), and which has a control electrode connected to a third internal node (ND3; ND13); a four th transistor (NQ2; PQ12) which is connected between the output node and the third internal node and which has a control electrode connected to the first internal node; a second capacitance element (C2; C12) which is connected between a third input node (S2; S12) which precharges a second charge receives a controlling third control signal and is connected to the first internal node; a third capacitance element (C3; C13) connected between a fourth input node (S3; S13) which receives a fourth control signal controlling charge transfer and the third internal node, the precharge voltage supply node (NDD2; NDD12) being supplied with the second control signal (ΦP; ΦPZ).

Description

  • The present invention relates to a voltage generating circuit for generating an internal voltage having a desired voltage level, and more particularly, to a structure of a voltage generating circuit that efficiently generates an internal voltage by applying a charge pumping operation of a capacitance element.
  • The patent specification DE 196 01 369 C1 discloses a voltage multiplication device for generating the erase voltage for an EEPROM. A negative high voltage is generated by a multi-stage circuit, an input of one stage being connected to the output of the preceding stage and the stages being identical to one another. In particular, the channel-forming wells of the respective transistors can be connected to a connection of the respective transistor without the negative high voltage poling the substrate well diode in the forward direction, so that there is no short circuit with the substrate and the substrate control effect is reduced.
  • Nakagome et al. describe in an article in IEEE Journal of Solid-State Circuits, VOL. 26, No. 4, April 1991 an experimental 1.5-V 64-Mb DRAM. A charge pump circuit is used to generate an increased voltage for a word line driver. Feedback is used in the charge pump circuit to achieve the highest possible voltage.
  • In the article “Switched-Capacitor DC-DC Converters for Low-Power On-Chip Applications”, Maksimovic and Dhar disclose charge pumps for applications with low power consumption. Two identical, phase-opposite SC converters are connected in parallel, which means that no separate bootstrap gate drivers are required.
  • In many cases, semiconductor devices are designed such that internal voltages with different voltage levels are used. For example, In a DRAM (Dynamic Random Access Memory), a negative voltage is used for pre-poling a substrate region of a memory cell array with a constant voltage, and a high positive voltage, which is higher than a supply voltage, is applied to a selected word line. Non-volatile memory uses negative and positive voltages to write back data.
  • When such voltages are applied externally at levels other than a supply voltage level, the system size increases and the power consumption of the entire system increases. In addition, a semiconductor memory device requires pin terminals provided for receiving such voltages, whereby the size also increases.
  • In view of the above, semiconductor devices are generally designed to internally generate voltages at the required levels. An example of the circuit that generates such an internal voltage is in publication 1 (Japanese Patent Laid-Open Publication JP H04-372 792 A).
  • One in block letters 1 disclosed internal voltage generating circuit generates a negative voltage by applying a charge pumping operation of a capacitance element. According to the structure of the internal voltage generating circuit from the publication 1 electrical charges are accumulated in a charge accumulation node by the charge pumping operation of a charge capacitance element. A discharge control transistor is turned on by the capacitive coupling of a control capacitance element to discharge the charge accumulation node to a ground voltage level. Thereafter, the charge capacitance element performs the charge pumping operation such that charges are pulled out of the charge accumulation node to drive the node to a negative voltage level. The charge accumulation node is changed with an amplitude of the supply voltage. Negative charges of this charge accumulation node are supplied through an output transistor to an output node, so that a negative voltage with a level of - VCC is provided, whereby VCC represents the supply voltage.
  • The gate potential of the output transistor, controlled by an output control transistor with a gate terminal connected to the charge accumulation node, changes between a ground voltage GND and a negative tension - VCC ,
  • Publication 1 provides a negative voltage with an appropriate voltage level by changing the charge accumulation node with an amplitude of VCC even with a low supply voltage.
  • In the structure which generates an internal voltage by applying the charge pumping operation of the capacitance element, in view of the power consumption of the semiconductor device, the charges generated by the charge pumping operation are necessary
  • In a process of preloading the charge accumulation node on the Ground voltage levels, when the output transistor is not in the off state, provide precharged charges through the output transistor to the output node at a negative level, so that the voltage level of the negative potential rises. For the on / off control of this output transistor, an output control transistor with essentially the same structure as that for the on / off control of the discharge control transistor is used. Accordingly, when the charge accumulation node is precharged to the ground voltage level, the output transistor is also brought into the on state for a certain period of time, so that a current is wasted.
  • When building from printed matter 1 As described above, charges generated by the charge pumping operation of the capacitance element are wasted, and it is difficult to efficiently generate the voltage at a desired level with a low power consumption.
  • US 6 130 572 A describes a negative NMOS charge pump circuit with a plurality of charge pump stages connected in series with each other, each stage having a stage input connection and a stage output connection, the plurality of stages including: a first stage which has connected the respective stage input connection to a reference voltage, an output stage, which has connected the respective stage output connection operationally to an output connection of the charge pump, in which a negative voltage is developed, and a plurality of middle stages or intermediate stages, each of which has connected the respective stage input connection to the stage output connection of a previous stage and the respective one Have connected the step output connection to the step input connection of a subsequent step. Each charge pump stage contains: a first MOSFET with a first electrode connected to the stage input connection and a second electrode connected to the stage output connection, a second MOSFET with a first electrode connected to the stage output connection and a second electrode connected to a gate electrode of the first MOSFET, one Booster capacitor with a first connection connected to the gate electrode of the first MOSFET and a second connection driven by a respective first digital signal that switches between the reference voltage and a positive voltage supply, and a second capacitor with a first connection connected to the charge pump output connection and one connected to a respective second digital signal that switches between the reference voltage and the voltage supply, second connection. The charge pump contains a device for supplying the second digital signal essentially in a phase opposite to the first digital signal. The first and the second MOSFET are N-channel MOSFETs, wherein a gate electrode of the second N-channel MOSFET is connected in the first stage to a third digital signal, which switches between the reference voltage and the voltage supply, a gate electrode of the second N-channel MOSFET is connected to the stage input terminal in all stages other than the first stage (SV).
  • It is an object of the present invention to provide a voltage generation circuit which can efficiently use the charges to generate a voltage at an intended level.
  • The object is achieved by a voltage generating circuit according to claim 1. Further developments of the invention are characterized in the subclaims.
  • In the voltage generating circuit, the first and second transistors can be turned on and off by cross-coupling the first and second transistors with optimal timing so that the voltages of the first and second internal nodes are changed at high speed to keep the changed voltage levels . Therefore, the second transistor is turned off while changing the voltage of the second internal node serving as the charge accumulation node, and then the charge pumping operation is applied to the second internal node, so that unnecessary current can be prevented from the second internal node flows.
  • According to the voltage generating circuit according to claim 1, the first internal node is precharged with the precharge voltage and coupled to the third control signal via the second capacitance element. The first internal node is also connected to the control electrode of the fourth transistor. Therefore, the on / off state of the respective transistors can be individually controlled by the charge pumping operation through the capacitance elements, and the flow of leakage current can be suppressed, so that the charges can be used efficiently to generate the internal voltage at the intended level.
  • Further features and advantages of the invention result from the description of exemplary embodiments with reference to the attached drawings.
  • From the figures show:
    • 1 a structure of a voltage generating circuit according to a first embodiment which is not part of the present invention;
    • 2 a signal waveform diagram illustrating an operation of the in 1 illustrated voltage generating circuit;
    • 3 a structure of a voltage generating circuit according to a second embodiment which is not part of the present invention;
    • 4 a signal waveform diagram illustrating an operation of the in 3 circuit shown;
    • 5 a schematic structure of an internal voltage generation circuit according to a third embodiment, which is not part of the present invention;
    • 6 a schematic structure of a in 5 control signal generating circuit shown;
    • 7 a timing diagram illustrating an operation of the in 6 circuit shown;
    • 8th a structure of a voltage generating circuit according to a fourth embodiment which is not part of the present invention;
    • 9 a signal waveform diagram illustrating an operation of the in 8th circuit shown;
    • 10A a structure of a voltage generating circuit according to a fifth embodiment which is not part of the present invention;
    • 10B building an in 10A charge transfer stage shown;
    • 11 a signal waveform diagram showing an operation of the in the 10A and 10B circuits shown;
    • 12 a schematic structure of a in 10A shown circuit which generates a control signal;
    • 13 a signal waveform diagram illustrating an operation of an in 12 circuit shown;
    • 14 a structure of a voltage generating circuit according to a sixth embodiment which is not part of the present invention;
    • 15 a signal waveform diagram illustrating an operation of an in 14 circuit illustrated;
    • 16 a structure of a voltage generating circuit according to a seventh embodiment which is not part of the present invention;
    • 17 a signal waveform diagram illustrating an operation of the in 16 circuit shown;
    • 18th a structure of a voltage generating circuit according to an eighth embodiment which is not part of the present invention;
    • 19 a timing diagram illustrating an operation of the in 18th illustrated voltage generating circuit;
    • 20th a structure of a voltage generating circuit according to a ninth embodiment which is not part of the present invention;
    • 21 a timing diagram illustrating an operation of the in 20th reproduces the voltage generating circuit shown;
    • 22 a structure of a voltage generating circuit according to a tenth embodiment, which is part of the present invention;
    • 23 a structure of a voltage generating circuit according to an eleventh embodiment, which is part of the present invention;
    • 24 a structure of a voltage generating circuit according to a twelfth embodiment which is not part of the present invention;
    • 25th a structure of a voltage generating circuit according to a modification of the twelfth embodiment which is not part of the present invention;
    • 26 a structure of a voltage generating circuit according to a thirteenth embodiment which is not part of the present invention; and
    • 27 a structure of a voltage generating circuit according to a modification of the thirteenth embodiment which is not part of the present invention.
  • Various embodiments of a voltage generating circuit are described below with reference to the figures. Of these embodiments, those are related to FIG 22 and 23 described tenth and eleventh Embodiment part of the present invention. The other embodiments are not part of the present invention, but serve as explanatory examples for a better understanding of the present invention.
  • First embodiment
  • 1 shows a structure of a voltage generating circuit according to a first embodiment. In the 1 The voltage generating circuit shown generates a negative voltage that is lower than a reference potential. In this embodiment, a ground potential GND used as the reference potential, and a signal for controlling a charge pump operation changes between a ground voltage and a supply voltage VCC so that a negative voltage of -VCC is produced.
  • In 1 includes the voltage generating circuit: a P-channel MOS transistor (insulating layer field effect transistor) PQ1 that is between an internal node ND1 and a reference potential node (hereinafter referred to as a "ground node") GG is switched and one with an internal node ND2 has connected gate connection; a P-channel MOS transistor PQ2 that is between the internal nodes ND2 and the ground node GG is switched and one with the internal node ND1 has connected gate connection; a capacity element C1 that between a control signal input node receiving a precharge control signal ΦP S1 and an internal node ND1 is switched; and a capacity element C2 that between a control signal ΦCP for the control signal input node receiving the charge accumulation S2 and the internal node ND2 is switched.
  • MOS transistors PQ1 and PQ2 correspond to the first and the second transistor, and capacitance elements C1 and C2 corresponding to the first or the second capacitance element. The control signals ΦP and ΦCP correspond to the first and the second control signal. The internal nodes ND1 and ND2 correspond to the first and second internal nodes, respectively.
  • The voltage generating circuit further includes: an N-channel MOS transistor NQ1 that is between the internal nodes ND2 and an exit node OD1 is switched and one with an internal node ND3 has connected gate connection; an N-channel MOS transistor NQ2 that is between the internal nodes ND3 and the output node OD1 is switched and the one with the internal node ND2 has connected gate connection; and a capacity element C3 that between a control signal ΦCT control signal input node receiving charge transfer S3 and the internal node ND3 is switched.
  • The MOS transistors NQ1 and NQ2 correspond to the third and the fourth transistor, the capacitance element C3 corresponds to the third capacitance element and the control signal ΦCT corresponds to the third control signal.
  • A capacity element C4 is between the output nodes OD1 and switched the ground node. This element of capacity C4 is used to stabilize an output voltage of -VCC against changes in an output load and can be omitted if the changes in the output load and therefore the change in the output voltage of - VCC is low. A voltage on the output node OD1 is applied to the internal circuit, not shown.
  • Each of the control signals ΦP . ΦCP and ΦCT alternates between the ground voltage GND and the supply voltage VCC ,
  • 2 Fig. 10 is a timing chart showing an operation of the voltage generating circuit 1 illustrated. For the sake of simplicity shows 2 Operating waveforms for the case where the voltage on the output node OD1 at the predetermined voltage level of -VCC is. Regarding 2 the operation of the voltage generating circuit will now stop 1 to be discribed.
  • The control signals ΦP . ΦCP and ΦCT change with one measure T , 2 illustrates signal waveforms over a period of 2-T ,
  • At a time t0 are the control signals ΦP . ΦCP and ΦCT at the level of the ground voltage GND , the supply voltage VCC or the ground voltage GND , The node is in this state ND1 through a cargo pull-out operation, the capacity element C1 at the voltage level of -VCC , and the knot ND2 by a charge supply operation of the capacity element C2 at the voltage level of the ground voltage GND ,
  • For the P-channel MOS transistor PQ1 serves the knot ND1 as a drain connection node and the ground node GG serves as a source connection node. The P-channel MOS transistor PQ1 is of the enhancement type and has a threshold voltage of a predetermined size. Therefore, the P-channel MOS transistor remains PQ1 off, since the potentials at its gate and source are equal, and no current flows between the nodes ND1 and the ground node GG ,
  • The MOS transistor PQ2 receives a negative potential -VCC at its gate connection and equal potentials at its drain connection (node ND2 ) and its source (ground node), so that no current between the drain and the source of the MOS transistor PQ2 flows.
  • The N-channel MOS transistor NQ1 regarding is the knot ND2 at the level of the ground voltage GND , the output node OD1 is at the level of the negative voltage -VCC and the knot ND3 is at the level of the negative voltage -VCC , The N-channel MOS transistor NQ1 is of the enhancement type, has a threshold voltage of constant magnitude and remains in the blocking state when the gate potential is equal to the source connection potential.
  • The N-channel MOS transistor NQ2 has a gate potential at the level of the voltage at the node ND2 or at the level of the ground voltage GND , and has drain and source connections at the same potential because the node ND3 and the output node OD1 are at the same potential level. Thus, no current flows between the drain and the source of the MOS transistor NQ2 , According to the control signal ΦP , the MOS transistor PQ2 brought to the knot ND2 precharge to the ground voltage level. In an initial state of charge pumping operation, the precharge voltage level of the node ND2 reduced in the direction of ground voltage.
  • At a time t1 when the control signal ΦP from the level of the ground voltage GND to the level of the supply voltage VCC changes, the charge pumping lifts through the capacitance element C1 the voltage level of the node ND1 from the negative tension -VCC to the ground voltage GND on. The drain and source connection of the MOS transistor are in the stable state PQ1 at the same voltage level and no current flows through the MOS transistor PQ1 ,
  • In a transition period of an initial stage of charge pumping is the node ND1 at the voltage level that is not less than the ground voltage GND is, and the knot ND1 and the ground node serve as the source and drain connection of the MOS transistor PQ1 , However, the voltage level of the node ND2 high in this state. The MOS transistor PQ1 is of the enhancement type, receives the gate-source voltage that is not higher than an absolute value of the threshold voltage, and remains in the off state. Thus, no current flows between the drain and source of the MOS transistor PQ1 ,
  • Because the knot ND2 at the level of the ground voltage GND is, drain and source connection of the MOS transistor PQ2 at the same potential, and no current flows between the drain and source of the MOS transistor PQ2 , even if the voltage level of the node ND1 from the negative tension -VCC to the ground voltage GND increases. By raising the control signal ΦP becomes the MOS transistor PQ2 brought into the locked state to prepare for the next charge pumping operation on the node ND2 ,
  • The knot ND2 maintains the level of the ground voltage GND and the knot ND3 is at the negative voltage level. The MOS transistor is in this state NQ2 conductive and electrically connects the output node OD1 with the internal node ND3 so that the internal node is at the same voltage level as the output node OD1 , This leaves the MOS transistor NQ1 reliable in the locked state. If the voltage level of the internal node ND3 and the output node OD1 the current through the MOS transistor stops immediately NQ2 to flow.
  • By matching the voltage levels of the internal node ND3 and the output node OD1 becomes the gate-source voltage of the MOS transistor NQ1 kept at or below the threshold voltage to prevent the MOS transistor NQ1 of the enrichment type before transmission of charges is in the on state, even if the internal node ND2 is driven to the negative voltage level, and the internal node ND2 serves as the source connection of the MOS transistor NQ1 , In an initial stage of charge pumping operation when the internal node ND2 is driven to the negative voltage level is the internal node ND3 at a high voltage level and the MOS transistor NQ1 can be brought into the open state. In this case, before generating the control signal ΦCT however, only negative charges to the output node OD1 transferred, and the charges are used to reduce the output voltage. Thus, the charges are used effectively.
  • At a time t2 the control signal drops ΦCP from the level of the supply voltage VCC to the level of the ground voltage GND , and the charge pumping through the capacitance element C2 lowers the voltage level of the node ND2 , Even if the voltage level of the node ND2 from the ground voltage GND to a negative voltage changes both the drain and source connection of the MOS transistor PQ1 at the level of the ground voltage GND , and no current flows between drain and source connection.
  • Because the MOS transistor PQ2 the knot ND2 serves as drain connection, both gate and source connection (ground node) are both at the level of the ground voltage. The MOS transistor PQ2 is of the enhancement type and has a gate-source voltage which is less than the absolute value of its threshold voltage, so that the MOS transistor PQ2 maintains the locked state. The knot drops accordingly ND2 through the charge pump operation of the capacitance element C2 to the level of the negative voltage -VCC , The node is in this state ND3 at the level of the negative voltage -VCC , and the MOS transistor NQ1 which the output node OD1 serves as the source connection, has the gate and source connections at the same potential and remains in the blocking state.
  • If the knot ND2 is driven to the negative voltage level, the voltage level of the node ND2 lower than the voltage level of the output node OD1 , The voltage level at the node ND3 is the voltage level at the output node. If the control signal ΦCT is at the ground voltage level, is the MOS transistor NQ1 is of the enhancement type and has a gate-source voltage that is less than the threshold voltage during the transfer stage and the stable stage, and maintains the blocking state so that the node ND2 can be driven exactly to the negative voltage level.
  • If the knot ND2 is driven to the negative voltage level in the transmission period, the MOS transistor PQ1 placed in the on state to the voltage level of the node ND1 decrease when the voltage level of the node ND1 is higher than the ground voltage.
  • In the charge pumping operation on the nodes ND2 there is therefore no path that allows a flow of the voltage level of the node ND2 adversely affecting leakage current, and the charges can be used efficiently to adjust the knot ND2 to the level of negative voltage - VCC.
  • With the MOS transistor NQ2 are drain and source connections at the same level of negative voltage -VCC , so that no current flows between drain and source connection.
  • By the time t3 the control signal increases ΦCT from the level of the ground voltage GND to the level of the supply voltage VCC on. At this time the control signal is ΦP to the level of the supply voltage VCC and the control signal ΦCP is at the level of the ground voltage GND , In this state, the charge pumping lifts through the capacitance element C3 the voltage level of the node ND3 from the negative tension -VCC to the level of the ground voltage GND on. Because the knot ND2 at the level of the negative voltage -VCC is the MOS transistor NQ1 brought to the knot ND2 at the exit node OD1 to couple. When the voltage level of the output node ÖD1 is higher than the negative voltage -VCC , negative electrical charges move from the output node OD1 to the knot ND2 so that the output node OD1 and the knot ND2 reach the same voltage level. In particular, the output node is in the stable state OD1 at the voltage level of -VCC , In this case, the gate connection and source connection of the MOS transistor NQ2 at the same potential and therefore the MOS transistor remains NQ2 in the off state, so no current between drain and source of the MOS transistor NQ2 flows.
  • In a transitional period, such as the start of charge pumping, the MOS transistor serves NQ2 the internal node ND3 as the drain, is the gate of the MOS transistor NQ2 after the start of charge transfer lower than the potential of the source, and the MOS transistor NQ2 remains in the locked state. Even if the gate and source connections are brought to the same potential by the charge transfer, the MOS transistor remains NQ2 due to its threshold voltage in the blocking state and does not adversely affect the charge transfer operation.
  • Thus the knot ND3 according to the control signal ΦCT driven to the supply voltage level, and negative charges can be efficiently sent to the output node OD1 be delivered so that the negative voltage - VCC of the intended voltage level is provided.
  • At a time t4 the control signal falls ΦCT from the level of the supply voltage VCC to the level of the ground voltage GND and the voltage level of the node ND3 decreases from the ground voltage GND to the negative tension -VCC , The lowest possible potential of the source connection node (node ND2 ) of the MOS transistor NQ1 is the negative tension -VCC , and the MOS transistor NQ1 is reliably brought into the locked state.
  • Drain and source connection of the MOS transistor NQ2 are at the level of the negative voltage -VCC and do not cause current to flow through it.
  • In the transition period at the start of charge pumping when the nodes ND2 and OD1 at voltage levels higher than the negative voltage -VCC the knot returns ND3 only to the voltage level of the output node OD1 back in the previous cycle, and the output node OD1 serves the MOS transistor NQ2 as source connection, gate and source connection of the MOS transistor NQ2 are at the same potential, and the MOS transistor NQ2 remains in the locked state. Even if the MOS transistor NQ1 the output node is switched on OD1 and the internal node ND2 , which act as the source or drain of the MOS transistor NQ1 serve at the same voltage level, and no current flows through the MOS transistor NQ1 , In the transition period is the voltage level to which the node ND3 returns the voltage level at which the MOS transistor NQ1 is locked and no charge is wasted.
  • At a time t5 the control signal increases ΦCP from the level of the ground voltage GND to the level of the supply voltage VCC on. In this period is the control signal ΦP at the level of the supply voltage VCC , The control signal ΦCT is at the level of the ground voltage GND , According to the increase in the control signal ΦCP through the charge pump operation of the capacity element C2 the voltage level of the node increases ND2 from the negative tension -VCC to the ground voltage GND on. During this process, the drain and source connection of the MOS transistor remain PQ1 at the level of the ground voltage GND , and the MOS transistor PQ1 turns off according to the increase in its gate potential. Thus, no current flows through the MOS transistor PQ1 ,
  • In the MOS transistor PQ2 the voltage level of the node increases ND2 only from the negative tension -VCC to the ground voltage GND on and exceeds the ground voltage GND not, so the ground node as the source of the MOS transistor PQ2 serves, which in turn remains in the locked state.
  • If the potential of the node ND2 the knot can be lifted ND2 in the transition period, such as an initial period of charge pumping, at a voltage level higher than the ground voltage GND be held (the knot ND2 serves as a source connection). In this case the control signal ΦP reduced so that the MOS transistor PQ2 is brought into the pass state so that the node ND2 is reliably discharged towards the ground voltage level. Therefore, there is no particular problem.
  • By the time t5 is the knot ND3 , even if the voltage level of the node ND2 to the ground voltage level, at the level of the negative voltage -VCC so the mos transistor NQ1 remains in the locked state. Even if the MOS transistor NQ2 goes into pass state is the internal node ND3 at the voltage level of the output node OD1 , ie the level of the negative voltage -VCC so that gate and source connection of the mos transistor NQ2 are at the same voltage, and thus the MOS transistor remains NQ2 in the locked state. Therefore, no current flows between the drain and source of the MOS transistor NQ2 ,
  • By the time t6 the control signal falls ΦP to the level of the ground voltage GND , Accordingly, the capacitance element decreases C1 the voltage level of the node ND1 from the ground voltage GND to the negative tension -VCC , According to this tension reduction of the knot ND1 goes the MOS transistor PQ2 in the pass state, and the node ND2 will reliably reach the level of the ground voltage GND set.
  • Even in the case where the knot ND2 is driven to a high voltage level, which is higher than the ground voltage in the transition period GND is the voltage level of the node ND2 be reliably lowered. In the next cycle, the voltage level of the node ND2 continue according to the control signal ΦCP can be reduced and the output voltage level can be reduced.
  • When the potential of the node is reduced ND2 serves the MOS transistor PQ1 the ground node as its source connection and accordingly are the gate and source connection of the MOS transistor PQ1 at the same voltage level so the mos transistor PQ1 remains in the locked state.
  • By the time t8 becomes a cycle T completed for a charge pumping operation, and that at the time t0 starting process will be repeated.
  • At the in 1 Therefore, the voltage generating circuit shown does not leak current during the charge pumping operation, and the charges can be used efficiently to generate the internal voltage at an intended level.
  • The MOS transistors PQ1 and PQ2 are cross-coupled and the gate terminal potentials thereof are individually determined by the charge pumping of the capacitance elements. After these MOS transistors PQ1 and PQ2 are brought into a blocking state, the voltage levels of the nodes ND1 and ND2 be changed reliably and quickly according to the control signals.
  • For the sake of simplicity, the effect of parasitic capacitance on the internal node ND2 neglected in the description above. If the internal node ND2 has a parasitic capacitance of a non-negligible size, is the voltage amplitude at the node ND2 less than the supply voltage VCC and accordingly is the absolute value of the output voltage of the output node OD1 decreased.
  • That is the voltage amplitude of the internal node ND2 determining control signal ΦCP is between the supply voltage VCC and the ground voltage GND changed. However, with tension Vr instead of the ground voltage GND as reference voltage and with the control signal ΦCP with a voltage amplitude an output voltage VOUT the starting node OD1 through the following relationship ( 1 ) are expressed: VOUT = Vr - V Φ
    Figure DE102004024612B4_0001
  • General is the reference voltage Vr as in the above description of the operations equal to the ground voltage GND or 0V, and the control signal ΦCP is generated by a circuit that uses the supply voltage VCC and the ground voltage GND used as operating supply voltages. Therefore, suppose that the voltage amplitude equal to the supply voltage VCC is the above relationship ( 1 ) in the following relationship ( 2 ) can be changed: VOUT = - VCC
    Figure DE102004024612B4_0002
  • In the above description, all control signals ΦP . ΦCP and ΦCT between the supply voltage VCC and the ground voltage GND switch, and are the same voltage levels in the high level state and in the low level state. However, the high level states of these control signals ΦP . ΦCP and ΦCT have a different voltage level from each other, and the low-level states thereof may have a different voltage level from each other provided the MOS transistors PQ1 . PQ2 . NQ1 and NQ2 be brought into the blocking state, so that current flow in a direction opposite to that of the voltage change after the voltage change of the internal nodes ND1 . ND2 and ND3 is prevented.
  • According to the first embodiment of the first invention, as described above, the cross-coupled P-channel MOS transistors are used, and the gate terminal potentials thereof are determined by the charge pumping operation of the capacitance elements. In addition, the on / off state of the output transistor is determined by the control signal. Thus, it becomes possible to prevent the flow of an unnecessary current after the potential of the charge accumulation node is changed, so that the voltage at an intended level can be generated efficiently.
  • Second embodiment
  • 3 shows a structure of a voltage generating circuit according to a second embodiment. In the 3 The voltage generating circuit shown uses the supply voltage VCC as a reference voltage and generates a high voltage of 2 · VCC that is higher than the supply voltage VCC ,
  • In 3 includes the voltage generating circuit: an N-channel MOS transistor NQ11 between a voltage supply node (reference node) PW and an internal node (first internal node) ND11 is switched, and the one with an internal node (second internal node) ND12 has connected gate connection; an N-channel MOS transistor NQ12 that is between a power supply node PW and an internal node ND12 is switched, and the one with the internal node ND11 has connected gate connection; a capacity element (first capacity element) C11 between a first control signal ΦPZ receiving control signal input node (first control signal input node) S11 and an internal node ND11 is switched; and a capacity element (second capacity element) C12 that between a control signal ΦCPZ receiving control signal input node (second control signal input node) S12 and an internal node ND12 is switched.
  • The control signal ΦPZ and ΦCPZ alternate between the supply voltage VCC and the ground voltage GND ,
  • The voltage generating circuit further includes: a P-channel MOS transistor (third transistor) PQ11 that is between the internal nodes ND12 and an exit node OD11 is switched, and the one with an internal node (third internal node) ND13 has connected gate connection; a P-channel MOS transistor (fourth transistor) PQ12 that is between the internal nodes ND13 and the output node OD11 is switched and one with the internal node ND12 has connected gate connection; and a capacity element (third capacity element) G13 that between a control signal ΦCTZ receiving control signal input node (third control signal input node) S13 and the internal node ND13 is switched.
  • In the above description, the elements in the parentheses correspond to the elements in the claims. The control signal ΦCTZ changes between the supply voltage VCC and the ground voltage GND ,
  • The exit node OD11 is provided with a stabilizing capacity C14 to stabilize a voltage at the output node OD11 , This stabilizing capacity C14 need not be provided when changing the load on the output node OD11 is low.
  • One in 3 The voltage generating circuit shown is the same as the voltage generating circuit 1 , provided the conductivity types of the transistors are inverted and the ground node and the supply node are interchanged. The control signals ΦPZ . ΦCPZ and ΦCTZ are complementary to the control signals ΦP . ΦCP and ΦCT out 1 ,
  • 4 Fig. 10 is a signal waveform diagram showing an operation of the voltage generating circuit 3 illustrated. Illustrated for simplicity 4 also the signal waveforms in the case when the output voltage is stable at the level of 2 · VCC. Regarding 4 operation of the voltage generating circuit is now carried out 3 to be discribed.
  • In the voltage generating circuit 3 As described above, the conductivity types of the transistors in the circuit are made of 1 which is the negative voltage -VCC generated, inverted. Therefore, similar operations are carried out. The flow of a leakage current can thus be prevented.
  • By the time t0 are the control signals ΦPZ . ΦCPZ and ΦCTZ at the level of the supply voltage VCC , the ground voltage GND or the supply voltage VCC , The node is in this state ND11 at a high voltage level of 2 · VCC and the node ND12 is at the level of the supply voltage VCC (in the stable state). The MOS transistor NQ11 has a power supply node PW , which serves as the source connection, and whose gate and source connection are at the same voltage level, and the MOS transistor NQ11 is put in the locked state.
  • Even if the MOS transistor NQ12 receiving a potential of the high voltage of 2 * VCC at the gate terminal is the voltage level of the node ND12 and the power supply node PW same, so no current between drain and source of the MOS transistor NQ12 flows.
  • The knot ND13 is at the high voltage level of 2 · VCC, and the MOS transistor PQ11 has a gate connection at a potential not below that of the source and drain connection, and the MOS transistor PQ11 remains locked. When the output voltage is stable, the node is ND12 at the level of the supply voltage VCC , and therefore the MOS transistor PQ12 in the open state. In addition, the voltage levels of the node ND13 and the output node OD11 same, so no current through the MOS transistor PQ12 flows.
  • In a transitional period, such as the start of charge pumping when the voltage of the output node OD11 is less than the level of the final voltage of 2 · VCC, the MOS transistor is PQ12 brought to the knot ND13 electrically with the output node OD11 to connect when the voltage level of the node ND12 is made lower than the voltage level of the nodes ND13 and the output node OD11 , In this case, however, a current flows in the direction of the rising voltage level of the output node OD11 , Therefore, no leakage current flows, causing the voltage rise of the output node OD11 with special needs. In this process, the flow of current through the MOS transistor ends PQ12 when the voltage level of the output node OD11 and the knot ND13 align with each other. Are in this state because of the output node OD11 as the source connection of the MOS transistor PQ11 serves the potentials of the gate and source connection of the MOS transistor PQ11 the same, and the MOS transistor PQ11 remains in the locked state.
  • By the time t1 the control signal falls ΦPZ from the level of the supply voltage VCC to the level of the ground voltage GND , The MOS transistor NQ11 goes into the locked state, and the charge pumping through the capacitance element C11 reduces the voltage level of the node ND11 from the high voltage of 2 · VCC to the supply voltage VCC , The node is in this state ND12 at the level of the supply voltage VCC and the MOS transistor NQ12 is in the locked state. The potential of the knot ND12 causes no change and no leakage current flows in this state.
  • For now t2 the control signal increases ΦCPZ from the level of the ground voltage GND to the level of the supply voltage VCC and the voltage level of the node ND12 increases from the supply voltage VCC to the high voltage of 2 · VCC. In this state, even if the MOS transistor NQ11 goes into the on state, the voltage level of the node ND11 and the supply voltage node PW the same and therefore no electricity flows. If the internal node ND12 reaches the high voltage level of 2 · VCC, is the gate of the MOS transistor PQ12 set to a potential not less than the source and drain potential, and the MOS transistor PQ12 is reliably set to the locked state. The gate connection of the MOS transistor PQ11 is on the high voltage of 2-VCC. Even if the voltage level of the node ND12 is raised to the high voltage of 2 · VCC, serves the MOS transistor PQ11 the knot ND12 as a source connection, its gate connection is brought to the same potential as its source connection, and therefore the MOS transistor remains PQ11 in the locked state.
  • In the transition state, in which the voltage of the output node OD11 is lower than the high final voltage of 2 · VCC, the MOS transistor goes PQ12 due to the potential increase of the node ND12 in the locked state. The exit node OD11 and the internal node ND13 are already electrically connected and are set to the same voltage level. The gate-source voltage of the MOS transistor PQ11 is in this state at most at a level whose absolute value is less than the threshold voltage of the MOS transistor PQ11 , and the MOS transistor PQ11 remains in the locked state.
  • The MOS transistors NQ11 . NQ12 . PQ11 and PQ12 are each of the enhancement type and only go into the off state when the gate-source voltage thereof reaches a level whose absolute value is equal to or higher than the threshold voltage.
  • By the time t3 the control signal falls ΦCTZ from the level of the supply voltage VCC to the level of the ground voltage GND , According to the drop in the control signal ΦCTZ lowers charge pumping through the capacitance element C13 the voltage level of the node ND13 from the high voltage of 2 · VCC to the supply voltage VCC and the gate of the MOS transistor PQ11 is at a much lower potential than the source connection, so the MOS transistor PQ11 goes into the pass state for electrical coupling of the node ND12 at the exit node OD11 ,
  • If the voltage level of the output node OD11 is less than the final voltage level of 2 · VCC positive charges from the internal node ND12 at the exit node OD11 supplied, and the voltage level of the output node OD11 rises. In this process of delivering loads to the output node OD11 is the potential of the gate of the MOS transistor PQ12 equal to or higher than that of the source, and the MOS transistor PQ12 remains in the locked state. Therefore, no current flows.
  • By the time t4 the control signal increases ΦCTZ from the level of the ground voltage GND to the level of the supply voltage VCC on. The charge pumping through the capacitance element C13 raises the voltage level of the node ND13 from the supply voltage VCC to the high voltage of 2 · VCC. The potential of the gate of the MOS transistor PQ11 is equal to or higher than that of the source thereof, and the MOS transistor PQ11 goes into the locked state.
  • In the transition period when the voltage level of the output node OD11 is less than the high voltage of 2 · VCC, the MOS transistor goes PQ12 in the pass state. Even in this state, however, positive charges from the node ND13 at the exit node OD11 supplied so that the voltage level of the output node OD11 is raised.
  • Especially when the voltage level of the output node OD11 is less than the high voltage of 2 · VCC, the voltage level of the node is normally in the transition period of the initial stage of charge pumping ND12 less than the high voltage of 2 · VCC, and the output node OD11 is essentially at the same voltage level (the voltage level of the node ND13 is set to the same voltage level as the output node before transferring charges). The gate-source voltage of the MOS transistor is therefore in this state PQ12 of the enhancement type not higher than the absolute value of the threshold voltage, and the MOS transistor PQ12 remains in the locked state.
  • In this transition period is the potential of the gate of the MOS transistor PQ11 higher than that of the source connection (output node OD11 ), and therefore the MOS transistor remains PQ11 in the locked state. Thus, no leakage current flows from the output node OD11 to the internal node ND12 ,
  • By the time t5 the control signal falls ΦCPZ from the level of the supply voltage VCC to the level of the ground voltage GND , The charge pumping through the capacitance element C12 reduces the voltage level of the node ND12 from the high voltage of 2 · VCC to the supply voltage VCC , The knot ND11 is at the level of the supply voltage VCC , The potential of the source and gate connection of the MOS transistor NQ12 is equal to each other, and the MOS transistor NQ12 remains in the locked state.
  • The gate connection potential of the MOS transistor PQ12 becomes lower than the voltage level of its source connection (output node OD11 ), and the MOS transistor PQ12 goes into the pass state, so the output node OD11 with the internal node ND13 is electrically connected. By connecting the internal node ND13 and the output node OD11 is the potential of the gate and source connection of the MOS transistor PQ11 equal, and thus the MOS transistor remains PQ11 in the locked state. Therefore, even if the internal node flows ND13 is charged only a current needed to transfer charges accurately to the output node and no leakage current flows.
  • In the transition period, even if the voltage level of the node ND13 when raising the voltage level of the internal node ND12 through the control signal ΦCPZ becomes lower than the voltage level of the internal node ND12 , the MOS transistor PQ11 held in the off state (the gate-source voltage is not held higher than the absolute value of the threshold voltage).
  • In the transition period, the voltage level of the node can ND12 below the supply voltage VCC decrease when the voltage at the output node OD11 has not yet reached the final voltage level. The node is in this state ND11 at the level of the supply voltage and the nodes ND12 is held at the voltage level around the threshold voltage of the MOS transistor NQ12 is lower than the supply voltage VCC , A current that flows in this state is only supplied by the supply node PW through the MOS transistor NQ12 to equalize the voltage level. There is no leakage current.
  • By the time t6 the control signal increases ΦPZ from the level of the ground voltage GND to the level of the supply voltage VCC , The charge pumping through the capacitance element C11 raises the voltage level of the node ND11 from the supply voltage VCC to the high voltage level of 2 · VCC so that the MOS transistor NQ12 is brought into the pass state, and the node ND12 is reliable to the level of the supply voltage VCC set.
  • Therefore, no leakage current flows to the supply voltage during the precharging periods VCC , charging to the high voltage 2 * VCC and transferring the accumulated charges to the output node to the internal node ND12 serving as a charge accumulation node according to the control signals ΦPZ . ΦCPZ respectively. ΦCTZ , Therefore, the charges can be effectively used to generate a high voltage of 2 · VCC.
  • When building the voltage generating circuit out 3 becomes the presence of parasitic capacitance at the node ND12 neglected. If there is a non-negligible parasitic capacitance at the internal node ND12 is present, the amplitude of the voltage at the internal node ND12 less than the supply voltage VCC made. Thus, the output voltage is the output node OD11 consequently at a level less than the high voltage of 2 · VCC.
  • Generally assumed that the control signal ΦCPZ similar to the previous embodiment, the amplitude of has and that the power supply node PW on a tension VPW is the output voltage VOUT from the output node OD11 through the following relationship ( 3 ) reproduced: VOUT = VPW + V Φ
    Figure DE102004024612B4_0003
  • Therefore, the amplitude of the control signal ΦCPZ set according to a required voltage level. In the in 3 The structure shown is the voltage supply node PW at a level of the supply voltage VCC and the control signal ΦCPZ has the amplitude of the supply voltage VCC so that the output voltage VOUT through the following relationship ( 4 ) can be reproduced: VOUT = 2 VCC
    Figure DE102004024612B4_0004
  • It is necessary that the control signals ΦPZ . ΦCPZ and ΦCTZ are equal in voltage to each other in the high level state and in the low level state. The high level and the low level of the control signals ΦPZ . ΦCPZ and ΦCTZ can be different from each other, provided the internal node is preloaded ND12 , the delivery of charges and the transfer of charges can be carried out during the on / off states of the MOS transistors NQ11 . NQ12 . PQ11 and PQ12 are ensured.
  • According to the second embodiment, as described above, the N-channel MOS transistors are cross-coupled, and the charge accumulation node is charged by using the charge pumping operation of the capacitance element. The charges can be delivered to the charge accumulation node after the MOS transistors are turned off. Thus, leakage current can be prevented, and a positive high voltage can be generated efficiently.
  • Third embodiment
  • 5 schematically shows a structure of an internal voltage generation circuit according to a third embodiment.
  • In 5 includes the internal voltage generating circuit: a control signal generating circuit 1 to generate the control signals ΦP, ΦCP and ΦCT according to a repeat signal Φ0 ; a negative voltage generating circuit 10 to generate a negative voltage -VCC according to control signals ΦP . ΦCP and ΦCT by the control signal generating circuit 1 be received; an inverter circuit 15 for inverting control signals ΦP . ΦCP and ΦCT such that control signals ΦPZ . ΦCPZ respectively. ΦCTZ be generated; and a positive voltage generation circuit 20th for generating a positive voltage of 2 · VCC according to control signals ΦPZ . ΦCPZ and ΦCTZ by the inverter circuit 15 are created.
  • The negative voltage generation circuit 10 has a structure similar to that of the voltage generating circuit 1 and the positive voltage generating circuit 20th has a structure similar to that of the voltage generating circuit 3 is. The control signal generation circuit 1 is for the negative and positive voltage generating circuits 10 and 20th provided together. The internal voltages at intended levels of -VCC and 2 · VCC can be generated efficiently with a reduced occupation area.
  • 6 schematically shows a structure of a control signal generating circuit 1 out 5 , In 6 includes the control signal generating circuit 1 : step delay circuits 30a to 30d of four stages for receiving the repetition signal Φ0 ; an inverter 32a which is an output signal Φ1 the delay circuit 30a receives; an inverter 32b which is an output signal Φ3 the delay circuit 30c receives; and an OR circuit 33 which is the output signal of the inverter 32a and an output signal Φ4 the delay circuit 30d receives a control signal ΦCP to create; and an AND circuit 34 which is the output signal Φ2 the delay circuit 30b and the output signal of the inverter 32b receives the control signal ΦCT to create.
  • Each of the delay circuits 30a to 30d is formed from an even number of stages of the step-shaped inverters and has a delay time DP.
  • 7 Fig. 12 is a signal waveform diagram showing an operation of the control signal generating circuit 1 out 6 illustrated. Regarding 7 the operation of the in 6 control signal generating circuit shown 1 to be discribed.
  • The repeat signal Φ0 has a constant period and is also used as a control signal ΦP used for preloading. The delay circuits 30a to 30d delay the received signals by a predetermined time DT such that respective delayed signals Φ1 to Φ4 be generated.
  • The OR circuit 33 receives the output signals of the inverter 32a and the output signal Φ4 the delay circuit 30d to the control signal ΦCP to generate for the accumulation of charges. Therefore, the period of time in which the control signal ΦCP at an L level (logic low level) is formed by the period of time in which the output signal Φ4 the delay circuit 30d at an L level and the output signal Φ1 the delay circuit 30a is at an H level (logic high level). The control signal therefore falls ΦCP to the L level when the output signal Φ1 the delay circuit 30a rises to H level, and rises to H level when the output signal Φ4 the delay circuit 30a rises to the H level. Accordingly, the control signal ΦCP held at the L level for a period of 3 * DT.
  • That from the AND circuit 34 applied control signal ΦCT for charge transfer is at the H level when the output signal Φ2 the delay circuit 30b at the H level and the output signal of the inverter 32b is at the H level. Therefore, the control signal reaches ΦCT the H level when the output signal Φ2 the delay circuit 30b rises to the H level and reaches the L level when the output signal Φ3 the delay circuit 30c reached the H level. The control signal ΦCT will be for the period of DT kept at H level.
  • The high level states of the output signals Φ1 to Φ4 of the delay circuits 30a to 30d are at the level of the supply voltage VCC , and the low level states thereof are at the level of the ground voltage GND , In this case it is for the control signals ΦP . ΦCP and ΦCT the high level state at the level of the supply voltage VCC and the low state at the ground voltage level GND , By changing the level of the operating supply voltage of the control signal generating circuit 1 it is possible to control the amplitudes and voltage levels of the high level and the low level of the control signals ΦP . ΦCP and ΦCT to change.
  • The repeat signal Φ0 can be generated by an internal oscillator circuit or can be formed from a clock signal which is provided externally for signal transmission, the establishment of operating cycles and other repetitive.
  • The positive voltage generation circuit 20th works according to control signals ΦPZ . ΦCPZ and ΦCTZ by inverting control signals ΦP . ΦCP respectively. ΦCT be generated. By using these control signals, it is possible to determine the phase relationship between the control signals in the timing diagrams of the 2 and 4 to reach. Thus, after the MOS transistors are turned off, the charge pumping operation can be performed to accumulate the charges to generate an internal voltage, and then the MOS transistors can be turned on to transfer the charges.
  • In the construction of the control signal generation circuit 1 out 6 have the delay circuits 30a to 30d the same delay time DT , The delay circuits 30a to 30d can have different delay times, provided the following control signal sequence is fulfilled. If a predetermined time after changing the voltage level of the control signal ΦP the control signal changes for precharging ΦCP for preloading. When a predetermined time has passed, the voltage level of the control signal changes ΦCT for the charge transfer such that the charge transfer is carried out. If the control signal ΦCT becomes inactive for the charge transfer, the logic level of the control signal changes ΦCP for the charge accumulation, and then the voltage level of the precharge control signal changes ΦP and precharging is done. Such an order must be achieved.
  • In the 5 The internal voltage generating circuit shown includes a negative voltage generating circuit 10 to generate a negative voltage -VCC and a positive voltage generation circuit 20th to generate a positive voltage of 2 · VCC. However, even in the case where only one of the two negative and positive voltage generating circuits 10 and 20th is used, the internal voltage at an intended level can be generated efficiently by using the control signal generating circuit 1 , The internal voltage generated can be at a level different from -VCC and 2 · VCC.
  • According to the third embodiment, as described above, the delay circuits are step-shaped, and the signals in an intended phase relationship are processed logically so that the control signals for charge precharging, charging and transferring are generated. Therefore, the control signals for the charge pumping operation for generating the internal voltages can be easily generated with a simple circuit structure.
  • Fourth embodiment
  • 8th shows a structure of a voltage generating circuit according to a fourth embodiment. The voltage generating circuit out 8th differs from the voltage generating circuit 1 in that a voltage driver stage 40 to increase an absolute value of an internal voltage generated additionally between the output nodes OD1 and a final exit node FOD is arranged.
  • The construction of the negative voltage generating section in front of the output node OD1 is the same as that in the voltage generating circuit 1 , Corresponding sections are provided with the same reference numerals and the description thereof is not repeated.
  • A voltage driver stage 40 includes: a capacity element C20 that between a control signal ΦP receiving control signal input node S31 and the output node OD1 is switched; an N-channel MOS transistor NQ31 that is between the internal output nodes OD1 and the final exit node FOD is switched and one with an internal node ND30 has connected gate connection; an N-channel MOS transistor NQ32 that is between the internal nodes ND30 and the final exit node FOD is switched and one with the internal output node OD1 has connected gate connection; and a capacity element C21 that between a control signal ΦCTF receiving control signal input node S32 and an internal node ND30 is switched.
  • The final exit node FOD is similar to the first embodiment with a stabilizing capacity C4 Mistake. However, the stabilizing capacity C4 be omitted if the change in output load is small.
  • The control signal ΦCTF becomes active when negative charges from the output node FOD to the internal output node OD1 are to be delivered. The control signals ΦP . ΦCP and ΦCT are the same as those in the first embodiment.
  • 9 Fig. 10 is a timing chart showing an operation of the voltage generating circuit 8th illustrated. Regarding 9 the operation of the voltage generating circuit will now stop 8th described. 9 also illustrates Signal waveforms in the stable state over a period of 2 · T. Operation in the steady state is described below. In a transition period in the initial stage of the charge pumping operation, an operation is carried out as in the stable state, although the respective nodes reach different voltage levels.
  • The control signals ΦP . ΦCP and ΦCT are the same as those in the first embodiment, and therefore the operation of the circuit is above the output node OD1 basically the same as that in the first embodiment. However, the voltage amplitude is the internal output node OD1 different from that in the first embodiment, so the voltage change at the internal node ND3 is different from that in the first embodiment.
  • At a time t10 are the control signals ΦP and ΦCT is set to the L level and is the control signal ΦCP set to the H level. The node is in this state ND1 to the level of the negative voltage -VCC and is the exit node OD1 at the negative voltage level of -2 · VCC. Hence the knot ND1 to the level of the negative voltage -VCC driven, and the knot ND2 is at the level of the ground voltage GND preloaded. Next is the internal exit node OD1 on the negative voltage of -2 · VCC, the MOS transistor NQ2 is in the pass state, and the internal node ND3 is electrical with the internal output node OD1 connected and kept at the same voltage level.
  • By holding the internal knot ND3 and the internal output node OD1 the MOS transistor is at the same voltage level NQ1 kept in the locked state.
  • By the time t11 the control signal increases ΦP from the level of the ground voltage GND to the level of the supply voltage VCC on. In response, the capacity element drives C1 the knot ND1 to the level of the ground voltage GND , and the preload operation on the node ND2 is closed. In this state, a capacitance element lifts C20 the voltage level of the output node OD1 from -2 · VCC -VCC on. The node is in this state ND2 at the level of the ground voltage GND and the MOS transistor NQ2 remains in the pass state, so the internal node ND3 the same voltage level as the internal output node OD1 reached and the level of negative voltage -VCC reached.
  • The gate connection (node ND3 ) and the source connection (internal output node OD1 ) of the MOS transistor NQ1 are set to the same potential, and the MOS transistor NQ1 remains in the locked state.
  • At a time t12 the control signal falls ΦCP from the level of the supply voltage VCC to the level of the ground voltage GND , and the knot ND12 gets to the level of negative voltage -VCC driven so that the N-channel MOS transistor NQ12 goes into the locked state. The node is in this state ND2 at the level of the negative voltage -VCC , and gate, source and drain connection of the MOS transistor NQ1 are all at the same potential in the stable state, so the MOS transistor NQ1 remains in the locked state. In a transition period is the gate-source voltage of the MOS transistor NQ1 at a voltage that does not exceed the threshold voltage as in the first embodiment, and the MOS transistor NQ1 remains locked.
  • By the time t13 the control signal increases ΦCT from the level of the ground voltage GND at the level of the supply voltage VCC and the voltage level of the node ND3 rises from the negative tension -VCC to the ground voltage GND on. The MOS transistor NQ1 goes to the pass state to the node ND2 electrically with the output node OD1 to connect, and the internal node ND2 and the internal output node OD1 are brought to the same voltage level. However, the internal output node is in the stationary state OD1 already at the level of the negative voltage -VCC precharged, and the drain potential and the source potential of the MOS transistor NQ1 are matched to each other so that no current flows through them when stationary.
  • By the time t14 the control signal falls ΦCT from the level of the supply voltage VCC to the level of the ground voltage GND , and the voltage level of the node ND3 decreases from the ground voltage GND to the negative tension -VCC , In response, the MOS transistor goes NQ1 in the locked state to the node ND2 from the internal output node OD1 to separate. The gate, drain and source connection of the MOS transistor are in the stable state NQ2 set to the same potential, and the MOS transistor NQ2 doesn't let electricity through.
  • By the time t15 the control signal increases ΦCP from the level of the ground voltage GND to the level of the supply voltage VCC and the voltage level of the node ND2 rises from the negative tension -VCC to the ground voltage GND on. According to the increase in the voltage level of the node ND2 is the MOS transistor PQ1 brought into the locked state to spread a next precharge.
  • Next is the MOS transistor NQ2 placed in the pass state to the internal node ND3 and the internal output node OD1 electrically connect with each other, and the internal node ND3 reaches the same voltage level as that on the internal output node OD1 , ie the level of the negative voltage -VCC , so the gate and source of the MOS transistor NQ1 are set to the same voltage, and the MOS transistor NQ1 is held in the locked state.
  • By the time t16 the control signal falls ΦP from the level of the supply voltage VCC to the level of the ground voltage GND , and in response the voltage at the node drops ND1 from the level of the ground voltage GND to the level of the negative voltage -VCC , In addition, the capacity element decreases C20 the potential at the internal output node OD1 from the level of the flat negative voltage -VCC to the level of the deep negative voltage of -2 · VCC. The knot ND2 is at the level of the ground voltage GND and the MOS transistor NQ2 is in a pass state, so the node ND3 and the internal output node OD1 are at the same voltage level, and the MOS transistor NQ1 is held in the locked state. The potential at the internal output node therefore drops OD1 , even if the knot ND2 at the level of the ground voltage GND is to the deep negative voltage level of -2-VCC, and also the potential at the node ND3 drops to the low negative voltage level of -2-VCC.
  • In this case the MOS transistor goes NQ1 quickly into the blocking state, since the source connection and the gate connection of the MOS transistor NQ1 through the MOS transistor NQ2 are electrically connected so that hardly any leakage current flows, and the potential at the internal output node OD1 reliably drops to the negative voltage level of -2 · VCC.
  • In a transition period and others, the voltage level of the internal node ND30 possibly the voltage level of the internal output node OD1 exceed. However, the internal node ND30 once electrically with the final output node FOD connected, and a difference in voltage level between the internal nodes ND30 and the internal output node OD1 is minor in such a state. Therefore, the MOS transistor holds NQ1 maintain the blocking state due to its threshold voltage.
  • By the time t17 the control signal increases ΦCTF from the level of the ground voltage GND to the level of the supply voltage VCC , and the voltage level of the node ND30 increases from the deep negative voltage -2 · VCC to the flat negative voltage -VCC on. In response, the MOS transistor goes NQ31 in the pass state to the output node OD1 with the final exit node FOD electrically connect with each other. When the voltage level of the final output node FOD is higher than the low negative voltage -2 · VCC, negative charges from the internal output node OD1 to the final exit node FOD delivered. In this charge transfer mode, the gate and source connection (final output node FOD ) of the MOS transistor NQ2 set to the same potential, and the MOS transistor NQ2 remains in the locked state. Thus the charges take effect from the internal output node OD1 at the final exit node FOD transfer.
  • By the time t18 the control signal increases ΦP from the level of the ground voltage GND at the level of the supply voltage VCC on. In response, the knot returns ND1 from the level of the flat negative voltage -VCC to the level of the ground voltage GND back, and the output node OD1 increases from the low negative voltage level of -2 · VCC to the flat negative voltage level -VCC on. The node is in this state ND2 at the ground voltage level and the voltage level at the node ND3 increases, similar to the starting node OD1 , from the deep negative voltage -2 · VCC to the negative voltage -VCC on.
  • By the time t19 and then the processes described are repeated.
  • If the output node OD1 to the level of deep negative voltage -2 · VCC drops to the voltage level of the node ND23 to lower the level of the deep negative voltage 2 · VCC, the voltage level of the node ND3 reliable and fast according to the voltage level of the output node OD1 with the capacity element C20 , which has a capacity value much larger than the capacity element C3 owns, be changed.
  • In the initial period at the start of the charge pumping operation, the voltage of the final output node drops FOD to -2 · VCC after the voltage at the output node OD1 between -VCC and -2 · VCC changes. Operation of the voltage driver stage 40 in this transition period is similar to that of the voltage generating circuit previously described in connection with the first embodiment.
  • The voltage driver stage 40 has a structure similar to that of an output stage (charge transfer stage) of a circuit which has the negative voltage -VCC generated, and is arranged in the ( -VCC ) Generation circuit in the previous Step. Therefore, the deep negative voltage of -2 · VCC can be generated without causing leakage current flow.
  • According to the fourth embodiment, as described above, the output stage of the circuit which is the flat negative voltage -VCC generated, further connected to the charge pumping capacity of the output node, and the output stage (charge transfer stage) of the same construction as the output stage of the ( -VCC ) Generating circuit is arranged such that it forms the voltage driver stage. This enables the charges to be used efficiently to generate the negative voltage of -2.VCC with low power consumption.
  • Fifth embodiment
  • 10A schematically shows a structure of a voltage generating circuit according to a fifth embodiment.
  • The voltage generating circuit out 10A includes charge transfer stages XFN1 . XFN2 , ... and XFNn that are cascading between the nodes ND2 and the output node FOD are arranged.
  • The P-channel MOS transistors PQ1 and PQ2 are cross-coupled and between the ground node and the node ND1 and ND2 arranged. The knot ND1 receives the control signal ΦP for precharging via the capacitance element C1 , and the knot ND2 receives the control signal ΦCP for the generation of charges via the capacity element C2 , The MOS transistors PQ1 and PQ2 , as well as the capacity elements C1 and C2 have the same structure as that in the 1 and 8th shown, and the voltage level at the nodes ND1 and ND2 is according to control signals ΦP and ΦCP between the ground voltage GND and the negative tension -VCC changed.
  • The capacity elements CK1 to CKn-1 are each with respective output nodes OD1 to ODn-1 the charge transfer stages XFN1 to XFNn-1 connected. In charge transfer stages XFN1 . XFN3 , ... and XFNn-1 receive capacity elements in odd-numbered stages CK1 , ..., CKn-1 that are at respective output nodes OD1 . OD3 , ... and ODn-1 are arranged, the control signal ΦP via the control signal input node S1 , In charge transfer stages XFN2 ... receive capacity elements in even-numbered stages CK2 ... at the respective output nodes OD2 ... are arranged, the control signal ΦCP via control signal input nodes S2 , The charge transfer stages XFN1 to XFNn alternately receive control signals ΦCT and ΦCTF , The charge transfer stage and the capacitance element which is arranged at a respective input node (ie the output node of the preceding charge transfer stage) form the voltage driver stage.
  • The final exit node FOD is with the stabilizing capacity element C4 connected. When the voltage on the final output node FOD the stabilizing capacity element can be stable C4 be omitted.
  • 10B shows a structure of the charge transfer stages XFN1 to XFNn , The charge transfer stages XFN1 to XFNn have the same structure, and 10B shows the charge transfer stage XFN which are generally the charge transfer stages XFN1 to XFNn reproduces.
  • The charge transfer stage XFN includes: an N-channel MOS transistor NQa that is between an input node NDI and an exit node NDO is switched; an N-channel MOS transistor NQb that is between the output nodes NDO and an internal node NDA is switched, and one with the input node NDI has connected gate connection; and a capacity element Ca that is between the control signal input node Sat and the internal node NDA is switched.
  • The charge transfer stage XFN corresponds in structure to the voltage driver stage 40 out 8th except the capacity element C20 , The control signal input node Sa receives the control signal ΦCT or ΦCTF for controlling charge transfer. Preloading the entry node NDI and the charge transfer are carried out alternately in the charge transfer stages XFN1 to XFNn so that a voltage drop from -VCC in each of the charge transfer stages XFN1 to XFNn can be effected and a tension of -nVCC can at a final exit node FOD be generated.
  • 11 Fig. 10 is a timing chart showing an operation of the process shown in Figs 10A and 10B shown voltage generating circuit reproduces. 11 illustrates signal waveforms on the output and input nodes of the charge transfer stages XFNi-1 . XFNi and XFNi + 1 , The capacitance elements Ca of the charge transfer stages XFNi-1 . XFNi and XFNi + 1 are supplied with a control signal ΦCTF ΦCT respectively. ΦCTF , Regarding 11 is now the operation of the in the 10A and 10B described voltage generating circuit described.
  • If the control signal ΦP from the ground voltage GND on the supply voltage VCC increases, the voltage level of the Input node NDIi-1 the charge transfer stage XFNi-1 through the charge pump operation of the corresponding capacity element CKi-2 raised. In this case, the voltage level changes from a negative voltage - (i-1) · VCC to a negative voltage - (i-2) · VCC , The internal node is in this state NDAi-1 on the tension - (i-1) · VCC , and the MOS transistor NQa in the charge transfer stage XFNi-1 remains in the locked state.
  • In the charge transfer stage XFNi + 1 becomes the charge pump operation with effect on the input node NDi + 1 similarly according to the control signal ΦP executed, and the voltage level thereof changes from - (i + 1) · VCC on -iVC C. The entry node NDIi + 1 the charge transfer stage XFNi + 1 corresponds to the starting node ODi the charge transfer stage XFNi , In this case, the MOS transistor NQb in the charge transfer stage XFNi in a pass state and the level of the node changes accordingly NDIi of a tension - (i + 1) · VCC on -iVCC , Even in this state, the potential of the gate of the MOS transistor is NQa in the charge transfer stage XFNi less than the potential of its source, and therefore the MOS transistor NQa remains in the off state.
  • If the control signal ΦCP from the level of the supply voltage VCC to the level of the ground voltage GND falls, the capacity element leads CKi in the charge transfer stage XFNi charge pump operation such that the voltage at the input node NDIi of - (i-1) · VCC on -i-VCC changes. This operation is in the charge transfer stage XFNi-1 the knot NDIi-1 at the voltage level - (i-2) -VCC and the MOS transistor NQb is in a pass state, so the node NDAi-1 from the voltage level - (i-1) · VCC to the voltage level -iVCC increases.
  • When a predetermined period of time expires, the control signal ΦCT to the level of the supply voltage VCC driven. In the charge transfer stage XFNi through the capacitance element Ca, the charge pumping raises the voltage level of the input node NDAi of - (i + 1) · VCC on -i-VCC on, and the MOS transistor NQa goes into the pass state. As a result, the charges go through the MOS transistor NQa driven into the charge transfer stage XFNi. The node is in this state NDIi + 1 at the voltage level -iVCC , and the voltage level of the input node NDIi in the charge transfer stage XFNi becomes the voltage level of the input node NDIi + 1 in the charge transfer stage XFNi + 1 aligned.
  • If the control signal ΦCT falls back to the ground voltage level, the voltage level of the input node NDAi in the charge transfer stage XFNi around the supply voltage VCC decreased to the voltage level -i-VCC to achieve, and the MOS transistor NQa in the charge transfer stage XFNi goes into the locked state.
  • Then the control signal rises ΦCP from the level of the ground voltage GND to the level of the supply voltage VCC , and the voltage level of the input node NDIi the charge transfer stage XFNi rises. In response, the voltage level at the internal node NDAi-1 in the charge transfer stage XFNi-1 through the MOS transistor NQb according to the voltage level of the node NDi raised and to the voltage level of - (i-1) · VCC set.
  • According to the control signal ΦCP the voltage level of the internal node also drops NDAi-1 in the charge transfer stage XFNi + 1 , so the corresponding MOS transistor NQa is brought into the locked state when the voltage level of the output node ODi + 1 sinks.
  • When a predetermined time elapses, the control signal falls ΦP from the level of the supply voltage VCC to the level of the ground voltage GND , In response, the capacitance element performs in the charge transfer stage XFNi + 1 charge pump operation on the input node NDIi + 1 off, and the voltage level thereof drops from -iVCC on - (i + 1) · VCC , This voltage drop is across the MOS transistor NQb on the internal nodes NDAi the charge transfer stage XFNi transferred, and this MOS transistor NQb is reliably brought into the locked state.
  • After another predetermined period of time expires, the control signal reaches ΦCTF the level of the supply voltage VCC and holds this level for a predetermined period of time, and the voltage levels of the internal nodes NDAi-1 and NDAi + 1 in the charge transfer stages XFNi-1 and XFNi + 1 be around the supply voltage VCC raised so that the corresponding MOS transistor NQa goes into the pass state to transfer charges.
  • In the above process is for the charge transfer stage XFNi the voltage level of the internal node NDAi equal to the voltage level of the input node NDIi + 1 the charge transfer stage XFNi + 1 , and therefore equal to the voltage level of the output node ODi the charge transfer stage XFNi , and thus the MOS transistor remains NQa in the blocked state, the backflow of current into the charge transfer stage XFNi to prevent.
  • Accordingly, cascading charge transfer stages XFN1 to XFNn and by alternately performing the precharge of the input nodes and the charging of the connected internal nodes according to phased control signals in these charge transfer stages, the backflow of the current can be reliably prevented, and the generated voltages can be reduced by the voltage VCC be reduced in the charge transfer stages. In the structure of the charge transfer stages XFN1 to XFNn of the n levels is at the exit node FOD a tension -nVCC generated. Thus, it is possible to generate a negative voltage with an intended voltage level, and a required voltage level can be stably generated with a low power consumption even under the condition of a low supply voltage.
  • 12 shows schematically a structure of a circuit for generating the control signals, which in the in the 10A and 10B shown voltage generating circuit can be used. In addition to the components of the control signal generating circuit 6 includes the in 12 Signal generation circuit shown an AND circuit 45 that have an output signal Φ4 the delay circuit 30d and the output signal of the inverter 32b receives the control signal ΦCTF to create. Other components of the in 12 control signal generating circuit shown are the same as those of the control signal generating circuit 6 , Corresponding sections are provided with the same reference numerals and the description thereof is not repeated.
  • According to the structure of the control signal generating circuit 12 generates the AND circuit 45 the control signal ΦCTF at the H level when the output signal Φ4 the delay circuit 30d at the H level and the output signal of the inverter 32b is at the H level. As in 13 the control signal is therefore shown ΦCTF at the H level when the output signals Φ3 and Φ4 of the delay circuits 30c and 30d on the Lbzw. Are H levels. The other control signals ΦP . ΦCP and ΦCT are produced from the same components as those in the in 6 circuit shown and have the same temporal relationship. By using the control circuit 12 For each charge transfer stage, when the negative charges are provided at its input node to be ready for transfer of the charges, the charge transfer control signal can be accurately applied to transfer the charges to the output node. In addition, the backflow of the current can be prevented.
  • According to the fifth embodiment, as described above, the plurality of charge transfer stages are cascaded, and charge transfer and precharge of the input node are carried out alternately in the respective charge transfer stages, so that a deep negative voltage with low power consumption can be generated.
  • Sixth embodiment
  • 14 shows a structure of a voltage generating circuit according to a sixth embodiment. In addition to the components of the voltage generating circuit 3 includes the voltage generating circuit 14 further a voltage driver stage 50 for transferring charges of the output node OD11 to the final exit node FOD according to the control signals ΦPZ and ΦCTFZ ,
  • The voltage driver stage 50 includes a capacitance element CC, which is a charge pumping operation on the internal output node OD11 according to the control signal ΦPZ performs, and a charge transfer stage XFP which are the electrical charges in the capacitance element CC to the final exit node FOD according to the control signal ΦCTFZ transmits.
  • The charge transfer stage XFP includes: a P-channel MOS transistor PQa that is between the internal output nodes OD11 and the final exit node FOD is switched and one with an internal node NDB has connected gate connection; a P-channel MOS transistor PQb that is between the internal nodes NDB and the final exit node FOD is switched and one with the internal output node OD11 has connected gate connection; and a capacity element CD that between a control signal ΦCTFZ receiving control signal input node S52 and the internal node NDB is switched. The charge transfer stage XFP has an input node PDI that with the internal output node OD11 is connected, as well as one to the final output node FOD connected output node POD ,
  • In the in 14 The voltage generating circuit shown is one in front of the output node OD11 for generating a voltage 2 · VCC arranged circuit formed from a section for generating the voltage lifting charges and a section for transmitting the voltage lifting charges. This charge generation section and this charge transfer section have the same construction as those in FIG 1 circuit shown. Corresponding components have the same reference numerals and the description thereof is not repeated.
  • 15 FIG. 10 is a signal waveform diagram showing an operation of the in FIG 14 shown voltage generating circuit shows in the stable state. Regarding 15 will now operate from the stable state of the voltage generating circuit 14 described.
  • The voltage generating circuit out 14 is the same as the voltage generating circuit 8th , provided that the conductivity types of the transistors, the polarities of the control signals and the polarities of the voltages are interchanged. Basically, the charge pump operation is for the charges of the node ND12 in the voltage generating circuit 14 the same as the one in 3 circuit shown, and the capacitance element C12 changes the voltage level of the node ND12 between the supply voltage VCC and the high voltage 2 · VCC according to the control signal ΦCPZ , The capacity element CC changes the voltage level of the internal output node OD11 by the charge pump operation according to the control signal ΦPZ , Therefore the internal output node changes OD11 between the tensions 2 · VCC and 3 · VCC , Because the voltage level of the internal output node OD11 yourself up to 3 · VCC changes, the voltage level of the internal node changes ND13 between the supply voltage VCC and the high tensions 2 · VCC and 3 · VCC over three levels.
  • By the time t11 the control signal falls ΦPZ from the supply voltage VCC to the ground voltage GND from. In response, the exit node OD11 through the charge pump operation of the capacitance element CC to the voltage level 2 · VCC set. In this process is the knot ND12 to the level of the supply voltage VCC and the MOS transistor PQ12 is in a pass state, so the node ND13 , similar to the internal output node OD11 , the voltage level 2-VCC reached. Accordingly, the gate and source connection of the MOS transistor PQ11 at the same potential, and the MOS transistor PQ11 goes into the locked state.
  • By the time t12 the control signal increases ΦCPZ at the level of the supply voltage VCC , In response, the node's voltage level reaches ND12 the level of high voltage 2 · VCC so the mos transistor PQ12 goes into the locked state. Gate, drain and source connection of the MOS transistor PQ11 are set to the same voltage level in this state, and the MOS transistor PQ11 remains in the locked state.
  • In the voltage driver stage 50 is the control signal ΦCTFZ to the level of the supply voltage VCC , the knot NDB is on level 3 · VCC and the MOS transistor PQa is in the locked state. Because the internal output node OD11 at the voltage level 2 · VC C is, the transistor remains PQb in the on state, but no current flows through the MOS transistor PQb because the knot NDB and the final exit node FOD are at the same voltage level.
  • At a time t13 the control signal falls ΦCTZ from the level of the supply voltage VCC to the level of the ground voltage GND from. In response, the node's voltage level drops ND13 of the tension 2 · VCC on the supply voltage VCC so the mos transistor PQ11 in the pass state to charge between the internal output node OD11 and the internal node ND12 transferred to. This charge transfer process is complete when the internal node ND12 and the output node OD11 reach the same potential level.
  • In the charge transfer process, the MOS transistor reaches PQ12 the blocking state, since its gate and its source connection are set to the same voltage level. In this charge transfer process is the node NDB to the voltage level 3 · VCC , the internal output node OD11 is at the voltage level 2 · VCC and the P-channel MOS transistor PQa for the charge transfer remains in the locked state.
  • At a time t14 the control signal increases ΦCPZ from the level of the ground voltage to the level of the supply voltage VCC in response, and in response the node's voltage level increases ND13 from the supply voltage VCC to the high tension 2 · VCC on so the mos transistor PQ11 goes into the locked state. The MOS transistor remains in this process PQ12 due to its threshold voltage in the off state since the node ND12 at the voltage level 2 · VCC is.
  • By the time t15 the control signal falls ΦCPZ from the supply voltage VCC to the ground voltage GND from. In response, charge pumping through the capacitance element lowers C12 the voltage level of the node ND12 of the high tension 2 · VCC on the supply voltage VCC , If the voltage level of the node ND12 to the level of the supply voltage VCC drops to the P-channel MOS transistor PQ12 for electrically connecting the nodes ND13 and OD11 Bringing them into the open state is the node ND13 and the internal output node OD11 at the same voltage level 2 · VCC , and no current flows in the stable state. The MOS transistor PQ11 remains there in the locked state The gate connection and its source connection are at the same potential level.
  • By the time t16 the control signal increases ΦPZ from the level of the ground voltage GND to the level of the supply voltage VCC and the answer becomes the node ND11 to the level of the supply voltage VCC raised so that the knot ND12 reliably to the level of the supply voltage VCC is charged.
  • If the control signal ΦPZ increases, the capacity element leads CC through the charge pump operation to the output node OD11 from the level 2 · VCC to the level 3 · VCC to raise. When the voltage level of the output node OD11 at the voltage level 3 · VCC increases, is the knot ND12 to the level of the supply voltage VCC , and the MOS transistor PQ12 is brought into the pass state so that the node ND13 to the voltage level 3 · VCC increases, and the MOS transistor PQ11 remains locked.
  • By the time t17 the control signal falls ΦCTFZ from the level of the supply voltage VCC to the level of the ground voltage GND from. In response, charge pumping through capacitance element Cb reduces the voltage level of the node NDB of the tension 3 · VCC on the tension 2 · VCC and the MOS transistor PQa is brought into the forward state to the charges from the output node OD11 to the final exit node FOD to transmit, so the final exit node FOD reliable at the voltage level 3 · VCC is held. In this charge transfer process is the node NDB at the voltage level 2 · VCC and the output node OD11 and the final exit node FOD are at the same voltage level that is higher than that of the node NDB , The MOS transistor thus remains PQb in the locked state.
  • By the time t18 the control signal increases ΦCTFZ from the level of the ground voltage GND back to the level of the supply voltage VCC on. In response, charge pumping lifts through the capacitance element Cb the voltage level of the node NDB on the tension 3 · VCC on and the MOS transistor PQa goes into the locked state.
  • By the time t19 the control signal falls ΦPZ from the level of the supply voltage VCC to the level of the ground voltage GND so that the voltage level of the output node OD11 to 2 · VCC decreased. In this process, the MOS transistor PQ12 in an on state, so the voltage level of the node ND13 from 3 · VCC on 2 · VCC decreased. Then the above operations are repeated.
  • Accordingly, since there is a voltage driver stage 50 is arranged to precharge the output node to transfer the charges in the process of precharging the internal node, the voltage on this output node by the voltage VCC be raised, and the tension 3 · VCC can without end exit node FOD be generated.
  • For the sake of simplicity, the operation in the transition period of the initial charge pumping process is not described. However, an operation similar to that in the circuit that uses the negative voltage of -2 · VCC in the fourth embodiment is generated, performed, and the threshold voltages of the enhancement type transistors are used to gradually raise the voltage level of the final output voltage while preventing leakage current from occurring.
  • The stabilizing capacity C4 that are at the final exit node FOD can be omitted if the load changes at the final output node FOD are small.
  • Control signals ΦPZ . ΦCPZ . ΦCTZ and ΦCTFZ can be generated by inverting the output signals of the control signal generating circuits 12 ,
  • Similar to the second embodiment, therefore, control signals ΦPZ . ΦCPZ . ΦCTZ and ΦCTFZ not required to switch between the ground voltage GND and the supply voltage VCC , and can be replaced by signals that alternate between any desired voltages provided the on / off conditions of the device's MOS transistors are met.
  • According to the sixth embodiment, as described above, the capacitance element for the charge pump is arranged at the output node of the circuit, which is the voltage 2 · VCC generated, and a stage of the charge transfer stage is further arranged in the on / off of the charge transfer transistor PQa is controlled by the capacitance element and the MOS transistor, which detects the potential of the output node. Accordingly, the flow of leakage current charges is prevented, and the charges can be used efficiently to generate the high voltage 3 · VCC ,
  • Seventh embodiment
  • 16 schematically shows a structure of a voltage generating circuit according to a seventh embodiment.
  • In 16 are charge transfer stages XFP1 to XFPn cascading between the internal nodes ND12 and the final exit node FOD arranged. Each of the charge transfer stages XFP1 to XFPn is the same in construction as in 14 charge transfer stage shown XFP ,
  • Capacity elements CC1 to CCn-1 are the input nodes ODP1 to ODPn-1 of the respective charge transfer stages XFP2 to XFPn arranged accordingly. The capacity elements CC1 to CCn-1 are through the control signal input node S11 and S12 alternating with control signals ΦPZ and ΦCPZ provided. The charge transfer stages XFP1 to XFPn are through the control signal input node S13 and S52 alternating with control signals ΦCTZ and ΦCTFZ provided. Thus the charge transfer stages XFP1 . XFP3 , ... and XFPn-1 in odd-numbered stages through control signal input nodes S13 with the control signal ΦCTZ supplied to transfer the charges and charge transfer stages XFP2 , ... and XFPn in even-numbered stages are supplied with the control signal ΦCTFZ through control signal input nodes S52 and charge transfer is controlled.
  • Each of the charge transfer stages XFP1 to XFPn raises the received voltage by the supply voltage VCC on. Hence a tension (n + 1) · VCC on the final exit node FOD generated.
  • To control the operation of accumulating charges on the node ND12 are N-channel MOS transistors NQ11 and NQ12 arranged crosswise, and are capacity elements C11 and C12 that the charge pumping operation on nodes ND11 and ND12 according to control signals ΦPZ and ΦCPZ perform, arranged. The circuit section that performs the charge pumping operation on the node ND12 is the same in structure as that in the 3 and 14 shown, and therefore the voltage at the node changes ND12 between the tension VCC and the high tension 2 · VCC ,
  • 17 Fig. 10 is a timing chart showing an operation of the voltage generating circuit 16 shows in the stable state. With regard to the 14 and 17 the operation of the voltage generating circuit will now stop 16 described in the stable state.
  • 17 illustrates waveforms of the voltages on the input nodes and the internal nodes of the charge transfer stages XFPi-1 . XFPi and XFPi + 1 , The charge transfer stages XFPi-1 and XFPi + 1 are supplied with the control signal ΦCTF , and the charge transfer step XFPi is supplied with the control signal ΦCT , The input node NDIj the charge transfer circuit XFPj is with the internal output node ODPj-1 the charge transfer circuit XFPj-1 connected in the previous stage. 17 illustrates internal exit nodes ODIi-1 and ODIi that are the input node NDIi respectively. NDIi + 1 correspond. The potentials of the input nodes of the respective charge transfer stages will now be referenced to 14 described.
  • If the control signal ΦPZ to the level of the ground voltage GND falls, the potential at the input node drops NDIi-1 the charge transfer stage XFPi-1 from a voltage level i · VCC to a voltage level (i-1) · VCC , In the charge transfer stage XFPi + 1 the tension of its input node drops NDIi + 1 from the voltage level (i + 1) · VCC to the voltage level (i + 1) · VCC , In these transmission stages XFPi-1 and XFPi + 1 are the internal nodes NDBi-1 and NDBi + 1 set to the voltage levels corresponding to the voltage levels of the subsequent charge transfer stages XFPi respectively. XFPi + 2 match because of the MOS transistor PQb is in a pass state.
  • If the input node NDIi + 1 that of the charge transfer stage XFPi following charge transfer stage XFPi + 1 to the voltage level (i + 1) · VCC decreases, the voltage level of the output node decreases NDBi the charge transfer circuit XFPi of (i + 2) VCC on (i + 1) · VCC because the MOS transistor PQd is in the pass state.
  • If the control signal ΦCPZ of the level of the ground voltage GND to the level of the supply voltage VCC increases, the charge pumping lifts through the corresponding capacity element CCi in the charge transfer stage XFPi the voltage level of the input node NDIi of the tension i · VCC on the tension (i + 1) · VCC on. Because the MOS transistor PQb in the charge transfer stage XFPi-1 is in a forward state, such an increased tension of the node NDIi the voltage level of the node NDBi-1 on (i + 1) VCC on, and the corresponding MOS transistor PQa is held in the locked state.
  • The voltage level of the internal node also increases NDBi + 1 in the charge transfer stage XFPi + 1 on the tension (i + 3) · VCC on, and the corresponding P-channel MOS transistor PQa is held in the locked state.
  • If the control signal ΦCTZ from the supply voltage VCC to the ground voltage GND the internal node drops NDBi in the charge transfer stage XFPi the voltage level i · VCC , the MOS transistor PQa goes to the on state to the voltage (i + 1) · VCC at the internal node NDIi on the input node NDIi + 1 in the subsequent or downstream charge transfer stage XFPi + 1 transferred to. With this charge transfer, the backflow of charges into the charge transfer stages XFPi-1 and XFPi + 1 prevented because of the MOS transistors PQa are in a locked state (non-conductive state).
  • If the control signal ΦCPZ to the level of the supply voltage VCC increases, the voltage level of the internal node increases NDBi in the charge transfer stage XFPi of the tension i · VCC on the tension (i + 1) VCC and the gate potential of the corresponding P-channel MOS transistor PQa will be equal to or higher than its source potential, so the MOS transistor PQA is brought into the locked state.
  • If the control signal ΦPZ from the ground voltage GND on the supply voltage VCC increases, lead the capacity element CCi-1 and CCi + 1 in the charge transfer stages XFPi-1 and XFPi + 1 the charge pumping processes to the voltage level of the corresponding input node each around the supply voltage VCC to raise. The input node thus reaches NDIi-1 the charge transfer stage XFPi-1 the voltage level i · VCC , and the input node NDIi + 1 the charge transfer stage XFPi + 1 reaches the voltage level (i + 2) VCC ,
  • In such a state, the MOS transistor goes PQb in the charge transfer stage XFPi in the on state, since its gate connection potential is lower than its source connection potential, and the internal node NDBi rises to the level of voltage (i + 2) VCC which is equal to that of the input node NDIi + 1 the charge transfer stage XFPi + 1 and the MOS transistor PQa is kept locked to prevent charge backflow.
  • The control signal drops in this state ΦCTZF from the supply voltage VCC to the ground voltage GND , and in the charge transfer stages XFPi-1 and XFPi + 1 become the voltage levels of the internal nodes NDBi-1 and NDBi + 1 around the supply voltage VCC reduced, and the corresponding MOS transistors PQa are brought into the pass state. As a result, charges from the input node NDIi-1 to the exit node ODPi-1 ( NDIi ) and the charges from the input node NDIi + 1 to the output node in the charge transfer stage XFPi + 1 transfer.
  • Then, the above operations are repeated so that the charge transfer stages XFP1 to XFPn alternately perform the charge pumping process to raise the received voltages so that the supply voltage VCC , and finally the tension (n + 1) · VCC on the final exit node FOD can be generated.
  • In the high voltage generating circuit, in the transition period of the initial period of charge pumping operation as in the sixth embodiment, the threshold voltage of a MOS transistor is used to control the setting of the off state of the MOS transistor to prevent leakage current from occurring, and the voltage level of each The node is gradually raised to reach the final stable voltage level.
  • In this seventh embodiment, the high level voltage and the low level voltage of the control signals ΦPZ . ΦCPZ . ΦCTZ and ΦCTFZ each be different from each other.
  • According to the seventh embodiment, as described above, a plurality of charge transfer stages are cascaded, the capacitance elements are used to perform the charge pumping operation on the input nodes of the respective charge transfer stages, and the charge transfer operations are performed in an alternate manner. Accordingly, the internal voltage can be generated at a desired level with reduced power consumption.
  • The control signal ΦPZ . ΦCPZ . ΦCTZ and ΦCTFZ can by inverting all the output signals of the control signal generating circuit 12 be generated.
  • Eighth embodiment
  • 18th shows a structure of a voltage generating circuit according to an eighth embodiment. The voltage generating circuit out 18th differs in structure from the voltage generating circuit 1 in the following points. The cross-coupled P-channel MOS transistors PQ1 and PQ2 in 1 are through N-channel MOS transistors NQQ1 and NQQ2 replaced, which form a charge transfer stage. The N-channel MOS transistor NQQ1 is between a precharge power supply NDD2 and the internal node ND2 switched, and has one with an internal node (first internal node) NDD1 connected gate connection (control electrode). The precharge voltage supply node NDD2 is with a ground knot GG connected to the ground voltage GND of the reference voltage.
  • The N-channel MOS transistor NQQ2 is between the internal nodes NDD1 and NDD2 switched and has a gate connection with which the control signal ΦP receiving control signal input node S1 connected is. The internal node NDD1 is about the capacity element CQ1 with the input node S32 connected to the control signal ΦCTF receives.
  • The structure of the charge transfer stage between the input node ND2 and the output node OD1 is the same as that in 1 shown. Corresponding elements are provided with the same reference symbols and the description thereof is not repeated.
  • The control signals ΦCTF . ΦP . ΦCP and ΦCT all switch between the ground voltage GND and the supply voltage VCC , and are from the control circuit 12 generated.
  • The MOS transistors NQQ1 and NQQ2 correspond to the claimed first and second transistor, and the capacitance element CQ1 corresponds to the claimed first capacity element. The control signal ΦCTF corresponds to the first control signal, and the control signal ΦP corresponds to the second control signal in the claims. The MOS transistors NQ1 and NQ2 correspond to the claimed third and fourth transistor, and the capacitance elements C2 and C3 correspond to the claimed second or third capacity element. The control signal ΦCP and ΦCT correspond to the claimed third and fourth control signals. All MOS transistors are each of the enhancement type.
  • 19 Fig. 10 is a signal waveform diagram that shows an operation of the voltage generating circuit 18th illustrated. Referring now to FIG. 19, the operation of the voltage generating circuit is stopped 18th described. 19 illustrates the signal waveforms in the case where the negative voltage -VCC at the exit node OD1 is produced.
  • By the time t0 are the control signals ΦP . ΦCT and ΦCTF at the L level, and the control signal ΦCP is at the H level. The internal node is in this state ND2 at the level of the ground voltage GND through the charge pump operation of the capacitance element C2 which is the control signal ΦCP receives. The internal node ND3 reaches the level of negative voltage -VCC through the charge pump operation of the capacitance element C3 , Stable when the internal node ND2 at the level of the ground voltage GND is, is the MOS transistor NQ2 brought into the pass state (output node OD1 is at the level of the negative voltage -VCC ), and the internal node ND3 is at the same voltage level as that of the output node OD1 set.
  • The internal node NDD1 is due to the charge pump operation of the capacitance element CQ1 at the level of the ground voltage GND , The control signal ΦP is at the L level of the ground voltage, and the MOS transistor NQQ2 is in the locked state.
  • By the time t1 the control signal increases ΦP to the H level of the supply voltage VCC on. In response to this rise in the control signal ΦP goes the MOS transistor NQQ2 in the pass state so that the internal node NDD1 and ND2 be electrically connected to each other to achieve the same voltage level (set to the ground voltage level).
  • By the time t2 , the control signal falls ΦCP to the L level of the ground voltage GND while the control signal ΦP is at the H level. In response to the drop in the control signal ΦCP reduces charge pumping through the capacitance element C2 the voltage level of the node ND2 , Because the MOS transistor NQQ2 is in a forward state, the charge pumping through the capacitance element lowers C2 the voltage levels of the nodes NDD1 and ND2 from ground voltage to negative voltage -VCC from. By the capacity element C2 is designed such that it has a capacitance value substantially greater than that of the capacitance element CQ1 has both internal nodes NDD1 and ND2 from the level of the ground voltage GND to the level of the negative voltage -VCC be lowered.
  • If the voltage level of the internal node ND2 to the level of the negative voltage -VCC decreases, the MOS transistor goes NQ2 in the output charge transfer stage in the lock state, so that the internal node ND3 from the output node OD1 is separated, and enters an electric floating state.
  • In this state at the time t3 the control signal ΦCT from the level of the ground voltage GND to the level of the supply voltage VCC raised. In response to the rise in the control signal ΦCT lifts charge pumping through the capacity element C3 the voltage level of the node ND3 from the negative tension -VCC to the level of the ground voltage GND on, and the MOS transistor NQ1 is put in the pass state to the internal node ND2 electrically with the output node OD1 connect to. If the output node OD1 is at a higher voltage level than the internal node ND2 , positive charges move from the output node OD1 to the internal node ND2 so that the voltage level of the output node DD1 sinks.
  • The internal node ND3 is at the level of the ground voltage GND , In this stationary State is the gate-source voltage of the MOS transistor NQ1 equal to the supply voltage VCC , and the charges can go between the internal nodes ND2 and the output node OD1 without being affected by the threshold voltage of the MOS transistor NQ1 be transmitted.
  • If the MOS transistor NQ1 is in the forward state to the charges between the internal nodes ND2 and the output node OD1 to move, reach gate and source of the MOS transistor NQ2 the same potential level. The MOS transistor is in this state NQ2 of the enrichment type and remains in the blocking state due to its threshold voltage.
  • By the time t4 the control signal falls ΦCT from the H level to the L level. In response, charge pumping through the capacitance element lowers C3 the voltage level of the internal node ND3 back to the negative tension -VCC , and the MOS transistor NQ1 goes into the locked state.
  • If the charges are between the internal nodes ND2 and the output node OD1 move is the MOS transistor NQQ2 in a pass state to the internal nodes NDD1 and ND2 electrically connect to each other, and the MOS transistor NQQ2 negative charges from the internal node ND2 to the internal node NDD1 deliver so that the loads can be transferred efficiently. In the above process, the MOS transistor remains NQQ1 in the locked state because of the internal nodes NDD1 and ND2 are at substantially equal potentials, and the gate-source voltage thereof is less than the threshold voltage.
  • By the time t5 becomes the control signal ΦCP from the L level of the ground voltage GND to the H level of the supply voltage VCC raised. In response to the rise in the control signal ΦCP lifts charge pumping through the capacity element C2 the potential of the internal node ND2 from the level of negative voltage -VCC on. In this state, the control signal ΦP is at the level of the supply voltage VCC and the MOS transistor NQQ2 is in an on state, so the voltage level of the two internal nodes NDD1 and ND2 to the ground voltage GND increase.
  • By the time t6 the control signal falls ΦP to the L level and the MOS transistor NQQ2 is in the locked state, and the internal node ND2 and NDD1 are electrically separated from each other.
  • By the time t7 the control signal increases ΦCTF to the H level. As a result, the charge pump operation of the capacity element lifts CQ1 the voltage level of the internal node NDD1 from the ground voltage GND on the supply voltage VCC (the MOS transistor NQQ2 is in the locked state). According to this increase in the potential level of the internal node NDD1 becomes the MOS transistor NQQ1 placed in the pass state to the internal node ND2 to the level of the ground voltage GND to preload.
  • By the time t8 the control signal falls ΦCTF to the L level. In response, charge pumping through the capacitance element lowers CC1 the potential of the internal node NDD1 back to the ground voltage level GND , and the MOS transistor NQQ1 is brought into the lock state (the node ND2 is at the ground voltage level).
  • Then the in between t0 by the time t8 operations performed repeatedly, so that at the output node OD1 the negative tension -VCC is generated, which is the potential amplitude of the internal node ND2 equivalent. A stabilizing element of capacity 4 the negative voltage drops -VCC at the exit node OD1 stable.
  • In the transition period, before the voltage level of the output node OD1 becomes stable, the knot reaches NDD1 the level of the supply voltage VCC according to the H level of the control signal ΦCTF in the period between times t7 and t8 to the MOS transistor NQ1 to bring it into the pass state so that the internal node ND2 is connected to the ground node to be set to the ground voltage level. After the MOS transistor NQQ1 has been brought into the blocking state, the control signal ΦCP lowered from the H level to the L level. According to such a control method, the internal node reaches ND2 the level of negative voltage -VCC and positive charges flow from the output node OD1 in the internal nodes ND2 (Negative charges flow from the internal node ND2 in the output node OD1 ) when the MOS transistor NQ1 is in the on state, and the voltage level of the output node OD1 gradually decreases.
    Even if the charges are in the transition state, the internal node is ND2 at the level of the negative voltage -VCC and the MOS transistor NQ2 has a gate connection potential which does not exceed the source and drain connection potential and remains in the blocking state. In this state, the MOS transistor NQ1 be kept in the on state according to the control signal OCT , In the transition period, therefore, negative charges can reliably from the output node OD1 are provided for gradually reducing its potential level.
  • When building the voltage generating circuit out 18th only N-channel MOS transistors are used. Therefore, it is not necessary to provide an area for isolating a P-channel MOS transistor from an N-channel MOS transistor, and the circuit area can be reduced. Furthermore, steps for forming the P-channel MOS transistor are not necessary, so that the number of manufacturing steps and the manufacturing cost can be reduced.
  • The gate connection potentials of the MOS transistors NQ1 . NQ2 . NQQ1 and NQQ2 are individually controlled by the control signals ΦCT . ΦCP . ΦCTF respectively. ΦP , Therefore, by appropriately adjusting the timing of these control signals, the charges can be transferred after disconnecting a path of the flow of leakage charges, and the flow of the leakage charges can be prevented, so that the negative charges efficiently at the output node OD1 can be transferred to the negative voltage -VCC to create.
  • Similar to the structure of the first embodiment 1 can the in 18th shown the structure of the output node OD1 Adjust the generated voltage level to any desired level by appropriately adjusting the amplitudes of the control signals ΦCT . ΦCP . ΦP and ΦCTF as well as the level of voltage applied to a ground node OGG is created as with the MOS transistor NQQ1 connected precharge voltage supply node is used.
  • According to the eighth embodiment, as described above, the charge transfer stages are cascaded, these charge transfer stages alternately carry out the charge transfer, and the precharging and the charge accumulation are alternately performed on the internal nodes connected to these charge transfer stages. Thus, the charges can be used efficiently to generate the negative voltage at an intended voltage level. Furthermore, the circuits are formed on the MOS transistors of the same conductivity type, and therefore no area is required to isolate the PMOS and NMOS transistors from each other. In addition, the number of manufacturing steps can be reduced, and therefore the manufacturing cost can be reduced.
  • Ninth embodiment
  • 20th shows a structure of a voltage generation circuit according to a ninth embodiment. In the 20th The voltage generating circuit shown differs in structure from the voltage generating circuit 1 in the following points. In the 3 shown cross-coupled N-channel MOS transistors NQ11 and NQ12 are through P-channel MOS transistors PQQ1 and PQQ2 replaced. The P-channel MOS transistor PQQ1 is between a precharge voltage supply node NDD12 and the internal node ND12 switched and has one with an internal node NDD13 connected gate connection.
  • The precharge voltage supply node NDD12 is with the power supply node PW which is the supply voltage VCC delivers, connects and delivers charges for precharging the internal node ND12 at the level of the supply voltage VCC , The internal node NDD13 is about a capacity element CQ13 at the input node S52 coupled to a control signal ΦCTFZ receives. The high voltage 2VCC (= 2 · VCC) is at the output node OD11 generated.
  • The P-channel MOS transistor PQQ2 is between the internal nodes ND12 and NDD13 switched and has a gate connection with which the control signal ΦPZ receiving input node S11 connected is.
  • A charge transfer stage, the charges between the internal nodes ND12 and the output node OD11 has the same structure as that in 3 shown. Corresponding elements are identified by the same reference symbols and the descriptions thereof are not repeated.
  • The internal node ND12 is with the input node S12 connected to the control signal ΦCPZ about the capacity element C12 receives.
  • These control signals ΦPZ . ΦCPZ . ΦCTZ and ΦCTFZ are generated by inverting the control signal ΦP . ΦCP . ΦCT and ΦCTF generated by the control signal generation circuits.
  • In the in 20th shown structure correspond to the assignment of the claimed elements, the MOS transistors PQQ1 and PQQ2 the first and the second transistor, and the MOS transistors PQ11 and PQ12 correspond to the third and the fourth transistor. The control signals ΦCTFZ . ΦPZ . ΦCPZ and ΦCTZ correspond to the first, second, third and fourth control signals. The capacity elements CQ13 . C12 and C13 corresponding to the first, the second and the third capacitance element.
  • 21 Fig. 10 is a signal waveform diagram showing an operation of the voltage generating circuit 20th illustrated. In the 20th The voltage generating circuit shown generates a voltage of 2 · VCC at the entry node OD11 based on the tension VCC connected to the power supply node PW is created. Accordingly, the operating waveforms of the voltage generating circuit can be made from 20th can be achieved by inverting voltage polarities of the signals and nodes of the in 18th voltage generating circuit shown, and by measuring the voltages at the respective nodes with respect to the supply voltage VCC , Therefore, the operation of the voltage generating circuit becomes off 20th now briefly with reference to 21 described.
  • By the time t0 are the control signals ΦPZ . ΦCTZ and ΦCTFZ at the H level of the supply voltage VCC , and the control signal ΦCPZ is at the L level of the ground voltage GND , The node is in this state ND12 at the level of the supply voltage VCC and the knot ND13 is at the level of the supply voltage VCC , The MOS transistor PQQ2 is in a blocking state, and the MOS transistor PQQ1 is also in a locked state. The node is similar to the second embodiment ND13 through the charge pump operation of the capacitance element C13 at the level of high voltage 2VCC , and the MOS transistor PQ11 is in the blocked state (non-conductive state). The MOS transistor PQ12 is in an on state (conductive state), and the internal node ND13 is electrical at the output node OD11 coupled.
  • By the time t1 the control signal falls ΦPZ from the H level of the supply voltage VCC to the L level of the ground voltage GND , and the MOS transistor PQQ2 goes to the pass state to the internal node NDD13 at the internal nodes ND12 to couple electrically. The MOS transistor PQQ1 remains in the blocking state since its gate, source and drain connection potentials are equal to one another.
  • By the time t2 the control signal increases ΦCPZ from the L level to the H level. In response to the rise in the control signal ΦCPZ lifts charge pumping through the capacity element C12 the voltage level of the node ND12 by an amplitude VCC of the control signal ΦCPZ from the supply voltage VCC to the high tension 2VCC , In this process, the MOS transistor PQQ2 in the on state, so the voltage level of the node NDD13 to the high tension 2VCC increases. With the capacity element C12 whose capacity value is significantly larger than that of the capacity element CQ13 , the knot NDD13 , similar to the loading operation of the node NDD12 , be charged to the level of high voltage 2VCC. According to the increase in the node's potential level NDD13 goes the MOS transistor PQQ1 in the locked state.
  • According to the increase in the potential level of the internal node ND12 goes the MOS transistor PQ12 in the locked state (output node OD11 is at the potential level of the voltage 2VCC ), and the internal node ND13 is separate from the output node OD11 ,
  • By the time t3 the control signal falls ΦCTZ from the H level to the L level, and charge pumping through the capacitance element C13 lowers the potential level of the internal node ND13 of the high tension 2VCC on the supply voltage VCC from. If the potential of the internal node ND13 to the level of the supply voltage VCC is lowered, the MOS transistor goes PQ11 in the conduction state to charge between the internal nodes ND12 and the output node OD11 transferred to. Because the absolute value of the threshold voltage of the MOS transistor PQ11 is much lower than the supply voltage VCC , the charges between the internal nodes ND12 and the output node OD11 without influencing the threshold voltage of the MOS transistor PQ11 be transmitted. If the voltage level of the output node OD11 is less than the voltage 2 · VCC , positive charges from the internal node ND12 at the exit node OD11 supplied, and the voltage level of the output node OD11 rises.
  • By the time t4 the control signal increases ΦCTZ from the L level to the H level, and charge pumping through the capacitance element C13 raises the potential level of the internal node ND13 back to the high tension 2VCC on. The MOS transistor goes accordingly PQ11 to the locked state and the charge transfer process is completed. In this state is the potential level of the internal node ND12 less than the potential level of the internal node ND13 , and the positive charges move from the internal node ND13 to the exit node OD11 via the MOS transistor PQ12 , even if the MOS transistor PQ12 is in a pass state. In response, the voltage level of the output node increases OD11 so that the discharged charges are used effectively and no leakage current flows. This is the same as in the second embodiment.
  • By the time t5 the control signal falls ΦCPZ from H level to L level, and in response, charge pumping through the capacitance element lowers C12 the voltage level of the internal node ND12 of the high tension 2VCC on the supply voltage VCC , If the internal node ND12 the level of the supply voltage VCC reached the MOS transistor PQ12 in the on state to the potential of the node ND13 and the output node OD11 to each other equalize, and accordingly the MOS transistor PQ11 brought into the lock state, and the internal node ND13 is from the output node OD11 disconnected (in the case where the voltage level of the output node OD11 is higher than the supply voltage VCC ).
  • Because the MOS transistor PQQ2 is in the on state, the voltage level of the internal node drops NDD13 from the positive high voltage 2VCC to the supply voltage VCC according to the potential change on the internal node ND12 , In this state, the gate and source of the MOS transistor are PQQ1 of the enhancement type set to the same potential, and the MOS transistor PQQ1 remains locked, so no charges from the internal node ND12 to the power supply node PW flow.
  • By the time t6 the control signal increases ΦPZ from the L level to the H level. In response are the gate and source of the MOS transistor PQQ2 set to the same potential level, and the MOS transistor PQQ2 goes into the lock state to the internal node NDD13 from the internal node ND12 electrically disconnect.
  • By the time t7 the control signal drops ΦCTFZ from the L level to the H level. In response are the gate and source of the MOS transistor PQQ2 set to the same potential level, and the MOS transistor PQQ2 goes into the lock state to the internal node NDD13 from the internal node ND12 electrically disconnect.
  • By the time t7 the control signal drops ΦCTFZ from the H level to the L level. In response, charge pumping through the capacitance element lowers CQ13 the voltage level of the internal node NDD13 from the supply voltage VCC to the ground voltage GND , and the MOS transistor PQQ1 goes to the pass state to the internal node ND12 with the power supply node PW to connect, and the internal node ND12 is at the level of the supply voltage VCC preloaded.
  • By the time t8 the control signal increases ΦCTFZ from the L level back to the H level, and the charge pumping operation of the capacitance element CQ13 changes the voltage level of the internal node NDD13 back to the supply voltage VCC , In response, the MOS transistor PQQ1 brought into the locked state, and the precharge of the internal node ND12 will be completed.
  • Then the operations between the time t0 and time t8 repeated so the high tension 2VCC at the exit node OD11 can be generated.
  • In the transition period, before the voltage at the output node OD11 the high tension 2VCC reached, decreases in a period between time t7 and time t8 the control signal ΦCTFZ to the L level of the ground voltage GND , and in response the MOS transistor PQQ1 placed in the pass state to the internal node ND12 to the level of the supply voltage VCC to preload. If the voltage level of the output node OD11 lower than the supply voltage VCC is the MOS transistor PQ12 reliably held in the locked state. If the control signal ΦCPZ to the level of the supply voltage VCC the internal node rises ND12 the level of high voltage 2VCC , In response, the MOS transistor goes PQQ1 in the lock state, and the flow of current from the internal node ND12 to the power supply node PW is suppressed. In addition, the gate terminal potential of the MOS transistor PQ12 higher than its source and drain potential, and the MOS transistor PQ12 is reliably brought into the locked state.
  • If the control signal ΦCTZ is at the L level, the internal node drops ND13 in a transition period at or below the level of the supply voltage VCC , and the gate terminal potential of the MOS transistor PQ11 is less than its source connection potential, and the MOS transistor PQ11 is brought into the pass state. Therefore, the positive charges from the internal node ND12 at the exit node OD11 are supplied, and the voltage level of the output node OD11 rises.
  • In this transition state, the voltage level of the node changes ND13 between the supply voltage VCC and the high tension 2VCC , Before the voltage at the output node OD11 on or below the supply voltage VCC the MOS transistor remains sinking PQQ12 in the locked state. In this state, the voltage level of the internal node changes ND13 between the supply voltage VCC and the ground voltage GND , and the MOS transistor PQ11 is put in the pass state when the internal node ND13 according to the control signal ΦCPZ is set to the ground voltage level. As a result, positive charges on the output node OD11 supplied to raise its voltage level.
  • If the MOS transistor PQ12 begins to conduct according to the rise in the voltage level of the output node OD11 on or below the supply voltage VCC , the voltage level of the internal node increases ND13 similar to the Output node voltage level OD11 on, and the voltage level of the internal node ND13 increases according to the voltage level of the output node OD11 on. In this case, those from the output node OD11 to the internal node ND13 flowing charges used to raise the potential level of the internal node ND13 to set the MOS transistors PQ12 and PQ11 to the on / off state according to the control signals ΦCTZ and ΦCPZ , Therefore no leakage current flows.
  • Similar to the eighth embodiment, the in 20th The voltage generating circuit shown transfers the charges efficiently without causing any leakage current and can thereby cause a high voltage 2VCC on the exit node OD11 produce.
  • At the in 20th shown voltage generation circuit, only P-channel MOS transistors are used. Therefore, similarly to the eighth embodiment, it is not necessary to manufacture both the P and the N-channel MOS transistors, so that the area occupied by the circuit and the number of manufacturing steps can be reduced, and accordingly the manufacturing cost can be reduced .
  • In the ninth embodiment, the control signals have ΦPZ . ΦCPZ . ΦCTZ and ΦCTFZ the amplitudes of the supply voltage VCC and high tension 2VCC which is higher by this amplitude than the reference voltage, which is the supply voltage VCC is. However, the voltage applied to the voltage supply node (precharge voltage supply node) may be at a level different from the supply voltage VCC be, and the control signals ΦPZ . ΦCPZ . ΦCTZ and ΦCTFZ can have amplitudes different from the supply voltage VCC to have. In this case, the reference precharge voltage supply node (voltage supply node PW ) supplied voltage can be used as a reference voltage, and a high voltage that is related to the amplitude of the control signal ΦCPZ is higher, based on such a reference voltage at the output node OD11 be generated.
  • According to the ninth embodiment, as described above, the PMOS transistor is used to accumulate and transfer the charges by controlling the voltage at the gate terminal, and the positive high voltage at an intended level can be generated without causing leakage current.
  • Tenth embodiment
  • 22 shows a structure of a voltage generating circuit according to a tenth embodiment. In the in 22 The voltage generation circuit shown is the precharge voltage supply node NDD2 with the input node S1 connected to the control signal ΦP receives. The other structure of the in 22 The voltage generating circuit shown is the same as that in FIG 18th shown voltage generating circuit. Corresponding sections are identified by the same reference numerals and the description thereof will not be repeated.
  • The MOS transistor NQQ1 is intended for reliable preloading of the internal node ND2 to the level of the ground voltage GND according to the control signal ΦCTF , If the control signal ΦCTF the H level of the supply voltage VCC the control signal is reached ΦP , at the L level of the ground voltage GND ( 19 ). Therefore, if the MOS transistor NQQ1 is switched through, the internal node ND2 be charged to the ground voltage level according to the control signal ΦP.
  • If the control signal ΦP at the H level of the supply voltage VCC is the control signal ΦCTF at the L level of the ground voltage GND , The MOS transistor is in this state NQQ2 in a pass state to the internal nodes NDD1 and ND2 electrically connect with each other. The potentials of the gate and source connection of the MOS transistor are accordingly NQQ1 aligned and the MOS transistor NQQ1 remains in the locked state. Therefore, such a situation can be reliably prevented from a current from the control signal input node S1 at the internal nodes ND2 flows when the potential level of the internal node ND2 sinks.
  • The operating waveforms of the voltage generating circuit 22 are the same as those in 19 for the voltage generating circuit 18th , It is not necessary to have the ground voltage GND to generate the negative voltage -VCC to use, and the circuit structure and layout can be made simple. The other electrode of the stabilizing capacity C4 is only with the ground node GG connected, and therefore the stabilizing capacity C4 be placed in any position. Accordingly, the voltage generation circuit is not restricted by the connection layout of the power supply line and the ground line, and the restrictions on the circuit arrangement positions are alleviated, which gives the degree of freedom in the arrangement position of the voltage generation circuit in the semiconductor device including the voltage generating circuit.
  • Eleventh embodiment
  • 23 12 shows a structure of a voltage generating circuit according to an eleventh embodiment. In the 23 The voltage generating circuit shown differs in structure from the voltage generating circuit 20th in the following points. In particular, the one with the P-channel MOS transistor PQQ1 connected precharge voltage supply node NDD12 with the control signal input node S11 connected to the control signal ΦPZ receives. The other construction of the voltage generating circuit 23 is the same as that of the voltage generating circuit 20th , Corresponding sections are identified by the same reference numerals and the description thereof is not repeated.
  • The MOS transistor PQQ1 is intended for preloading the internal node ND12 to the level of the supply voltage VCC , The control signal ΦPZ is at the H level of the supply voltage VCC when the control signal ΦCTZF which is the MOS transistor PQQ1 in the on state, is at the L level. If the MOS transistor PQQ1 is in the on state, the control signal can ΦPZ the internal node ND12 to the level of the supply voltage VCC preload. Accordingly, the operating waveforms of the power supply circuit are turned off 23 provided by the operating waveforms that those in 21 illustrated, and the same operations as that of the voltage generating circuit 20th can be done.
  • If the control signal ΦPZ is at the L level, is the control signal ΦCTFZ at the H level, and the MOS transistor PQQ2 connects the internal nodes NDD13 and ND12 electric. Therefore, there is a gate and source connection (internal node ND12 ) of the MOS transistor PQQ1 the same potential and therefore the MOS transistor remains PQQ1 in the blocked state, so that the flow of a current from the internal node DN12 to the input nodes S11 can be reliably suppressed.
  • By using the in 23 The voltage generating circuit shown can therefore look similar to the voltage generating circuit 20th a high positive tension 2VCC be generated.
  • The voltage generating circuit out 23 used to generate the high voltage 2VCC not the supply voltage VCC , Therefore, the circuit structure can be made simple, and the connection layout can also be made simple. Because the voltage generating circuit is not the supply voltage VCC The voltage generating circuit can be used without being restricted by the connection layout of the supply voltage VCC may be arranged (when arranged as an internal circuit of a semiconductor integrated circuit). This voltage generating circuit can be arranged in a structure such as a system LSI as a macro of a circuit block.
  • According to the eleventh embodiment, as described above, the control signals are used to precharge the internal node, and a supply voltage is not required, so the circuit structure can be made simple.
  • Twelfth embodiment
  • 24 shows a structure of a voltage generation circuit according to a twelfth embodiment. In the 24 The voltage generating circuit shown differs in structure from the voltage generating circuit 10A in the following points. The negative charge generation stage is not formed from a cross-coupled P-channel MOS transistor PQ1 and PQ2 in 10A , but is formed from MOS transistors NQQ1 and NQQ2 as well as from in 18th shown capacity elements CQ1 and CQ2 ,
  • Between the internal nodes ND2 and the final exit node FOD is a plurality of charge transfer stages XFN1 to XFNn connected in series, similar to that in 10A shown construction. The one between the internal nodes ND2 and the final exit node FOD arranged structure is the same as in 10A shown. Corresponding sections are identified by the same reference numerals and the description thereof is not repeated. Each of the charge transfer stages XFN1 to XFNn has the same structure as that in 10B charge transfer stage shown XFN ,
  • At the in 24 The voltage generating circuit shown changes the voltage level of the internal node ND2 between the ground voltage GND and the negative tension -VCC , and the charge transfer step XFN1 delivers from the internal node ND2 negative charges on the internal output nodes OD1 , In the process of transferring negative charges from the internal node ND2 at the internal output node OD1 is the control signal ΦP at the H level, and the internal output node OD1 was on the negative tension -VCC preloaded (in stable operation) so that the internal output node OD1 according to the transmission control signal ΦCT reliably to the level of negative voltage -VCC is set. In the charge transfer process is the MOS transistor NQ2 in the locked state, and the internal node ND3 is in response to the control signal ΦCT set to the ground voltage level, and accordingly the MOS transistor NQ1 placed in the on state so that the negative charges between the nodes ND2 and OD1 can be transferred.
  • If the control signal ΦCP reaches the H level, the internal node reaches ND2 the ground voltage level, and the MOS transistor NQ2 is put in the pass state to the internal output node OD1 with the internal node ND3 to connect electrically so that the MOS transistor NQ1 is reliably brought into the open state.
  • If the control signal ΦP falls from the H level to the L level, the voltage level of the internal output node drops OD1 from the negative tension -VCC to the negative tension -2 · VCC , The MOS transistor is in this state NQ2 in the on state, and the potential of the source and drain of the MOS transistor NQ1 is matched, and the MOS transistor NQ1 remains locked. Therefore, the negative charges do not reflux.
  • Similar to that in 10A shown structure is in each of the charge transfer stages XFN2 to XFNn the voltage drop that is equal to the amplitude of VCC the control signal ΦCP and ΦP is caused. Therefore, the potential of the output node changes ODn-1 the charge transfer stage XFNn-1 between the negative tension - (n-1) · VCC and the negative tension -nVCC , The last charge transfer stage XFN1 delivers the negative voltage to the final output node FOD according to the control signal ΦCTF , Hence the negative tension -nVCC similar to that in 10A shown structure at the final output node FOD generated.
  • In the construction of the in 24 The voltage generating circuit shown is for the internal node ND2 the capacity element C2 provided, and the negative voltage n · VCC becomes at the final exit node FOD generated. By using this capacitance element C2 becomes the negative potential of the internal node ND2 between the ground voltage GND and the negative tension -VCC changed, and accordingly the charge transfer stage XFN1 reliably the negative voltage -VCC at the internal output node OD1 transferred when the internal MOS transistor ( NQ1 ) for the charge transfer in the on state is in response to the control signal ΦCT , If the internal node ND2 the level of the ground voltage GND the charge transfer transistor ( NQ1 ) in the charge transfer stage XFN1 be brought into the locked state. In the charge transfer stage XFN1 can therefore the charge transfer operation according to the control signal ΦCT can be controlled, and therefore the voltage drop around the amplitude VCC in each of the charge transfer stages XFN1 to XFNn can be effected without causing a leakage current flow.
  • The operating waveforms of the 24 The voltage generating circuit shown are represented by the signal waveforms shown in 11 are shown.
  • The charge transfer stages are accordingly XFN1 to XFNn in the in 24 shown voltage generation circuit all formed from N-channel MOS transistors, and the elementary negative charge generation stage, which the negative elementary charges on the internal node ND2 is generated from the N-channel MOS transistors NQQ1 and NQQ2 educated. In this voltage generating circuit, therefore, each stage is made up of the N-channel MOS transistors and the negative voltage -nVCC can be generated at a desired level with a small circuit area and a reduced power consumption.
  • modification
  • 25th Fig. 14 shows a structure of a voltage generation circuit according to a modification of the twelfth embodiment.
  • In the 25th The voltage generating circuit shown differs in structure from that in FIG 24 shown voltage generation circuit in the following points. The precharge voltage supply node NDD2 of the N-channel MOS transistor NQQ1 is connected to the input node S1 which is the control signal ΦP receives. The other construction of the voltage generating circuit 25th is the same as that of the voltage generating circuit 24 , Corresponding sections are identified by the same reference numerals and the description thereof is not repeated.
  • When building the in 25th The voltage generating circuit shown changes the voltage level of the internal node ND2 between the ground voltage GND (corresponds to the L level of the control signal ΦP ) and the negative voltage -VCC , Therefore, on the final exit node FOD the negative tension -nVCC generated.
  • The operating waveforms of the voltage generating circuit 25th are by the in 11 illustrated reproduced. At the in 25th The voltage generating circuit shown becomes the ground circuit GND is not used to generate the negative voltage, so that the circuit structure as in the tenth embodiment can be kept simple, and thus manufacturing costs can be reduced.
  • According to the twelfth embodiment, as described above, a plurality of charge transfer stages are cascaded so that the negative output voltage is generated on the final output node, and the negative voltage at a desired voltage level can be generated easily. Since each charge transfer stage is made up of the N-channel MOS transistors, the circuit structure can be made simple. The circuit layout area can also be reduced and the manufacturing costs can be kept low.
  • Thirteenth embodiment
  • 26 12 shows a structure of a voltage generating circuit according to a thirteenth embodiment. In the 26 The voltage generating circuit shown differs in structure from that in FIG 16 shown voltage generation circuit in the following points. For a circuit that has the positive charges on the internal nodes ND12 supplies, uses the in 26 shown voltage generating circuit P-channel MOS transistors PQQ1 and PQQ2 as well as capacity elements CQ13 and CQ12 like the one in 20th shown construction. The precharge voltage supply node NDD12 of the MOS transistor PQQ1 is with the power supply node PW connected and receives the supply voltage VCC , The circuitry for delivering the positive charges to the internal nodes ND12 is the same as that in 20th shown construction. Corresponding sections are identified by the same reference numerals and the description thereof is not repeated.
  • Similar to the structure of the in 6 The voltage generation circuit shown are the charge transfer stages XFP1 to XFPn consisting of n levels cascading between the internal nodes ND12 and the final exit node FOD arranged. In addition, the capacity elements CC1 to CCn-1 with internal output nodes ODP1 to ODPn-1 respective charge transfer stages XFP1 to XFPn-1 connected. The connection and operation of these charge transfer stages XFP1 to XFPn and capacity elements CC1 to CCn-1 are the same as those of the voltage generating circuit 18th , and corresponding sections are identified by the same reference numerals. The charge transfer stages lead accordingly XFP1 to XFPn alternately by precharging the internal nodes and the charge transfer operation, and the capacity elements CC1 to CCn alternately carry out the precharging and lifting of the corresponding internal output nodes ODP1 to ODPn-1 by.
  • The potential of the internal node ND12 changes between the supply voltage VCC and the high tension 2VCC , similar to the structure of the in 20th shown voltage generating circuit. After the charge transfer stage XFP1 the high tension 2VCC at the internal output node ODP1 ( OD11 ) has transferred, raises the capacity element CC1 the voltage level of the internal output node ODP1 further on the tension VCC according to the control signal ΦPZ on. Therefore, charge transfer stages create XFP1 to XFPn-1 at their respective output nodes the voltage VCC voltages raised relative to the output node voltages of the previous stages. The voltage level of the output node ODPn-1 the charge transfer stage XFP (n-1) alternates between the tension n · VCC and (n + 1) · VCC , Therefore, the charge transfer stage creates XFPn in the last stage the high tension (n + 1) · VCC on the final exit node FOD ,
  • The operating waveforms of the 26 The voltage generation circuit shown by those of FIG 19 shown voltage generating circuit, and the high voltage (n + 1) · VCC can also be generated by the supply voltage VCC.
  • By arranging the capacity element C12 for the internal node ND12 , and by changing the potential of the internal node ND12 between the supply voltage VCC and the high tension 2VCC becomes the following operation in the charge transfer stage XFP1 performed reliably. The MOS transistor for transmission (MOS transistor PQ11 ) remains in a locked state to prevent the backflow of positive charges when the control signal ΦCPZ reached the H level. In addition, the positive charges from the node ND12 to the internal output node ODP1 are transferred through the charge transfer stage XFP1 according to the control signal ΦCTZ ,
  • The charge transfer stages XFP1 to XFPn are each formed from P-channel MOS transistors, and the stage for supplying positive charges to the internal nodes ND12 is also made of P-channel MOS transistors PQQ1 and PQQ2 or formed from MOS transistors of the same conductivity type. Therefore, the positive high voltage (n + 1) · VCC can be generated at any voltage level with the circuit of a simplified structure.
  • modification
  • 27 FIG. 13 shows a structure of a voltage generation circuit according to a modification of the thirteenth embodiment.
  • In the 27 The voltage generating circuit shown differs in structure from that in FIG 26 shown voltage generation circuit in the following points. The precharge voltage supply node NDD12 is with the input node S11 connected to the control signal ΦPZ receives. The other construction of the voltage generating circuit 27 is the same as the one in 26 shown voltage generating circuit. Corresponding sections are provided with the same reference numerals and the description thereof is not repeated.
  • According to the structure of the 27 The voltage generating circuit shown is on the internal node ND12 a voltage change between the voltages VCC and 2 · VCC generated. Similar to that in 26 shown voltage generating circuit, the high positive voltage at the level (n + 1) · VCC from the final exit node FOD generated similar to the voltage generating circuit 26 ,
  • In the 27 The voltage generation circuit shown does not use the supply voltage VCC to generate the high voltage (n + 1) · VCC , Therefore, the circuit structure can be kept simple.
  • The operating waveforms of the 27 Voltage generation circuit shown by the in 19 shown, similar to that shown in 26 shown voltage generating circuit.
  • According to the thirteenth embodiment, as described above, a plurality of charge transfer stages are cascaded between the internal nodes and the final output nodes, and these charge transfer stages alternately precharge the output node and charge transfer. In addition, all the transistor elements are formed from the P-channel MOS transistors, and the charges can be efficiently transferred to generate a positive high voltage. Furthermore, the circuit area and the manufacturing cost can be reduced.
  • The voltage generating circuit according to the invention can be applied to a general LSI (high integrated circuit) as an integrated circuit that generates an internal voltage. Furthermore, the present invention can be generally applied to a semiconductor device that requires a voltage at a level different from the supply voltage and / or the ground voltage. Furthermore, the voltage generating circuit according to the invention can be used to drive liquid crystal elements in a liquid crystal display device which requires positive and negative voltages. By using the voltage generating circuit according to the invention it is possible to reduce the cost of parts and / or an end product and also to reduce the power consumption.
  • According to the invention, as described above, the gate terminal potential of each transistor is controlled by the charge pumping operation of the capacitance element so that the charges for generating an internal voltage are generated, and the on / off state of the transistors is individually and accurately controlled to the charges for the Generating internal voltage. Thus, the flow of leakage current can be suppressed, and the charges can be efficiently generated to generate an internal voltage at a desired level with a reduced power consumption.

Claims (6)

  1. Voltage generation circuit comprising: a first transistor (NQQ1; PQQ1) connected between a precharge voltage supply node (NDD2; NDD12) providing a precharge voltage and a first internal node (ND2; ND12), and the one with a second internal node (NDD1; NDD13) has connected control electrode; a first capacitance element (CQ1; CQ13) connected between a first input node (S32; S52) receiving a first control signal for precharging and the second internal node; a second transistor (NQQ2; PQQ2) connected between the first and second internal nodes and having a control electrode which receives a second control signal (ΦP; ΦPZ) controlling the accumulation of charges; a third transistor (NQ1; PQ11) connected between the first internal node and an output node (OD1; OD11) and having a control electrode connected to a third internal node (ND3; ND13); a fourth transistor (NQ2; PQ12) connected between the output node and the third internal node and having a control electrode connected to the first internal node; a second capacitance element (C2; C12) connected between a third input node (S2; S12), which receives a third control signal controlling a second charge precharge and is connected to the first internal node; a third capacitance element (C3; C13) connected between a fourth input node (S3; S13) receiving a fourth control signal controlling charge transfer and the third internal node, the precharge voltage supply node (NDD2; NDD12) having the second control signal ( ΦP; ΦPZ) is supplied.
  2. Voltage generating circuit after Claim 1 further comprising a circuit for generating the first through fourth control signals, the third control signal (ΦCP; ΦCPZ) reaching and maintaining a second logic level when the second control signal (ΦP; ΦPZ) is at a first logic level , and the fourth control signal (ΦCT; ΦCTZ) reaches and maintains the first logic level for a predetermined period of time when the third control signal is at the second logic level, and precharging the first internal node is performed when the first control signal is the first logic level is reached while the second control signal is at the second logic level.
  3. Voltage generating circuit according to one of the Claims 1 to 2 , further with: at least one voltage driver stage (XFN2 to XFNn, CK1 to CKn-1; XFP2 to XFPn; CC1 to CCn-1), which is electrically connected in series between the output node (OD1; OD11) and an end output node (FOD) and which generates a final voltage at the final output node, which contains a voltage driver stage: a fifth transistor (NQa; PQa) which is connected between an input node (NDI; PDI) of the voltage driver stage and an output node (NDO; PDO) of the voltage driver stage and the one with a fourth internal node (NDA; NDB) connected control electrode; a fourth capacitance element (CK1 to CKn-1; CC1 to CCn-1) connected to the input node of the voltage driver stage; a fifth capacitance (Ca; Cd) connected to the fourth internal node; and a sixth transistor (NQ12; PQb) connected between the fourth internal node and the output node of the voltage driver stage and having a control electrode connected to the input node of the voltage driver stage; and wherein the at least one voltage driver stage includes a plurality of such electrically connected voltage driver stages, the second and third control signals are alternately applied to the four capacitance elements in a connection order of the voltage driver stages, and the first and fourth control signals are applied to the fifth capacitance elements in the connection sequence are created alternately.
  4. Voltage generating circuit after Claim 3 further comprising a circuit for generating the first through fourth control signals, the first control signal reaching a first logic level and maintaining it for a predetermined period of time when a predetermined time has elapsed since the second control signal from the first logic level to the second logic levels Level has changed, and the second control signal changes from the second logic level to the first logic level after the first control signal changes from the first logic level to the second logic level; the third control signal reaches and maintains the second logic level for a predetermined period of time since the second control signal has changed to the first logic level, and the second control signal has reached the second logic level after the third control signal has changed to the first logic level; and the fourth control signal reaches and maintains the first logic level for a predetermined time after the third control signal changes to the second logic level, and the third control signal changes to the first logic level after the fourth control signal changes to the second logic level .
  5. Voltage generating circuit after Claim 3 or 4 , wherein the final output node applies a final voltage to an internal circuit, and the voltage generating circuit further comprises a capacitance element (C4; C14) connected to the final output node.
  6. Voltage generating circuit after Claim 1 , wherein the output node generates an internal voltage to be applied to an internal circuit, and the voltage generating circuit further comprises a capacitance element (C4; C14) connected to the output node.
DE102004024612.2A 2003-05-19 2004-05-18 Voltage generating circuit Active DE102004024612B4 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2003140079 2003-05-19
JP2003/140079 2003-05-19
JP2003/419716 2003-12-17
JP2003419716A JP4393182B2 (en) 2003-05-19 2003-12-17 Voltage generation circuit

Publications (2)

Publication Number Publication Date
DE102004024612A1 DE102004024612A1 (en) 2004-12-23
DE102004024612B4 true DE102004024612B4 (en) 2020-03-05

Family

ID=33455503

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102004024612.2A Active DE102004024612B4 (en) 2003-05-19 2004-05-18 Voltage generating circuit

Country Status (6)

Country Link
US (2) US20040232974A1 (en)
JP (1) JP4393182B2 (en)
KR (1) KR100538021B1 (en)
CN (1) CN100414644C (en)
DE (1) DE102004024612B4 (en)
TW (1) TWI240276B (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100365935C (en) * 2002-10-24 2008-01-30 松下电器产业株式会社 Voltage generating circuit, voltage generating device and semiconductor device using the same, and driving method thereof
US7248096B2 (en) * 2004-11-22 2007-07-24 Stmicroelectronics S.R.L. Charge pump circuit with dynamic biasing of pass transistors
US7317347B2 (en) * 2004-11-22 2008-01-08 Stmicroelectronics S.R.L. Charge pump circuit with reuse of accumulated electrical charge
WO2007058088A1 (en) 2005-11-17 2007-05-24 Nec Corporation Semiconductor integrated circuit
US7443202B2 (en) * 2006-06-02 2008-10-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic apparatus having the same
KR101230313B1 (en) 2006-07-05 2013-02-06 재단법인서울대학교산학협력재단 LEVEL SHIFTER and DRIVING MATHOD thereof
JP4929999B2 (en) * 2006-11-17 2012-05-09 セイコーエプソン株式会社 Boost circuit, control method thereof, and voltage generation circuit.
US7446596B1 (en) * 2007-05-25 2008-11-04 Atmel Corporation Low voltage charge pump
JP4969322B2 (en) * 2007-06-01 2012-07-04 三菱電機株式会社 Voltage generating circuit and image display device including the same
US7808301B2 (en) * 2007-07-26 2010-10-05 Macronix International Co., Ltd. Multiple-stage charge pump circuit with charge recycle circuit
JP5142861B2 (en) * 2008-07-09 2013-02-13 パナソニック株式会社 Internal voltage generation circuit
US9396465B2 (en) * 2009-07-22 2016-07-19 Visa International Service Association Apparatus including data bearing medium for reducing fraud in payment transactions using a black list
JP2011150482A (en) * 2010-01-20 2011-08-04 Sanyo Electric Co Ltd Power supply circuit
KR101764125B1 (en) 2010-12-15 2017-08-02 삼성전자주식회사 Negative high voltage generator and non-volatile memory device including negative high voltage generator
KR101736453B1 (en) 2011-01-05 2017-05-16 삼성전자주식회사 Flash memory device and wordline voltage generating method thereof
US8897073B2 (en) * 2012-09-14 2014-11-25 Freescale Semiconductor, Inc. NVM with charge pump and method therefor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04372792A (en) * 1991-06-21 1992-12-25 Sharp Corp Charge pump circuit
DE19601369C1 (en) * 1996-01-16 1997-04-10 Siemens Ag Voltage multiplier or providing negative high voltage
US6130572A (en) * 1997-01-23 2000-10-10 Stmicroelectronics S.R.L. NMOS negative charge pump

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950008453B1 (en) * 1992-03-31 1995-07-31 김광호 Internal source voltage generating circuit
JP2755047B2 (en) * 1992-06-24 1998-05-20 日本電気株式会社 Boost potential generation circuit
JP3853513B2 (en) * 1998-04-09 2006-12-06 エルピーダメモリ株式会社 Dynamic RAM
JP3476363B2 (en) * 1998-06-05 2003-12-10 Necエレクトロニクス株式会社 Bandgap reference voltage generator
JP3554497B2 (en) * 1998-12-08 2004-08-18 シャープ株式会社 Charge pump circuit
US6208196B1 (en) * 1999-03-02 2001-03-27 Maxim Integrated Products, Inc. Current mode charge pumps
US6501325B1 (en) * 2001-01-18 2002-12-31 Cypress Semiconductor Corp. Low voltage supply higher efficiency cross-coupled high voltage charge pumps
US6661682B2 (en) * 2001-02-16 2003-12-09 Imec (Interuniversitair Microelectronica Centrum) High voltage generating charge pump circuit
TW564434B (en) * 2002-02-22 2003-12-01 Ememory Technology Inc Charge pump circuit without body effects

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04372792A (en) * 1991-06-21 1992-12-25 Sharp Corp Charge pump circuit
DE19601369C1 (en) * 1996-01-16 1997-04-10 Siemens Ag Voltage multiplier or providing negative high voltage
US6130572A (en) * 1997-01-23 2000-10-10 Stmicroelectronics S.R.L. NMOS negative charge pump

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MAKSIMOVIC,D.; DHAR,S.: "Switched-Capacitor DC-DC Converters For Low-Power On-Chip Applications", Power Electronics Specialists Conference, PESC 1999, 30th Annual IEEE Volume 1, 27.Juni - 1.Juli 1999, S.54-59 *
NAKAGOME,Y. [et al]: "An Experimental 1.5-V 64-Mb DRAM" in IEEE j. solid-state circuits, Vol.26, No.4, April 1991, S.465-472 *

Also Published As

Publication number Publication date
US20060028266A1 (en) 2006-02-09
DE102004024612A1 (en) 2004-12-23
KR20040100933A (en) 2004-12-02
US20040232974A1 (en) 2004-11-25
JP2005006489A (en) 2005-01-06
TWI240276B (en) 2005-09-21
CN100414644C (en) 2008-08-27
CN1551236A (en) 2004-12-01
TW200426834A (en) 2004-12-01
JP4393182B2 (en) 2010-01-06
US7365591B2 (en) 2008-04-29
KR100538021B1 (en) 2005-12-21

Similar Documents

Publication Publication Date Title
TWI517541B (en) Four-phase charge pump circuit
US7397710B2 (en) Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same
TW586267B (en) Semiconductor integrated circuit with leak current cut-off circuit
US7023260B2 (en) Charge pump circuit incorporating corresponding parallel charge pump stages and method therefor
US6278315B1 (en) High voltage generating circuit and method for generating a signal maintaining high voltage and current characteristics therewith
US7592832B2 (en) Adjustable transistor body bias circuitry
KR100543659B1 (en) Active driver for generating internal voltage
US7042276B2 (en) Charge pump with improved regulation
US6064251A (en) System and method for a low voltage charge pump with large output voltage range
US6661682B2 (en) High voltage generating charge pump circuit
JP3732914B2 (en) Semiconductor device
US5838047A (en) CMOS substrate biasing for threshold voltage control
US7312649B2 (en) Voltage booster power supply circuit
US7667484B2 (en) Semiconductor device reducing power consumption in standby mode
US6359501B2 (en) Charge-pumping circuits for a low-supply voltage
US6333874B2 (en) Semiconductor memory device having normal and standby modes, semiconductor integrated circuit and mobile electronic unit
CN100508072C (en) Shift register and method for driving the same
JP2755047B2 (en) Boost potential generation circuit
EP1338081B1 (en) Charge pump power supply
JP3851302B2 (en) Buffer circuit and active matrix display device using the same
JP2604526B2 (en) Semiconductor memory device
EP0129217B1 (en) A semiconductor circuit including a memory and a pulse drive circuit
TWI439051B (en) Level converting flip-flop and method of operating the same
US6525949B1 (en) Charge pump circuit
US6677805B2 (en) Charge pump stage with body effect minimization

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
R016 Response to examination communication
R084 Declaration of willingness to licence
R018 Grant decision by examination section/examining division