DE10136335A1 - Processor with several arithmetic units - Google Patents

Abstract

The invention relates to a processor comprising a first arithmetic-logic unit (2), a second arithmetic-logic unit (4) and a control device (6) for controlling both arithmetic-logic units (2, 4). The control device controls the arithmetic-logic units in such a manner that they operate, as desired, in a high-security operational mode, in which complementary data is processed, or in a parallel operational mode, in which independent data is processed, or in a security operational mode, in which the same the data is processed, or are located in a power saving mode, in which one of the arithmetic-logic units (2, 4) is switched off.

Description

The present invention relates to a processor with several arithmetic units and in particular on one Processor with multiple arithmetic units that can be selected in one Interact operating mode according to the dual rail logic can.

Microprocessors or controllers for chip card applications and other cryptographic applications have to be common special safety conditions are sufficient. One of the The main requirement is the security of the microprocessor against one unauthorized reading of secret information, especially about Side channel attacks. Side channel attacks are carried out, for example, by detecting the Power consumption of a processor or via a electromagnetic or electrostatic detection of signal flows, whereby conclusions can be drawn from the information thus obtained internal processes can be drawn in the processor. Next However, a chip card controller must perform high-security tasks also perform a variety of conventional operations at where a high performance is a big advantage and can give an important market advantage. As examples applications from the mobile radio sector should be mentioned here to whom the actual authentication is only a very minor one Makes up part of the program duration. Still, for this low percentage the full security of authentication required. The same applies to electronic wallets, even for the cash card, because even with these applications large parts of the program run are not safety-critical, however, the real authentication is one High-security task.

A highly secure execution of the processor core is e.g. B. in the so-called dual-rail logic with precharge possible. The Execution of a safety microcontroller in dual-rail logic with Precharge is an important measure against Side channel attacks, which are a major threat today. It caused however, compared to a conventional processor economically disadvantageous larger space requirements and can due to the need for multiple clock phases Reduced performance of the microprocessor. This has compared to Standard architectures lower computing power or a low data throughput as well as an increased Processor power requirements result.

The object of the present invention is a Processor with increased security to create the one higher computing power or a smaller power requirement having.

This object is achieved by a processor according to claim 1, 2, 3 or 11 solved.

A processor according to the present invention includes a first arithmetic unit, a second arithmetic unit and one Control device for controlling the two arithmetic units in such a way that these optionally process in a complementary data High security mode or in an independent data parallel processing mode. Instead of Parallel mode or in addition can be used as another mode a power saving mode in which one of the arithmetic units is switched off, or a safety mode in which both calculators process the same data in parallel, be provided.

According to a preferred embodiment of the present Invention, a processor further includes a switchable Complementing device with an output that with a Input of the second arithmetic unit is connected to receive Data and for optionally outputting the received data or the complement of the data received.

A processor according to the present invention can also comprise a third arithmetic unit and a fourth arithmetic unit, the third arithmetic unit and the fourth arithmetic unit by the control device can be controlled such that they optionally processing in a complementary data High security mode or in an independent data parallel processing mode. In one instead of the High security mode or in addition to that provided Power saving mode is the third and / or the fourth Calculator switched off.

The first arithmetic unit and the second arithmetic unit are preferably designed such that they in the High-security operating mode process the same commands synchronously can. The first arithmetic unit and the second arithmetic unit are preferably arranged spatially adjacent. The processor can for example, be a cryptographic processor.

Another processor in accordance with the present invention comprises a first arithmetic unit, a second arithmetic unit, one Data source, which with the first arithmetic unit and the second Arithmetic unit is connected in such a way that the first Calculator data and the second calculator the complement of Data are supplied, and an instruction source, which a Has pair of commands, one of the commands of the Command pair is provided for the first arithmetic unit and wherein the other instruction of the instruction pair for the second arithmetic unit is provided, and wherein the command source with the first Arithmetic unit and the second arithmetic unit is connected in such a way that the command provided for the first arithmetic unit is synchronous of the instruction pair the first arithmetic unit and that for the second arithmetic command of the pair of commands second arithmetic unit can be supplied.

The command intended for the first arithmetic unit and that for the command provided for the second arithmetic unit can be the same, when the processor is in a dual rail mode or one Security mode should work, they can be from each other be different if the processor is in a High performance mode should work, and one of the two commands can shut down the calculator for which it is intended if the processor is operating in a power saving mode should.

Another object of the present invention is therein a chip card with increased security and one improved computing power and / or a reduced To create power requirements.

This object is achieved by a chip card according to claim 13 solved.

A chip card according to the present invention comprises one of the processors described above.

• 1. Hochsicherheitsbetriebsart: Einer der beiden CPU-Teile bzw. eines der beiden Rechenwerke arbeitet wie ein herkömmlicher Standardprozessor. Der zweite Teil jedoch wird mit den komplementären Daten versorgt und bearbeitet diese zeitsynchron mit exakt den gleichen Befehlen und der gleichen Ansteuerung, wobei die Rechenwerke im Precharge-Betrieb arbeiten. Damit wirken die beiden Prozessorteile zusammen wie ein einziger Prozessor mit Dual-Rail-Logik, sie befinden sich in der Hochsicherheitsbetriebsart. Vorteilhaft sind die komplementär rechnenden Elemente räumlich nebeneinander angeordnet und vorzugsweise sind sie ferner verwoben angeordnet, wodurch eine solche Anordnung auch gegen elektromagnetische Abstrahlungsanalysen gesichert werden kann. Im Sinne dieser Anmeldung ist ein Prozessor mit komplementär rechnende Rechenwerke ein Prozessor mit einer von verarbeiteten Daten unabhängigen Stromaufnahme.
• 2. Hochleistungsbetriebsart: Für Programme oder Programmteile, bei denen eine starke Sicherung gegen Seitenkanalangriffe nicht erforderlich ist, ist die Hochleistungsbetriebsart vorgesehen. In dieser Betriebsart werden die CPU-Teile bzw. Rechenwerke mit parallel abzuarbeitenden bzw. unterschiedlichen Programmteilen versorgt. So entsteht eine Anordnung von zwei CPUs bzw. Prozessoren, wodurch sich der Datendurchsatz verdoppeln kann.
• 3. Leistungssparbetriebsart: In der Leistungssparbetriebsart wird eines oder mehrere Rechenwerke deaktiviert, so daß nur noch ein Rechenwerk oder ein Teil der Rechenwerke arbeitet. Durch die kleinere Anzahl von schaltenden Gattern ist die Leistungsaufnahme reduziert. Der Prozessor arbeitet in dieser Betriebsart weder im Bereich der höchsten Sicherheitsstufe noch im Bereich der höchsten Leistung.
• 4. Sicherheitsbetriebsart: Eine Sicherheitsbetriebsart ist eine Betriebsart, bei der zwei Rechenwerke die gleichen Daten verarbeiten und durch Vergleich der Ergebnisse dieser Verarbeitung die Betriebssicherheit erhöht wird, was beispielsweise einen Schutz gegen DFA (differential fault attack) bietet.

The present invention is based on the finding that dual rail logic can be implemented by arranging a plurality of processor submodules which can be operated in different operating modes. Such a microprocessor advantageously contains two or another even number of CPU sub-modules, which are constructed identically, at least in pairs. With two CPU parts, you can choose between four different operating states and switch over during operation:

• 1. High security mode: One of the two CPU parts or one of the two arithmetic units works like a conventional standard processor. The second part, however, is supplied with the complementary data and processes it synchronously with exactly the same commands and the same control, with the arithmetic units working in pre-charge mode. The two processor parts work together like a single processor with dual-rail logic, they are in the high-security mode. The complementary computing elements are advantageously arranged spatially next to one another and preferably they are also arranged interwoven, so that such an arrangement can also be secured against electromagnetic radiation analyzes. In the sense of this application, a processor with complementary computing units is a processor with a current consumption that is independent of processed data.
• 2. High-performance operating mode: The high-performance operating mode is intended for programs or program parts in which a strong protection against side-channel attacks is not required. In this operating mode, the CPU parts or arithmetic units are supplied with different program parts to be processed in parallel. This creates an arrangement of two CPUs or processors, which can double the data throughput.
• 3. Power saving mode: In the power saving mode, one or more arithmetic units is deactivated, so that only one arithmetic unit or part of the arithmetic units is working. The power consumption is reduced due to the smaller number of switching gates. In this operating mode, the processor works neither in the area of the highest security level nor in the area of the highest performance.
• 4. Safety operating mode: A safety operating mode is an operating mode in which two arithmetic units process the same data and the operational safety is increased by comparing the results of this processing, which, for example, offers protection against DFA (differential fault attack).

An advantage of the processor according to the invention is that that he has the high security of a dual rail logic for security-relevant programs or program parts and a high Computing power or a lower power requirement for one Processing of less security-relevant program parts offers, being dynamic between different operating modes can also be switched during operation.

If in the present application of two arithmetic units N.2 arithmetic units can be used, where n is a natural number.

A preferred embodiment of the present Invention is hereinafter referred to the accompanying Drawings explained in more detail. Show it:

Fig. 1 is a schematic representation of an embodiment of the present invention;

FIG. 2 shows a schematic illustration of a high-security operating mode of the exemplary embodiment from FIG. 1;

FIG. 3 shows a schematic illustration of a high-performance operating mode of the exemplary embodiment from FIG. 1; FIG.

Fig. 4 is a schematic illustration of a power saving mode of the embodiment of Fig. 1; and

FIG. 5 shows a schematic illustration of a safety operating mode of the exemplary embodiment from FIG. 1.

Fig. 1 is a schematic representation of the relevant for the present invention, part of a processor according to an embodiment of the present invention. The processor has a first arithmetic unit 2 , a second arithmetic unit 4 , a control device 6 and a complementing device 8 . In the case of two parallel data lines, the complementing device 8 can be formed by an inverter. The control device 6 is effectively connected to the first arithmetic unit 2 via a control line 12 and to the second arithmetic unit 4 via a control line 14 . The first arithmetic unit 2 has a command input 16 which is connected via a line 18 to a command source (not shown), for example a program memory in the form of a ROM (ROM = Read Only Memory), a RAM (RAM = Random Access Memory = Memory with random access) or a hard drive, and a data input 20 , which is connected via a data line 22 to a data source (not shown), for example a data memory or an interface. The second arithmetic unit 4 has a command input 24 , which is connected via a command line 26 to the command source (not shown), to which the first arithmetic unit is connected via the command line 18 , or to another command source, and a data input 28 , which is connected via a data line 30 is connected to an output 32 of the complementing device 8 . The complementing device 8 also has an input 34 , which is connected via a data line 36 to the data source to which the first arithmetic logic unit 2 is connected via the data line 22 , or to another data source. The control device 6 and the complementing device 8 are effectively connected via a control line 38 .

The first arithmetic unit 2 and the second arithmetic unit 4 , controlled by commands which are fed to it at the command input 16 or 24 , processes data which are fed to it at the data input 20 or 28 . The complementing device 8 is controllable or switchable, ie it outputs data 32 that it has received at the input 34 (complementing device switched off) or its complement (complementing device switched on). These two states of the complementing device 8 are controlled or switched by the control device 6 via the control line 38 . The control device 6 also controls the first arithmetic unit 2 and the second arithmetic unit 4 in order to set a plurality of different operating modes or operating modes, which are described in more detail below with reference to FIGS. 2 to 4.

FIG. 2 is a schematic illustration of a high-security operating mode of the exemplary embodiment from FIG. 1. In this operating mode, the first arithmetic logic unit 2 and the second arithmetic logic unit 4 receive the same commands for processing data at the command inputs 16 and 24, respectively. Furthermore, the first arithmetic unit 1 at data input 20 and the complementing device 8 at input 34 are supplied with the same data. The complementing device 8 is switched on, ie it outputs the complement of the data which it receives at the input 34 at the output 32 . The second arithmetic unit 4 thus receives at its data input 28 the complement of the data which the first arithmetic unit 2 receives at its data input 20 . In this high-security operating mode, the function of the processor according to the present exemplary embodiment thus corresponds to the dual-rail logic, that is to say the arithmetic units 2 and 4 , which are preferably of identical construction, process synchronously complementary data controlled by the same commands. In this high-security operating mode, a side channel attack by measuring the power consumption of the processor is very difficult or even impossible, since the power consumption of the first arithmetic unit and the second arithmetic unit is not dependent on the data due to the processing of complementary data. If the first arithmetic unit 2 and the second arithmetic unit 4 are arranged in spatial proximity to one another or interwoven with one another, a side channel attack is also made considerably more difficult by analyzing the electromagnetic radiation of the processor, since currents or voltages are always in close proximity to one another due to the processing of complementary data occur which correspond to a digital value and its complement.

Fig. 3 shows a high-performance mode of the first arithmetic unit 2 and the second calculating unit 4. In this operating mode, the first arithmetic unit 2 and the second arithmetic unit 4 are supplied with different data at their data inputs 20 and 28 and different commands at their command inputs 16 and 24 . The parallel or simultaneous processing of different or the same data with different or the same commands or programs or program parts doubles the computing power of the processor according to the present exemplary embodiment. The processor can thus process twice the number of data in the same time and with the same power consumption as in the high-security mode, controlled by the double number of instructions. At the same time, this operating mode does not offer the special protection against side-channel attacks that the high-security operating mode explained with reference to FIG. 2 offers. However, it offers the advantage of concealing the current profiles and electromagnetic radiation by processing various data in parallel.

Fig. 4 is a schematic diagram of a power saving mode. In this operating mode, one of the two arithmetic units, here the second arithmetic unit 4 , is switched off or it is not supplied with power. The other arithmetic unit, here the first arithmetic unit 2 , receives data and commands which it processes. In this operating mode, the power consumption and the computing power of the two arithmetic units are halved compared to the high-performance operating mode explained with reference to FIG. 3. Like the high-performance operating mode, the low-power operating mode does not offer the particular security against side-channel attacks that the high-security operating mode explained with reference to FIG. 2 offers.

FIG. 5 is a schematic illustration of a safety operating mode of the exemplary embodiment from FIG. 1. In this operating mode, the first arithmetic unit 2 and the second arithmetic unit 4 receive the same commands for processing data at the command inputs 16 and 24, respectively. Furthermore, the first arithmetic unit 1 at data input 20 and the complementing device 8 at input 34 are supplied with the same data. The complementing device 8 is switched off, ie it outputs the data at the output 32 which it receives at the input 34 . The second arithmetic unit 4 thus receives at its data input 28 the same data that the first arithmetic unit 2 receives at its data input 20 . In this safety operating mode, the first arithmetic unit 2 and the second arithmetic unit 4 process the same data synchronously, controlled by the same commands. The results output by both arithmetic units are fed to a comparison device, not shown in FIG. 1, which checks the output of the first arithmetic unit 2 and the output of the second arithmetic unit 4 for correspondence and, depending on this, outputs a signal which can be used, for example, for a repetition to control or trigger the processing of the input data, the use of default data or preset data instead of the output results, a plausibility check of the two output results, a temporary interruption or a complete abort of data processing by the arithmetic units or another preset reaction. The safety operating mode thus offers protection against a DFA.

Correspondingly, a check of the results output by the first arithmetic unit 2 and the second arithmetic unit 4 for complementarity can also be carried out in the high-security operating mode illustrated above with reference to FIG. 2.

The operating modes explained with reference to FIGS. 2 to 5 are suitable for various tasks which a processor, for example a processor in a chip card or another crypto processor, must often perform alternately or in succession. When processing programs or program parts for authentication, encryption or access protection, maximum security against unauthorized attacks, for example against side-channel attacks, is required. The scope of these extremely security-related tasks is often comparatively small. They are run in the high security mode, which provides maximum security and medium performance.

Operations have the greatest scope in many applications or processor tasks, the lesser or none at all Make security requirements against attacks, however, processing them in the shortest possible time is desirable is, for example, to provide a user with a high level of comfort offer and save him waiting times. These operations can be run in the high performance mode a lower level of security against attacks, however one doubled compared to the high security mode Offers computing power.

Tasks also occur in numerous applications which are only slight or almost vanishing Computing power is required because, for example, in the program flow to a user's input or information that was requested by another facility becomes. These tasks can be done in the power saving mode run, which the low computing power of High security mode with the low security of the High performance mode combined, but the Power requirements of the arithmetic units halved.

An advantage of a processor according to the present invention is that by realizing two or three of the operating modes described above, in particular the High security mode along with the High performance mode and / or low power mode, one flexible adjustment of security standard, computing power and Power requirement is possible, being between the operating modes dynamically or switched during operation or can be changed. For example, in the High performance mode will prompt a user for a PIN to enter in the power saving mode on an input the PIN are maintained and then in the High security mode can be processed cryptographically.

To implement a processor which, according to the present invention, has two, three or four of the operating modes explained with reference to FIGS. 2 to 5, the circuit shown schematically in FIG. 1 consists of the first arithmetic unit 2 , the second arithmetic unit 4 , and the control device 6 and the complementing device 8 is only one example. As an alternative to the illustration in FIG. 1, the complementing device 8 , for example, a component of the second arithmetic unit 4 and its data input 28 can be connected downstream and / or a further complementing device can be provided in the data line 22 of the first arithmetic unit or in the first arithmetic unit 2 . Depending on the architecture or the circuitry used for the arithmetic units 2 and 4 , a complementation device may also be dispensed with, because, for example, only two lines have to be crossed in order to complement.

The control device 6 can switch on or activate the first arithmetic unit 2 and the second arithmetic unit 4 through the control lines 12 and 14 and switch it off or shut down (in the power-saving mode), but it can alternatively also do this by accessing the power supply of the two arithmetic units ,

The same data can be supplied in various ways via the data line 22 to the data input 20 of the first arithmetic unit 2 and via the data line 36 to the input 34 of the complementing device 8 . For example, a "data switch" (not shown in FIG. 1), which is connected to the data lines 22 and 36 , can be used to route data from a data source synchronously with the data input 20 of the first arithmetic logic unit 2 and with the input 34 in the complementing device 8 .

Alternatively, a data switch can be integrated in the control device 6 . Then, in a departure from the illustration in FIG. 1, the control device 6 is connected to a data source, the data input 20 of the first arithmetic unit 2 being connected to the control device 6 via a data line, and the input 34 of the complementing device 8 being connected to the control device via a data line 6 is connected. Depending on the desired operating mode, the control device 6 can then route the same data synchronously to the first arithmetic unit 2 and via the complementing or non-complementing complementing device 8 to the second arithmetic unit 4 , or different data to the first arithmetic unit 2 and via the non-complementing complementing device 8 to the conduct second arithmetic unit 4 or only pass data to first arithmetic unit 2 .

There are also various possibilities for routing commands via the command lines 18 and 26 to the command input 16 of the first arithmetic logic unit 2 and the command input 24 of the second arithmetic logic unit 4 . The command input 16 of the first arithmetic unit 2 and the command input 24 of the second arithmetic unit 4 can be connected directly to one and the same or to two different command sources via the command lines 18 and 26 , as was explained above in connection with FIG. 1. Alternatively, a command source can be connected to the control device 6 , which is connected via a command line to the command input 16 of the first arithmetic unit and via a command line to the command input 24 of the second arithmetic unit. Depending on the desired operating mode, the control device 6 then sends the same commands or different commands to the command input 16 of the first arithmetic unit 2 and the command input 24 of the second arithmetic unit 4 or only to one of the two arithmetic units 2 and 4 .

The control device 6 for controlling the two arithmetic units 2 and 4 can thus be implemented in various ways and can be effectively connected to the first arithmetic unit 2 , the second arithmetic unit 4 and the complementing device 8 , so that the first arithmetic unit 2 and the second one depending on the desired operating mode Arithmetic unit 4 can process the same or different data and commands synchronously or so that one of the two arithmetic units 2 and 4 can be shut down.

Furthermore, software implementation of the operating modes explained above with reference to FIGS. 2 to 4 and the change between them is possible. In this case, the processor has a first arithmetic unit 2 and a second arithmetic unit 4 , and the control device is implemented by commands which can be executed by the processor or the arithmetic units. The command input 16 of the first arithmetic logic unit 2 and the command input 24 of the second arithmetic logic unit 4 are connected to an instruction source or a program memory, for example a ROM (ROM = read only memory). The first arithmetic unit 2 and the second arithmetic unit 4 each have one or more data inputs 20 and 28 , all data sources which supply data which are to be processed in the high-security operating mode, for example a user interface via which a user enters a PIN , are connected in parallel with a data input 20 of the first arithmetic unit and a data input 28 of the second arithmetic unit in such a way that the data from the data source are fed to the first arithmetic unit 2 and the complement of the data from the data source is synchronized to the second arithmetic unit 4 .

As already explained above with reference to the exemplary embodiment shown in FIG. 1, this can be done, for example, by a complementing device in the data line between the data source and the data input of the second arithmetic unit or, depending on the architecture of the arithmetic unit, also simply by crossing Data lines take place. The command source contains pairs of commands, one of the commands being provided for the first arithmetic logic unit and being supplied to it via a command input 16 , and the other command of the pair being provided for the second arithmetic logic unit 4 and being synchronously via the command input 24 is fed.

Program parts which are provided for the high-security operating mode explained above with reference to FIG. 2 have pairs of instructions, each of which comprises two identical instructions. Program parts which are provided for processing in the high-performance operating mode explained above with reference to FIG. 3 have pairs of instructions which comprise two instructions to be processed simultaneously by the first arithmetic unit 2 and the second arithmetic unit 4 . Program parts which are provided for processing in the power-saving mode of operation explained above with reference to FIG. 4 have pairs of commands which for one of the arithmetic units 2 and 4 a command to be executed and for the respective other arithmetic unit a command which is not to be processed or a deactivation or Have shutdown command.

In the case of program parts which run in the high-security operating mode, the first arithmetic logic unit 2 and the second arithmetic logic unit 4 process synchronously complementary data from the same data source, controlled by identical commands. In the case of program parts which run in the high-performance operating mode, the first arithmetic unit 2 and the second arithmetic unit 4 process different data from one and the same or different data sources, controlled by commands which are generally different from one another. In the case of program parts which are intended for processing in the power-saving mode, one of the two arithmetic units processes data, controlled by commands, and the other arithmetic unit is shut down or switched off. In the case of three or more arithmetic units, a combination of the operating modes is possible.

The embodiments shown above are without further on processors with more than two arithmetic units, preferably with an even number of identical pairs Calculators expandable. In this case, all pairs of Calculators in the same operating mode or in different operating modes. In the power saving mode all arithmetic units except one can be switched off. in the The case of three or more arithmetic units is a combination of Operating modes possible.

The present invention is suitable for all processors which can be used for cryptographic or security applications and are to be protected against side-channel attacks, for example for processors in chip cards. Reference number list 2 first arithmetic unit
4 second arithmetic unit
6 control device
8 inverting device
12 control line
14 control line
16 command input
18 Command line
20 data input
22 Data line
24 command input
26 Command line
28 Data input
30 data line
32 Inverter output
34 Input of the inverting device
36 data line
38 control line

Claims (13)

1. Processor with the following features:
a first arithmetic unit ( 2 );
a second arithmetic unit ( 4 ); and
a control device ( 6 ) for controlling the two arithmetic units ( 2 ) and ( 4 ) in such a way that they work either in a complementary data processing high-security mode or in an independent data processing parallel mode. 2. Processor with the following features:
a first arithmetic unit ( 2 );
a second arithmetic unit ( 4 ); and
a control device ( 6 ) for controlling the two arithmetic units ( 2 ) and ( 4 ) in such a way that they either work in a complementary data processing high-security mode or are in a power-saving mode in which one of the arithmetic units ( 2 , 4 ) is switched off. 3. Processor with the following features:
a first arithmetic unit ( 2 );
a second arithmetic unit ( 4 ); and
a control device ( 6 ) for controlling the two arithmetic units ( 2 ) and ( 4 ) in such a way that they work either in a complementary data processing high-security mode or in a same data processing security mode. 4. Processor according to one of claims 1 to 3, further comprising a switchable complementing device ( 8 ), having an output ( 32 ), which is connected to an input ( 28 ) of the second arithmetic unit ( 4 ), for receiving data and for optional Output the received data or the complement of the received data. 5. Processor according to one of claims 1 to 4, further comprising the following features:
a third arithmetic unit; and
a fourth arithmetic unit;
wherein the third arithmetic unit and the fourth arithmetic unit can be controlled by the control device ( 6 ) in such a way that they operate either in a complementary data processing high-security mode or in an independent data processing parallel mode. 6. Processor according to one of claims 1 to 4, further comprising the following features:
a third arithmetic unit; and
a fourth arithmetic unit;
wherein the third arithmetic unit and the fourth arithmetic unit can be controlled by the control device ( 6 ) in such a way that they either work in a complementary data-processing high-security mode or are in a power-saving mode in which the third and / or fourth arithmetic unit is switched off. 7. Processor according to one of claims 1 to 4, further comprising the following features:
a third arithmetic unit; and
a fourth arithmetic unit;
wherein the third arithmetic unit and the fourth arithmetic unit can be controlled by the control device ( 6 ) in such a way that they operate either in a complementary data processing high-security mode or in a same data processing security mode. 8. Processor according to one of claims 1 to 7, in which the first arithmetic unit ( 2 ) and the second arithmetic unit ( 4 ) are designed such that they can process the same commands synchronously in the high-security mode. 9. Processor according to one of claims 1 to 8, wherein the first arithmetic unit ( 2 ) and the second arithmetic unit ( 4 ) are arranged spatially adjacent or interwoven. 10. Processor according to one of claims 1 to 9, wherein the Processor is a cryptography or security processor. 11. Processor with the following features:
a first arithmetic unit ( 2 );
a second arithmetic unit ( 4 );
a data source which is connected to the first arithmetic unit ( 2 ) and the second arithmetic unit ( 4 ) in such a way that the complement of the data is fed synchronously to the first arithmetic unit ( 2 ) and the second arithmetic unit ( 4 ); and
an instruction source, which has a pair of instructions, one of the instructions of the instruction pair being provided for the first arithmetic unit ( 2 ) and the other instruction of the instruction pair being provided for the second arithmetic unit ( 4 ), and which is connected to the first arithmetic unit ( 2 ) and the second arithmetic unit ( 4 ) is connected in such a way that the command of the command pair provided for the first arithmetic unit ( 2 ) synchronously communicates the first arithmetic unit ( 2 ) and the command of the command pair provided for the second arithmetic unit ( 4 ) to the second arithmetic unit ( 4 ) can be supplied. 12. The processor of claim 11, wherein the instruction provided for the first arithmetic unit ( 2 ) and the instruction provided for the second arithmetic unit ( 4 ) are the same. 13. Chip card with a processor according to one of the claims 1 to 12.