DE10118404C1 - Storage arrangement comprises a storage unit having a cell with a storage element, and a writing/reading device having a probe tip which moves via the storage unit with a single electron transistor arranged on the front end of the probe tip - Google Patents

Abstract

Storage arrangement comprises: a storage unit (101) having a cell (102) with a storage element (103); and a writing/reading device having a probe tip (105) which moves via the storage unit with a single electron transistor (106) arranged on the front end of the probe tip. The transistor has a changeable source-drain conductivity between a source electrode and a drain electrode. Preferred Features: The storage element is made from a metallic conducting material and is partially surrounded by electrically insulating material. The storage cell is formed as a floating gate storage cell.

Description

Computers with memory arrays come from different applications, be it as Mainframes, as personal computers, in washing machines, in Kitchen appliances, in motor vehicles, in telephones, in Answering machines or in other applications. A computer is here in the broadest sense as an electronic tax and / or to understand computing device.

The memory arrangement of the computer is for permanent or temporarily storing data, for example from Parameters required to operate the computer, or of calculation results that occur during the operation of the computer generated by the computer.

The memory arrangement has a memory with a plurality of memory cells. There is a date in each memory cell of the data as the memory content of the memory cell are saved. The memory arrangement also has a Reading device for reading the memory content (ROM, see below), or alternatively a read / write device for writing and reading the memory contents (RAM, see below).

In the case of memories, a basic distinction is made between Read storage or read only storage (ROM = Read Only Memory) on the one hand and read-write storage or storage with random access (RAM = Random Access Memory) on the other hand.

With a read only memory (ROM) is in each one A fixed memory content is stored in the memory cell. The memory content is due to the manufacturing process for the  Memory is fixed and is by means of the reading device readable, but not writable. As variants of the Read-only memory (ROM) there is the programmable read-only Memory (PROM = programmable ROM) in which the memory content can be registered exactly once, as well as the delete and Reprogrammable read-only memory (EPROM = erasable programmable ROM) and the electrically erasable and reprogrammable read only memory EEPROM = electrically EPROM), in which the memory content is repeated several times is enrollable.

In the case of a random access memory (RAM), the memory content is the memory cell by means of a read / write device either writable by writing or by read a read process.

Each memory cell has at least one memory element. The memory content of the memory cell is one in which Storage element stored electrical charge set.

In a conventional semiconductor-based memory device can be for the storage element depending on the storage type of the memory for example a transistor or a Capacitor used.

When writing the memory content of a memory cell a predetermined amount of charge of electric charge into the Storage element moved or from the storage element away. This shifting of electrical charges corresponds to an electrical current flow. To the electrical To cause electricity to flow, energy must be used accordingly the larger the electrical Is the amount of charge to be moved.

A current flow is also required to read the memory content be maintained.  

In addition, it is necessary to shift the amount of cargo The greater the amount of charge, the greater the time.

One goal in developing memory arrays is to the power consumption when writing and reading the Reduce storage arrangement.

Another goal in the development of memory arrays is the write and read speed at which the Memory can be written or read to increase.

The one required to operate a storage array Power consumption can be reduced by making the amount of electrical charge required for writing, especially for Changing the memory content has to be postponed, is reduced.

A single electron memory cell is described in [1]. The single electron memory cell has a memory element a charge island made of an electrically conductive material and with a diameter of a few nanometers. Two electrical leads from an electrically conductive Material lead to the cargo island. The cargo island and the Feed lines are each through a 1 to 2 nm thin Tunnel barrier made of an electrically insulating material separated from each other. Alternatively, as a storage element instead of the single charge island, several in a row arranged charge islands provided, each by a 1 to 2 nm thick tunnel barrier are separated from each other. The Memory content of the memory cell is by a few Electrons formed by means of Coulomb blockade on the Charge island or the charge islands are held. In [1] is further described that the electrons with an all higher containment energy on the charge islands included, the greater the number of in series arranged charge islands. They are accordingly Storage time of the electrons on the charge islands, after  which averages the electrons out of the charge islands tunnel, and the maximum temperature above which the Tunnel electrons out of the charge islands, the bigger, the greater the number of charge islands arranged in series is.

A single electron memory cell, the memory content formed by just a few electrons has very small ones Dimensions. But not just about electricity when operating the It is a goal of saving storage arrangement Manufacture of a memory array, the dimensions of the to select individual memory cells small.

The space available for the storage arrangement is usually limited. The limited space becomes even more so used more efficiently, the greater the integration density, d. H. the number of memory cells in a given space or a given area. Accordingly, it is a Another goal in the development and manufacture of Memory arrays to increase their integration density. For this purpose, for example, the individual memory cells be made smaller.

A traditional technology for making Memory devices is the semiconductor-based CMOS Technology (CMOS = Complementary Metal Oxide Semiconductor) silicon-based, in the circuit structures for the Memory arrangement can be produced lithographically. In CMOS Technology are currently minimal memory arrays Structure sizes of 130 nm can be produced as standard.

If the minimum structure size is further reduced CMOS technology is increasingly reaching its limits.

As insulating, semiconducting and metallically conductive Structures with very small dimensions are made of nanotubes Boron nitride or known from carbon. Are nanotubes  Fullerenes from atoms, which form a tubular crystalline structure are arranged. You can use one Diameters from approximately 0.2 (0.5) nanometers up to approximately 50 Nanometers and more and a length of up to several Micrometers are manufactured. Typically this is Diameter 1 to 20 nm and the length up to a few hundred Nanometers.

[2] discloses a method for producing carbon nanotubes in a closely packed arrangement of 1.1.10 ¹⁰ tubes per cm ² . First, the surface of a thin aluminum sheet, which serves as a substrate, is provided with fine pores by anodization. A catalyst surface made of a catalyst material is deposited at the bottom of each pore. A step is then carried out in a space above the porous aluminum sheet treated with catalyst material, in which carbon nanotubes are produced. The carbon nanotubes are created exclusively on surface areas of the aluminum sheet that are covered with the catalyst material, ie exclusively on catalyst material. No carbon nanotubes are formed directly on the aluminum sheet. For example, reduced copper can be provided as the catalyst material, which has been reduced at a temperature of approximately 600 ° C. in a CO atmosphere.

As a read / write device for writing and reading a hard drive memory, such as for one Personal computer being used becomes a read / write arm used that in an area above the hard drive like that is movable that he can choose over each one Storage cell can be positioned.

From [3] is a memory arrangement with a memory field and a matrix of 32 × 32 cantilevers known. The cantilevers can be moved in an area above the storage field. With  the majority of cantilevers, it is possible to have several Read out memory cells at the same time so that the data Readout rate compared to a memory arrangement with only one Cantilever is increased.

From [4] is a single electron transistor scanning microscope known with the electric charges and fields at one Surface with a resolution of approximately one percent of the Charge of a single electron can be measured in a spatially resolved manner. The single electron transistor scanning microscope works similar to a scanning tunneling microscope. In both, one Scanning probe tip over the surface to be examined screened and a signal measured by electrical Charges and fields on and near the surface is influenced. The scanning tunneling microscope shows as Raster probe tip a fine metal tip, for example a tip of tungsten. The single electron transistor Scanning microscope has a scanning probe tip at the front Tipped glass fiber with one on the tipped front Single electron transistor arranged at the end (SET = single electron transistor).

In [5] is a single electron transistor scanning microscope for imaging objects at ambient temperature described. In doing so, the near field is scanned Single electron transistor used. Detected in particular the single electron transistor variations in one electrical field surrounding or from the object goes out, the object in the ambient temperature can remain, although the single electron transistor is cooled.

Carbon fibers are known from [6], which consist of single-wall carbon nanotubes are made. Moreover is in [6] a method for purifying a mixture single-walled carbon nanotubes and amorphous Carbon pollution revealed.  

A method for storing information units in the Nanometer range is known from [7], in which the well-shaped Indentations are created in a precious metal surface.

The problem underlying the invention is an efficient, compact and fast storage arrangement with high To create integration density.

The problem is solved by a memory arrangement with the Features according to the independent claim.

The storage arrangement has:
a memory with at least one memory cell, each with at least one memory element, each memory cell having a memory content that can be changed by a write operation and is determined by an electrical charge stored in the memory element, and
a read / write device for writing and reading the memory content, with at least one scanning probe tip movably arranged above the memory, with an individual electron transistor arranged on the front end of the scanning probe tip facing the memory, with a source electrode, a drain electrode, a charge island, one between the source -Electrode and the charge island arranged first tunnel barrier and a second tunnel barrier arranged between the charge island and the drain electrode, wherein the single-electron transistor has a variable source-drain conductivity between the source electrode and the drain electrode, wherein the scanning probe tip above the memory cell can take two positions, namely
a writing position in which the memory content of the memory cell can be written into the memory cell by a voltage applied to the memory cell by the scanning probe tip, and
a reading position in which the memory content of the memory cell can be read out on the basis of the source-drain conductivity of the single electron transistor.

The single electron transistor has electrical Charges in the memory cell have a high sensitivity about 1% of the charge of a single electron. Accordingly, with the read / write device with the scanning probe tip movably arranged above the memory, at the front end facing the storage the Single electron transistor is arranged, also a Memory cell are read out, the memory content by a very small amount of charge is formed. Furthermore can use the scanning probe tip to charge small amounts of charge be moved so that the read / write device Allows you to read and write memory contents are formed by very small amounts of charge.

The invention thus enables a power-saving and thus efficient writable and readable memory arrangement.  

In addition, the grid probe tip enables a high Spatial resolution. Consequently, with the read / write device the memory cell array can then also be written to and read out, if the memory cell array is a high density Memory cell array is.

The memory element of the memory cells of the memory field can be made of a dielectric or a combination of be made of several different dielectrics.

The storage element is preferably made of a metallic made of conductive material and at least partially so surrounded by electrically insulating material that in the Electrical charge stored during a storage element predetermined storage time remains in the storage element. The storage element can, for example, be made of metal or Be made of polysilicon.

The memory cell is further preferred as a floating gate Memory cell trained. With a floating gate Memory cell is made of a floating gate as a memory element provided a metallic conductive material that at least partially from an electrically insulating Material is surrounded. By means of a control gate electrical charge carriers can be loaded onto the floating gate and can be pushed out of the floating gate again. The Memory content of the memory cell is due to the electrical Charge determined on the floating gate.

Basically, the dimensions of the memory cell, and especially the memory element, freely selectable. So that Integration density of the memory array is high, the Dimensions of the memory cell are preferably as small as possible selected.

The storage element is further preferably dimensioned and the electrically insulating material is arranged so that the  electrical charge stored in the storage element by means of the effect of the Coulomb blockade on the Storage element is kept stored. This is preferred at room temperature and / or at a temperature of up to approx. 150 ° C the case. In the storage element, if it is so fully loaded with load carriers that a fully loaded memory state is reached, e.g. Legs logical "one", only a few charge carriers are stored.

With such a storage element based on a Coulomb blockade is a power-saving memory cell realized. In addition is realizes a fast memory cell since the time that is required to the very small number of Moving load carriers is small.

The storage element preferably has at least one or in each spatial direction has a dimension of no more than a few ten nanometers, e.g. B. not more than 35 nm or 20 nm.

The memory cell further preferably has at least one each Hetero-nanotube with at least one electrically insulating one first nanotube section, at least one metallic conductive second nanotube section and at least one electrically insulating third nanotube section. The first, second and third nanotube sections are included arranged so that the metallically conductive second Nanotube section at its first end to the electrical isolating first nanotube section directly adjacent and at its second end to the electrically insulating third Nanotube section directly adjacent. The metallic conductive nanotube section is therefore between the electrically insulating first nanotube section and the electrically insulating third nanotube section.

The metallically conductive second nanotube section provides the storage element. The first and the third insulating nanotube section represents one  Tunnel barrier. In the metallically conductive second Nanotube section is an electrical charge of some few individual electrons using Coulomb blockade storable.

The hetero-nanotube can be more insulating and metallic have conductive nanotube sections. The The hetero nanotube alternately prefers one metallically conductive and an insulating nanotube Section on. Any metallically conductive nanotube Section forms a cargo island divided by two insulating nanotube sections is limited, and on the Load carriers can be stored by means of a Coulomb blockade. The Memory content of a single memory cell is due to the Sum of the total connected in series on all Charge islands of the corresponding hetero-nanotube stored load carriers set. Such Configuration of the hetero-nanotube with several in series switched charge islands has the advantage that the Storage time is increased.

A lower end section of the hetero-nanotube is preferred from a metallically conductive fourth nanotube section formed and an upper end portion of the hetero nanotube of a metallically conductive fifth nanotube section educated. I.e. the hetero nanotube is preferred on both Ends of a metallic conductive nanotube section limited.

Electrical supply lines for contacting the Storage element can also be made of metallic conductive Be formed nanotubes.

For a metallically conductive nanotube section preferably a metallic conductive carbon Nanotube used.  

For at least one electrically insulating nanotube Section can be an electrically insulating boron nitride Nanotubes can be used.

The single electron transistor can on the memory facing front end of the scanning probe tip arranged be that either the source electrode or the drain Electrode is closest to the memory.

With this configuration, the memory content in the Storage element one under the grid probe tip positioned memory cell the energy levels for Electrons on the charge island on the one hand and the between the source electrode and the drain electrode actually applied voltage, on the other hand, to a similar extent affected.

The single electron transistor is preferably at the front end the grid probe tip arranged that the charge island is arranged closer to the memory than the source electrode and the drain electrode. With this configuration are through the memory content in the memory element only or at least mainly the energy levels for electrons on the Charge island influenced. The one between the source electrode and the voltage applied to the drain electrode is not or at least hardly influenced. This makes the memory cell particularly energy-saving and easy to control configured.

In an alternative embodiment of the invention the read / write device has a plurality of scanning probe tips, so that several memory cells can be written or are readable.

In a memory arrangement with hetero nanotubes as Memory cells can be used in any of the hetero-nanotubes Arrangement may be provided on a substrate. The hetero-  Nanotubes can be arranged criss-cross to one another. The hetero-nanotubes are preferably approximately parallel arranged to each other. This is the description and Reading the individual memory cells easier. The Hetero-nanotubes can be arranged further bent. The hetero-nanotubes are preferably approximately upright and aligned straight. This in turn is that Describe and read out the individual memory cells relieved, since crosstalk between neighboring Memory cells is difficult. More preferably all point Hetero-nanotubes are approximately the same length, so the upper ends of the hetero-nanotubes together a single form a flat surface. This also describes and Reading the individual memory cells easier. In particular, the spacing of the scanning probe tip can Read / write device constant when reading and writing are kept, which means the equipment effort at Read / write device is reduced.

A single memory cell can be separated by a single one Hetero-nanotube can be formed. Alternatively, a single Memory cell each by a bundle of several adjacent individual hetero-nanotubes can be formed. in the the second case is the memory content by the sum of Charges in all individual hetero-nanotubes of one Bundle formed. Therefore the memory arrangement works reliable even with some hetero-nanotubes are faulty. Consequently, when using multiple hetero-nanotubes for a single memory cell the reliability requirements of the Hetero-nanotube less.

Optionally, the hetero nanotubes can be targeted at one A plurality of predetermined locations are made. This can be caused at the predetermined locations Catalyst surfaces provided from a catalyst material that are involved in the manufacture of hetero-nanotubes,  that only on the catalyst surfaces nanotubes be trained and that away from the catalyst surfaces no nanotube is formed. As a catalyst material For example, reduced copper can be provided, which at a temperature of approximately 600 ° C in a CO atmosphere has been reduced. Alternatively, as a catalyst material any transition metal can be used.

Each catalyst surface can optionally be sunk into a pore be so that the catalyst area is no increase compared their environment, which has no catalyst surface, represents, but with their surroundings, which none Has catalyst surface, terminates approximately flush.

In particular, a memory in which hetero-nanotubes are used for the memory cells can be provided with:
a substrate,
a metallically conductive back contact layer arranged flat on the substrate and
at least one catalyst particle provided on the surface of the back contact layer, wherein
a hetero nanotube is arranged upright on the at least one catalyst particle,
the hetero-nanotube is surrounded on its outer wall by a nanotube insulating layer made of a first electrically insulating material and regions of the surface of the back contact layer which are not occupied by a catalyst particle are covered by a back contact insulating layer made from a second electrically insulating material,
a filling layer made of a third electrically insulating material is arranged on the back contact insulating layer in such a way that the hetero-nanotube partially protrudes from the filling layer at the top and
a counterelectrode layer made of a metallic conductive material is formed on the filling layer, the counterelectrode layer being arranged at a height with respect to the hetero-nanotube, so that the counterelectrode layer is at least partially at the same height as the metallic conductive fourth nanotube section in the one opposite the catalyst particle upper end section of the hetero nanotube.

Embodiments of the invention are in the figures are shown and are explained in more detail below. Show it:

. Figure 1 shows a memory device according to an embodiment of the invention, with a memory and a read / write means;

FIG. 2a shows an enlarged partial view of the read / write device from FIG. 1;

Figure 2b shows the read / write device of Figure 2a in the equivalent circuit..;

FIG. 3 shows a hetero nanotube, each with an insulating nanotube section which is alternately formed from a boron nitride nanotube and a metallically conductive nanotube section which is formed from a metallically conductive carbon nanotube; FIG.

FIG. 4 shows a memory according to an embodiment of the invention;

Figure 5a shows a memory according to another embodiment of the invention in a partially completed first manufacturing condition.

5b the memory of Figure 5a in a second manufacturing stage..;

5c the memory of Figure 5a in a third manufacturing condition..;

5d the memory of Figure 5a in a fourth, final manufacturing condition..;

FIG. 5e shows the memory from FIG. 5d together with a scanning probe tip of a read / write device.

Fig. 1 shows a memory device according to an embodiment of the invention, with a memory 101 and a read / write device 104.

The memory 101 has a plurality of memory cells 102 , each with at least one memory element 103 . Each memory cell 102 has a memory content that can be changed by a write operation and is determined by an electrical charge stored in the memory element 103 .

The read / write device 104 is provided for writing the memory content through the writing process and for reading the memory content. The read / write device 104 includes a movably disposed on the memory 101 with a scanning probe tip 105 to the memory 101 facing front end of the scanning probe tip 105 disposed single-electron transistor 106 on.

FIG. 2a shows an enlarged partial view of the read / write device from FIG. 1.

The single electron transistor 106 has a source electrode 201 , a drain electrode 202 , a charge island 203 , a first tunnel barrier 204 arranged between the source electrode 201 and the charge island 203 and a second tunnel barrier arranged between the charge island 203 and the drain electrode 202 205 on.

The single electron transistor 106 has a variable source-drain conductivity between the source electrode 201 and the drain electrode 202 .

The scanning probe tip 105 can assume two positions above the storage cell 102 .

On the one capable scanning probe tip 105 to assume a writing position on the memory cell 102 in the electric by a voltage applied from the scanning probe tip 105 to the memory cell 102 voltage of the memory content of the memory cell 102 is inscribed. In the writing position, in particular the distance between the scanning probe tip 105 and the memory cell 102 is selected such that the memory content of the memory cell 102 can be changed with the applied electrical voltage. For example, electrons can be removed from the memory cell 102 by applying a suitable positive electrical voltage to the scanning probe tip 105 . By applying a suitable negative electrical voltage to the scanning probe tip 105 , electrons can be supplied to the memory cell 102 .

On the other hand, the scanning probe tip 105 can assume a reading position above the memory cell 102 , in which the memory content of the memory cell 102 can be read out on the basis of the source-drain conductivity of the single-electron transistor 106 .

FIG. 2b shows the read / write device from FIG. 2a in the equivalent circuit diagram.

The source electrode 201 and the charge island 203 are connected to one another via a first tunnel barrier 204 . The charge island 203 and the drain electrode 202 are connected to one another via a second tunnel barrier 205 . The storage cell 102 , in particular the storage element 103 of the storage cell 102 , has a similar effect on the charge island 203 as a gate electrode arranged opposite the charge island 203 , with which the energy levels for charge carriers on the charge island 203 can be tuned (changed). Depending on the electrical fields emanating from the memory cell 102 and the electrical charges present there, the Coulomb blockade of the charge island 203 is either established or removed. Accordingly, the single electron transistor 106 between the source electrode 201 and the drain electrode 202 is either blocked or conductive. Thus, on the basis of the conductivity of the single electron transistor 106 existing between the source electrode 201 and the drain electrode 202 , electrical fields emanating from the memory cell 102 and electrical charges stored in the memory cell 102 can be detected.

To read the memory cell 102 in the read position, a suitably predetermined electrical voltage is applied between the source electrode 201 and the drain electrode 202 of the single-electron transistor 106 . A suitable distance of approximately 1 nm to approximately 10 nm, typically 2 nm, is set between the charge island 203 and the surface of the memory 101 . The raster probe tip 105 is positioned over the memory cell 102 to be read.

Depending on the electrical charge stored in the memory cell 102 , the single electron transistor 106 is conductive or blocked. For example, the single-electron transistor is disabled 106 if a logic "one" corresponding electric charge is stored in the memory cell 102, and the single-electron transistor 106 is conductive, if in the memory cell 102 is a logic "zero" electric charge corresponding is stored, or vice versa ,

The single electron transistor can be manufactured as follows become. An optical fiber becomes conical at one end pointed. A foremost end portion of the thus produced The tip is flattened so that at the front end the sharpened glass fiber a flat surface is formed. The pointed and flattened glass fiber is in one first evaporation step on its conical long side with  vaporized a metal so that a first metal layer is trained. Because of its own shading only evaporated less than half the glass fiber in the circumferential direction. In a second evaporation step, it is turned by 180 ° Longitudinal axis rotated glass fiber again vaporized, so that previously switched off side of the glass fiber is steamed and a second metal layer is formed. Between the first metal layer and the second metal layer remain two extending in the longitudinal direction of the glass fiber unevaporated areas. The first metal layer and the second Metal layers are consequently electrically insulated from one another. Then the flat surface at the front end of the flattened tip oxidized so that on the flat surface an oxide layer is formed. In a third Evaporation step is a third on the oxide layer Metal layer evaporated, leaving the charge island is trained. The first metal layer serves as a source Electrode. The second metal layer serves as a drain Electrode. The one below the third metal layer The oxide layer fulfills the function of the first and the second Tunnel barrier.

Fig. 3 shows a hetero-nanotube three hundred and first

The hetero-nanotube 301 , with several layer-like materials with different electrical conductivity properties, is functionally similar to a semiconductor heterostructure, e.g. B. a GaAs / AlGaAs heterostructure.

The hetero-nanotube shown in FIG. 3 alternately has an insulating nanotube section 302 , 304 , which is formed from a boron nitride nanotube (shown in stripes), and a metallically conductive nanotube section 303 , 305 , 306 , which consists of a Metallic conductive carbon nanotube is formed on. Each insulating nanotube section has a thickness of approximately 2 nm and represents a tunnel barrier between the two adjacent metallically conductive nanotube sections. For example, the third nanotube section 304 forms a tunnel barrier between the second nanotube section 303 and the fourth nanotube section 305 represents

Different methods can be used to produce the hetero nanotube 301 . In a first method, a first nanotube, for example a carbon nanotube, is first produced. Then, starting at the upper end of the first nanotube, a second nanotube, for example a boron nitride nanotube, is produced. A further nanotube, for example a carbon nanotube, is produced at the upper end of the second nanotube. Further corresponding manufacturing steps can follow. In a second process, several different nanotubes are manufactured separately and then assembled into a single hetero nanotube. In a third method, a carbon nanotube is first produced and converted into a boron nitride nanotube in predetermined sections, so that a hetero nanotube is formed which is formed in the predetermined subsections from a boron nitride nanotube and otherwise from carbon nanotubes is formed.

In particular, the hetero-nanotube from FIG. 3 has an electrically insulating first nanotube section 302 , a metallically conductive second nanotube section 303 and an electrically insulating third nanotube section 304 . The first, second and third nanotube sections 302 , 303 , 304 are arranged such that the metallically conductive second nanotube section 303 directly adjoins the electrically insulating first nanotube section 302 at its first end and at the second end thereof electrically insulating third nanotube section 304 directly adjacent. The metallically conductive nanotube section 303 thus lies between the electrically insulating first nanotube section 302 and the electrically insulating third nanotube section 304 .

The metallically conductive second nanotube section 303 here forms part of the memory element 103. The first insulating nanotube section 302 and the third insulating nanotube section 304 each represent a tunnel barrier. In the metallically conductive second nanotube section 303 there is an electrical charge of a few individual electrons can be stored using Coulomb blockade.

The hetero-nanotube 301 has, subsequent to the electrically insulating third nanotube section 304 , a further metallically conductive nanotube section made of a carbon nanotube (shown in white). This is in turn followed by another electrically insulating nanotube section made of a boron nitride nanotube (shown in stripes).

Each metallically conductive nanotube section 303,. , , forms a charge island, which is formed by two insulating nanotube sections 302 , 304,. , , is limited, and on which charge carriers can be stored by means of a Coulomb blockade. The memory content of the hetero-nanotube 301 is determined by the sum of the total of all charge islands 303 ,. , , of the hetero-nanotube 301 stored charge carriers.

In addition, the hetero-nanotube 301 has a metallically conductive fourth nanotube section 305 at its one end section. At its other end section, the hetero-nanotube 301 has a metallically conductive fifth nanotube section 306 . The two metallically conductive nanotube sections 305 and 306 can be used for the electrical coupling of the hetero nanotube 301 to an external line arrangement (not shown).

In total, the hetero-nanotube has nine metallically conductive nanotube sections (shown in white) 305 , 303 , 306 and eight electrically insulating nanotube sections (shown in stripes). The hetero-nanotube 301 accordingly has seven charge islands 303 ,. , , in which electrical charge carriers can be stored by means of a Coulomb blockade.

In alternative embodiments of the hetero-nanotube 301 according to the invention, more or less than seven charge islands are provided. For example, a single charge island can be provided, or three charge islands can be provided. Alternatively, 10 charge islands can be provided. Alternatively, 20 charge islands can also be provided. A total of 3 to 10 charge carriers are typically stored together on all charge islands.

According to one embodiment of the invention, a memory arrangement is provided with a memory 101 and a read / write device 104 , in which the memory 101 has a plurality of memory cells 102 , each memory cell 102 having a single hetero-nanotube 301 . The memory 101 of this memory arrangement is shown in FIG. 4.

The memory 101 from FIG. 4 is provided with: a substrate 401 , a metallically conductive back contact layer 402 arranged flat on the substrate 401 and a plurality of catalyst particles 404 provided on the surface 403 of the back contact layer 402 . A hetero nanotube 301 is arranged upright on each catalyst particle 404 . Each hetero-nanotube 301 is surrounded on its outer wall 405 by a nanotube insulating layer 406 made of a nitride. Not occupied by a catalyst particle 402 regions of the surface 403 of the back contact layer 402 are covered by a back contact insulating layer 407 made of a nitride. A filler layer 408 made of silicon dioxide is arranged on the back contact insulating layer 407 in such a way that the spaces between the individual hetero-nanotubes are almost completely filled with silicon dioxide in such a way that the hetero-nanotubes 301 partially protrude from the filler layer 408 at the top. On the filling layer 408 is a counter electrode layer 409 made of a metal, e.g. B. aluminum. The counter-electrode layer 409 is arranged at a height with respect to the hetero-nanotube 301 such that the counter-electrode layer 409 is at least partially at the same level as the metallically conductive fourth nanotube section 306 in the upper end section of the hetero-nanotube 301 opposite the catalyst particle 404 . A region of the back contact insulating layer 407 arranged between the fourth nanotube section 306 and the counter electrode layer 409 serves as a tunnel barrier between the fourth nanotube section 306 and the counter electrode layer 409 . Correspondingly, the back contact insulating layer 407 has a thickness of approximately 2 nm that it is suitable as a tunnel barrier.

When the Coulomb blockage is released in one of the hetero-nanotubes 301 , an electrical current can flow from the back contact layer 402 through the hetero-nanotube 301 into the counter electrode layer 409 , and in the opposite direction. Accordingly, an electrical charge stored in the hetero-nanotube can optionally flow into the back contact layer 402 or into the counter-electrode layer 409 or a preselected amount of electrical charge can be supplied to the hetero-nanotube 301 .

According to a further embodiment of the invention, a memory arrangement is provided which has a memory 101 which is basically constructed in the same way as the memory from FIG. 4. FIG. 5e shows a memory arrangement according to this embodiment.

In the memory from FIG. 5e, in comparison to the memory from FIG. 4, the catalyst particles 404 are additionally arranged on the pore bottom 502 of pores 501 countersunk in the back contact layer 402 . A single catalyst particle 404 is arranged in each of the pores 501 . A single memory cell 102 is formed by each individual pore 501 with the individual hetero-nanotube 301 arranged therein.

In an alternative embodiment to the embodiment of the invention shown in FIG. 5e, five hetero-nanotubes 301 are provided in each pore 501 .

In further alternative embodiments to the embodiment of the invention shown in FIG. 5e, two to 30 hetero-nanotubes 301 are provided in each pore 501 .

A method for producing the memory 101 shown in FIG. 5e is explained below with reference to FIGS. 5a to 5d.

As shown in FIG. 5a, a substrate 401 is first provided. The substrate can be made of a semiconductor material, e.g. B. silicon or a compound semiconductor, or z. B. from an insulator material, for. B. consist of a glass. An aluminum layer is formed on the substrate, which has the function of the back contact layer 402 . Instead of aluminum, another electrically conductive material can alternatively be used for the back contact layer, e.g. B. another metal such as titanium or gold. A plurality of pores 501 are formed in the aluminum back contact layer 402 . A catalyst particle 404 made of copper is deposited on the pore bottom 502 of each pore 501 . The catalyst particles serve as growth nuclei for the subsequent growth of the hetero-nanotubes 301 .

As shown in FIG. 5b, a hetero-nanotube 301 is formed on each catalyst particle 404 .

The respective hetero-nanotube 301 can be produced in that a carbon nanotube 305 is formed on the catalyst particle 404 , a boron nitride nanotube 302 is formed on the upper end of the carbon nanotube 305 , and on the upper end of the boron nitride nanotube 302 a carbon nanotube 303 is formed, a boron nitride nanotube 304 is formed on top of the carbon nanotube 303 , other nanotubes are formed in the same way, and finally a final carbon nanotube 306 is formed.

Alternatively, the respective hetero-nanotube 301 can be produced in that a carbon nanotube 305 is formed on the catalyst particle 404 , the carbon nanotube 305 is converted into a boron nitride nanotube in an upper section, so that a boron nitride nanotube 302 is formed For example, if a carbon nanotube 303 is formed on the upper end of the boron nitride nanotube 302 , the carbon nanotube 303 is converted into a boron nitride nanotube in an upper portion so that a boron nitride nanotube 304 is formed, and so on Nanotubes are formed and finally a final carbon nanotube 306 is formed.

The next process steps are illustrated in Fig. 5c. Thus, nitride is deposited next, so that the hetero-nanotube 301 is surrounded on its outer walls 406 by a nanotube insulating layer 406 made of nitride and is covered at its upper end by a cover layer 503 made of nitride. Subsequently, interstices remaining between the hetero-nanotubes surrounded with nitride are filled with oxide (silicon dioxide), so that a filling layer 408 is formed. The surface formed from the filler layer 408 and the cover layers 503 of the hetero-nanotubes 301 is planarized by means of CMP, so that a flat surface is generated.

The process steps that now follow are illustrated in FIG. 5d. The oxide of the filler layer 408 is etched back, so that with each hetero-nanotube 301 an upper section of the hetero-nanotube 301 projects out of the filler layer 408 at the top. The nanotube insulating layer 406 and the cover layer 503 made of nitride remain. Now a counterelectrode layer 409 made of metal, eg, is applied to the filler layer 408 and to the hetero-nanotubes 301 covered by the respective cover layer 503 . B. aluminum, titanium or gold. The counter electrode layer 409 is etched back in such a way that a counter electrode layer 409 only remains on the filling layer 408 . The hetero-nanotubes 301, however, are exposed. The cover layer 503 is then removed, so that the arrangement shown in FIG. 5d is produced.

The memory 101 is thus completed.

Fig. 5e shows the memory 101, the preparation in Fig. Has been illustrated 5a to 5d, together with the scanning probe tip 105 of a read / write device 104. The scanning probe tip 105 is shown in a highly schematic manner.

The following publications are cited in this document:
[1] W. Rösner et al., "Simulation of single electron circuits", Microelectronic Engineering 27, 55-58 ( 1995 )
[2] JS Suh and JS Lee, "Highly ordered two-dimensional carbon nanotube arrays", Appl. Phys. Lett. 75, 2047-2049 ( 1999 )
[3] MI Lutwyche et al., "Millipede - A Highly-Parallel Dense Scanning-Probe-Based Data-Storage System", ISSCC 2000 IEEE International Solid-State Circuits Conference, 126-128 ( 2000 )
[4] MJ Yoo et al., "Scanning Single-Electron Transistor Microscopy: Imaging Individual Charges", Science 276, 579-582 ( 1997 )
[5] WO 00/34796 A1
[6] WO 98/39250 A1
[7] DE 40 21 075 A1

LIST OF REFERENCE NUMBERS

FIG.

1

101

Storage

102

memory cell

103

storage element

104

Reader / writer

105

Scanning probe tip

106

Single-electron transistor

FIG.

2

201

Source electrode

202

Drain

203

charge island

204

First tunnel barrier

205

Second tunnel barrier

FIG.

3

301

Straight nanotube

302

electrically insulating first nanotube section

303

Metallically conductive second nanotube section

304

electrically insulating third nanotube section

305

Metallically conductive fourth nanotube section

306

Metallically conductive fifth nanotube section

FIG.

4

401

substratum

402

Back contact layer

403

Surface of the back contact layer

404

catalyst particles

405

Outer wall of the nanotube

301

406

Nanotube insulation

407

Back-contact insulating layer

408

filling layer

409

Counter electrode layer

FIG.

5

a-

5

e

501

pore

502

pores ground

503

cover layer

Claims (12)

1. Storage arrangement with
a memory ( 101 ) with at least one memory cell ( 102 ), each with at least one memory element ( 103 ), each memory cell ( 102 ) having a memory content that can be changed by a write operation and is determined by an electrical charge stored in the memory element ( 103 ), and
A read / write device ( 104 ) for writing and reading the memory content, with at least one scanning probe tip ( 105 ) movably arranged above the memory ( 101 ), with a single electron transistor () arranged on the front end of the scanning probe tip ( 105 ) facing the memory ( 101 ). 106 ) with a source electrode ( 201 ), a drain electrode ( 202 ), a charge island ( 203 ), a first tunnel barrier ( 204 ) arranged between the source electrode ( 201 ) and the charge island ( 203 ) and one between the Charge island ( 203 ) and the drain electrode ( 202 ) arranged second tunnel barrier ( 205 ), the single electron transistor ( 106 ) having a variable source-drain conductivity between the source electrode ( 201 ) and the drain electrode ( 202 ),
wherein the scanning probe tip ( 105 ) can assume two positions above the memory cell ( 102 ), namely
a writing position in which the memory content of the memory cell ( 102 ) can be written into the memory cell ( 102 ) by a voltage applied by the scanning probe tip ( 105 ) to the memory cell ( 102 ), and
a reading position in which the memory content of the memory cell ( 102 ) can be read out on the basis of the source-drain conductivity of the single electron transistor ( 106 ). 2. Storage arrangement according to claim 1, wherein the storage element ( 103 ) is made of a metallic conductive material and is at least partially surrounded by electrically insulating material such that the electrical charge stored in the storage element ( 103 ) during a predetermined storage time in the storage element ( 103 ) remains. 3. Memory arrangement according to claim 2, wherein the memory cell ( 102 ) is designed as a floating gate memory cell. 4. Storage arrangement according to claim 2 or 3, wherein the storage element ( 103 ) is dimensioned and the electrically insulating material is arranged such that the electrical charge stored in the storage element ( 103 ) by means of the effect of the Coulomb blockade on the storage element ( 103 ) is saved. 5. Storage arrangement according to claim 4,
in which the memory cell ( 102 ) each has at least one hetero-nanotube ( 301 ) with at least one electrically insulating first nanotube section ( 302 ), at least one metallically conductive second nanotube section ( 303 ) and at least one electrically insulating third nanotube section ( 303 ) 304 ), the first, second and third nanotube sections ( 302 , 303 , 304 ) being arranged such that the metallically conductive second nanotube section ( 303 ) has at its first end the electrically insulating first nanotube section ( 302 ) directly adjoins and directly adjoins the electrically insulating third nanotube section ( 304 ) at its second end,
wherein the metallically conductive second nanotube section ( 303 ) represents the storage element ( 103 ). 6. The memory arrangement as claimed in claim 5, in which a lower end section of the hetero-nanotube ( 301 ) is formed by a metallically conductive fourth nanotube section ( 305 ) and an upper end section of the nanotube ( 301 ) by a metallically conductive fifth nanotube section ( 305 ) 306 ) is formed. 7. Storage arrangement according to claim 5 or 6, in the case of at least one metallically conductive Nanotube section a metallic conductive carbon Nanotube is used. 8. Storage arrangement according to one of claims 5 to 7, in the case of at least one electrically insulating one Nanotube section an electrically insulating carbon Nanotube is used. 9. Storage arrangement according to one of claims 5 to 8, in the case of at least one electrically insulating one Nanotube section an electrically insulating boron nitride Nanotube is used. 10. Storage arrangement according to one of claims 1 to 9, in which the charge island ( 203 ) is arranged closer to the memory ( 101 ) than in each case the source electrode ( 201 ) and the drain electrode ( 202 ). 11. Memory arrangement according to one of claims 6 to 10, with
a substrate ( 401 ),
a metallically conductive back contact layer ( 402 ) arranged flat on the substrate ( 401 ) and
at least one catalyst particle ( 404 ) provided on the surface ( 403 ) of the back contact layer ( 402 ),
in which
on which at least one catalyst particle ( 404 ) a hetero nanotube ( 301 ) is arranged upright,
the hetero-nanotube (301) on its outer wall (405) of a nanotube-insulating layer (406) is surrounded by a first electrically insulating material and not of a catalyst particles (402) occupied areas of the surface (403) of the back contact layer (402) of a back contact insulating layer ( 407 ) made of a second electrically insulating material is covered,
a filling layer ( 408 ) made of a third electrically insulating material is arranged on the back contact insulating layer ( 407 ) such that the hetero-nanotube ( 301 ) partially protrudes from the filling layer ( 408 ) and
a counter-electrode layer ( 409 ) made of a metallic conductive material is formed on the filling layer ( 408 ), the counter-electrode layer ( 409 ) being arranged at a height with respect to the hetero-nanotube ( 301 ) such that the counter-electrode layer ( 409 ) is at least partially on the same Like the metallically conductive fourth nanotube section ( 306 ), the height lies in the upper end section of the hetero nanotube ( 301 ) opposite the catalyst particle ( 404 ). 12. The storage arrangement as claimed in claim 11, in which a plurality of catalyst particles ( 404 ) are arranged on the pore bottom ( 502 ) of pores ( 501 ) countersunk in the back contact layer ( 402 ), at least one catalyst particle ( 404 ) being arranged in each pore ( 501 ), wherein each individual pore ( 501 ) with the at least one hetero-nanotube ( 301 ) arranged therein forms a single memory cell ( 102 ).