DE10111454A1 - Memory arrangement for computer has memory cell field, decoder circuit with word, bit line decoders, read output for reading from individual cells by selecting corresponding word, bit lines - Google Patents

Abstract

The memory arrangement has a memory cell field (2) and a decoder circuit for reading from the memory cells (3) with a word line decoder (8), a bit line decoder (11) and a read output (14) for reading out the contents of each individual cell by selecting the word and bit lines corresponding to individual cells. Independent claims are also included for the following: a method of reading from a memory arrangement and a computer arrangement with a processor and memory arrangement.

Description

The invention relates to a memory arrangement and a Computer with a memory array.

Computers with memory arrays come from different applications, be it as Mainframes, as personal computers, in washing machines, in Motor vehicles, in telephones, in answering machines or in other applications. A computer is the broadest Senses as an electronic tax and / or Computing device to understand. The memory arrangement of the Computers is used, for example, to save Parameters for operating the computer. Alternatively, the Storage arrangement for permanent or interim Store calculation results or other data.

The space available for the storage arrangement is usually limited. The limited space becomes even more so used more efficiently, the greater the integration density, d. H. the number of memory cells in a given space or a given area. Accordingly, it is a Main goal in the development and manufacture of Memory arrays to increase their integration density.

A typical memory arrangement 301 , as shown in FIG. 3, has a memory cell array 302 and a decoder circuit 307 .

In memory cell array 302 , the data is stored in memory cells 303 as the memory content of memory cells 303 . The decoder circuit 307 serves to select the individual memory cells 303 in order to read out their memory content.

The memory cell array 302 includes a corresponding plurality of memory cells 303, a plurality of mutually parallel word conductive traces 304 and a plurality of the word line webs 304 intersecting perpendicularly and parallel to each other Bitleiterbahnen 305th The memory cells 303 are arranged at the locations of the intersections of the word conductor tracks 304 and the bit conductor tracks 305 . The spacing between adjacent word conductor tracks 304 and the spacing between adjacent bit conductor tracks 305 represent the raster of the memory cell array 302 .

The decoder circuit 307 has a word line decoder 308 and a bit line decoder 311 . Furthermore, the memory arrangement 301 has a read-out output 314 . With the word line decoder 308 , each individual word conductor 304 of the memory cell array 302 can be specifically selected. Likewise, the bit line decoder 311 can be used to selectively select each individual bit conductor path 305 of the memory cell array 302 .

By selecting a predetermined word line 304 and a predetermined bit line 305 , the memory cell 303 at the intersection of the selected word line 304 and the selected bit line 305 is selected and the memory content of this memory cell 303 is applied to the readout output 314 .

The word line decoder 308 includes a plurality of each having a word conductor 304 of the memory cell array 302 electrically coupled to word lines 309 and a plurality of at least one word line 309 electrically coupled to word line address lines (WL address lines) 310th

The bit line decoder 311 includes a plurality of each having a Bitleiterbahn 305 of the memory cell array 302 electrically coupled to bit lines 312 and a plurality of at least one bit line 312 electrically coupled to bit line address lines (BL address lines) 313 on.

For selecting a predetermined word line 309 of a particular word line is applied 309 associated word address "aabbcc" to the word line decoder 308th This is achieved by applying a corresponding word signal a, a, b, b, c and c to each WL address line 310 . The word address "aabbcc" is formed from the totality of the word signals a, a, b, b, c, c applied.

Each word line 309 can be uniquely selected by the associated word address "aabbcc".

To select a predetermined bit line 312 , a bit address "ddeeff" assigned to the specific bit line 312 is applied to the bit line decoder 311 . This is achieved by applying a corresponding bit signal d, d, e, e, f and f to each BL address line 313 . The bit address "ddeeff" is formed by the totality of the applied bit signals d, d, e, e, f, f.

Each bit line 311 can be uniquely selected by the associated bit address "ddeeff".

The word address and the bit address are from a (not shown) control logic supplied.

The WL address line 310 is typically electrically coupled to the word line (s) 309 coupled to it via (each) a transistor. The BL address line 313 is also usually electrically coupled to the bit line (s) 312 coupled to it via (each) a transistor. In this case one speaks of a decoder circuit in transistor logic.

The memory cell array 302 and also the decoder circuit 307 can be implemented, for example, in CMOS technology (Complementary Metal Oxide Semiconductor Technology).

Each memory cell 303 is usually constructed from one (for example in the case of a DRAM, Dynamic Random Access Memory) or several (for example in the case of an SRAM, Static Random Access Memory) transistors.

Advances in semiconductor process technology allow that Manufacturing of memory cell arrays with smaller and smaller ones Grid. Accordingly, the manufacture of semiconductor Storage arrangements with ever higher integration densities possible.

There are also alternative materials to semiconductors: Example organic materials used as raw materials promising for memory cells for high-density memories are. In [1] an organic material is described, the Conductivity by an electric field by a factor of 104 is reversibly changeable. Elements from such organic material could serve as storage cells. In The organic material can, depending on the Electrical field applied either a high or have a low conductivity value and therefore either a logical "1" ("one") or a logical "0" ("zero") be saved.

The organic material described in [1] has a first one Material component made of 3-nitrobenzal-malonitrile molecules (NBMN) and a second material component made of 1.4- Phenylenediamine molecules (pDA). The NBMN molecules and the pDA molecules are conjugated to each other, and one each NBMN molecule and a pDA molecule form in the organic Material a complex. From the organic material produced a 20 nm to 200 nm thick layer. To the An electrical voltage was applied to the layer  to influence the electrical conductivity of the layer. At a 200 nm thick layer was changed by changing the applied voltage by 3.2 V a change in specific electrical conductivity by four Orders of magnitude achieved. The change achieved Conductivity is reversible.

In [1] there is also a comparable effect for others organic materials with a first material component from first molecules and a second material component second molecules described. One is in particular Effect described for such organic materials that a first material component from first molecules and a second material component from second molecules that belong to the first molecules are conjugated, so that each a molecule from the first material component and a molecule a complex from the second material component form.

In [2] is a metal / organic material / metal (MOM) - Heterostructure diode described. With the MOM heterostructure Diode is a monomolecular layer made of an electrical conductive, rectifying organic material between two layers of metal are embedded so that the layer from the rectifying organic material the function of a Diode takes over. The rectifying property of everyone single organic molecule of the organic material attributed to the asymmetric structure of the molecule.

To further increase the integration density not only to shrink the memory cells themselves, but also the electrical leads to the Memory cells, i. H. the word traces and Bit lines.

Electrically conductive carbon nanotubes are known as extremely thin, electrically conductive elements. The diameter of a carbon nanotube can range from 0.2 nanometers to approximately 50 nanometers and is typically 0.7 nanometers to a few nanometers. With carbon nanotubes, for example, a line grid of 10 nm can be realized for the word and bit lines. A memory with 1 cm ² area and such a line grid of 10 nm would then have a capacity of 1 terabit, for example.

So the integration density of a memory arrangement continues can be increased, not only the grid of the Memory cell array can be reduced. Rather, it must the grid for reading out the memory cell array used decoder circuit can be reduced.

With a conventional decoder circuit in transistor logic however, the space requirement is relatively large. Therefore, that can The grid of the decoder circuit is not the same are reduced like the grid of the memory cell array.

A memory cell array with a very small grid can be controlled by gradually adapting the grid of the memory arrangement from the memory cell array to the decoder circuit to the grid of the decoder circuit. This possible solution is illustrated schematically in FIG. 4. FIG. 4 schematically shows three conductor tracks 404 (e.g. word conductor tracks or bit conductor tracks) in a memory arrangement. The conductor tracks 404 extend in a memory cell array 401 , a decoder circuit 403 and a transition region 402 arranged between the memory cell array 401 and the decoder circuit 403 . In the memory cell array 401 , the conductor tracks 404 have a first, smaller grid, in the decoder circuit 403 , the conductor tracks 404 have a second, larger grid. In the transition region 402 , the grid is gradually enlarged from the smaller grid of the memory cell array 401 to the larger grid of the decoder circuit 403 .

The problem underlying the invention is an efficient, simple and compact storage arrangement with high Integration density and a computer with one To create storage arrangement.

In particular, the invention is based on the problem of a to create such a memory array that a Has decoder circuit which decodes a any small grid memory cell array (Memory cell array with a small grid).

The problem is solved by a memory arrangement with the Features according to the independent claim.

The memory arrangement has a memory cell array and one Decoder circuit on.

The memory cell array has a plurality of memory cells on, each a storage element with a changeable Have memory content. The memory content can be changed during the normal operation can be changed, as with a conventional RAM. In this case, in normal operation Reading and writing of the memory cells possible. Alternatively, the memory content can be changed during ordinary Operational be "firm" and during the manufacturing process or in a maintenance operation that is in normal operation is not possible to be changeable, such as. B. in a ROM, PROM, EPROM or EEPROM (ROM = Read Only Memory; PROM = Programmable ROM; EPROM = Erasable PROM; EEPROM = Electrically EPROM). In this case there is only one in normal operation Reading of the memory cells possible, but not one Describe.

The memory cell array also has a plurality of Word traces and a plurality of the word traces crossing bit lines, with the memory cells on  Locations of intersections of word lines and bit lines are arranged.

The decoder circuit is for reading out the memory cells provided and has a word line decoder and one Bit line decoder.

The word line decoder has a plurality of one each Word circuit of the memory cell array electrical coupled word lines and a plurality of with at least a word line electrically coupled word line Address lines (WL address lines). About any WL Address line is a word signal to the with the respective WL address line coupled at least one word line can be created. The WL address line is with the one (s) with it coupled word line (s) (each) via a diode electrically coupled.

The bit line decoder has a plurality of one each Bit line of the memory cell array electrically coupled Bit lines and a plurality of with at least one Bit line electrically coupled bit line address lines (BL address lines). There is one over each BL address line Bit signal to the with the respective BL address line coupled at least one bit line applied. The BL Address line is with the one (s) coupled to it Bit line (s) (each) electrically via a diode coupled.

In addition, the memory arrangement has a readout output Reading out the memory content of each individual memory cell on, by selecting a predetermined word line and a predetermined bit line one of the memory contents reflecting a predetermined single memory cell Output to the readout output.  

To select the predetermined word line, the Word line decoder one of the determined word line assigned word address created. This is done by that a corresponding word signal to each WL address line is created. Through all of the created Word signals, the word address is formed.

Each word line is through the associated word address clearly selectable.

To select the predetermined bit line, the Bit line decoder one assigned to the specific bit line Bit address created. This is caused by each A corresponding bit signal is applied to the BL address line. Due to the totality of the applied bit signals, the bit Address formed.

Each bit line is through the associated bit address clearly selectable.

The word address and the bit address are from a (not shown) control logic supplied.

The use of diodes to couple the WL address lines with the word lines or the BL address lines with the Bit lines allow a particularly compact design for the Storage arrangement and thus enables the production of a particularly efficient memory arrangement with a particularly high integration density.

By using diodes, the (possibly mean) distance between adjacent word lines or Bit lines, hereinafter referred to as the grid of Decoder circuit is called, designed particularly small be. On the one hand, this has the effect that the space requirement is low. On the other hand, even if that Memory cell array has a relatively small grid that  Decoder circuit and the memory cell array the same Have grid. That is, two adjacent word lines of the Decoder circuit can be the same distance as that corresponding two adjacent word traces of the Memory cell array; and / or two adjacent bit lines the decoder circuit can have the same distance as the corresponding two adjacent bit lines of the Memory cell array. This is not a transition area necessary in which the grid of the memory cell array to the Grid of the decoder circuit is approximated. Thus additionally saved space.

Each individual memory cell can be used as a conventional, in CMOS Technique or a similar technique implemented SRAM, Semiconductor-based DRAM or ROM memory cell provided be. A typical such memory cell has at least a transistor.

A structure is preferably provided as the memory cell each at the location of the crossing of a word line a bit line, the word line and the bit line through a memory resistor with a changeable Conductivity are electrically connected. The Conductivity of the memory resistor can be optional at least a first conductivity value and one from first conductivity value different Accept conductivity value. The memory content of the Storage cell is characterized by the conductivity of the storage Resistance determined. So that space is saved, the Memory resistance preferably also mechanical Connection between the bit line and the word line causes. Alternatively, the mechanical connection between the bit line and the word line by one separate element can be effected.  

The memory cell described with the memory resistor as a storage element has the advantage that it takes up space is very low.

Any resistance can be used as a memory resistor be used, the conductivity between a first Conductivity value and a second, from the first Conductivity value different conductivity value is reversibly changeable.

In this case, the first conductivity value is one Memory content "1" of the memory cell, and the second Conductivity value represents a memory state "0" Memory cell, or vice versa. Because of the reversible The conductivity value can be changed Memory content of the memory cell very reliably between "1" and "0" switchable.

Typically, the first conductivity value differs from the second conductivity value by a factor of approximately 10 ⁴ +/- 10 ³ . In this way, the difference between the conductivity value for a logic "0" and the conductivity value for a logic "1" is so great that the risk that a "0" is incorrectly interpreted as a "1" or vice versa is low.

Alternatively, a diode can be used as the memory element will. The memory content can be determined by the orientation the diode must be fixed. For example, one of one Word line to a bit line in reverse direction oriented built-in diode represent a logical "1", and one from a word trace to a bit trace in Forward direction built-in diode a logical "0" represent, or vice versa. Alternatively, the Memory content determined by the threshold voltage of the diode be. The threshold voltage can be determined, for example, by a  determined dopant concentration provided in the diode be fixed.

Alternatively, a memory element can be used as the memory element an organic film can be used which is an organic Has material, the conductivity of the organic Film by applying a suitable electric field the organic film is changeable. The memory content can in this case through the specifically set conductivity of organic film.

In particular, a memory element can be used as the memory element an organic film can be used, the one rectifying organic material. The In this case, memory content can be determined by the orientation of the organic film.

When using an organic film for the Memory element can be a memory element with special small dimensions can be produced. That’s it possible, the integration density of the memory array further to increase.

According to one embodiment of the invention, as Storage element is a film made of an organic material used a first material component from first Molecules and a second material component from the second Has molecules.

In particular, such a film can be used in which the first molecules and the second molecules to each other are conjugated, so that if first molecules and second Molecules are brought into contact, first each Molecule and a second molecule form a complex.

In particular, the first molecules can be 3- nitrobenzal malonitrile molecules (NBMN) and the second molecules can be 1,4-phenylenediamine molecules (pDA). In particular, the organic material described in [1], consisting of 3-nitrobenzal-malonitrile molecules (NBMN) and 1,4-phenylenediamine molecules (pDA), can be used as the organic material.

Alternatively, another suitable organic material can be used for the memory diode. The organic Material is then provided in a suitable form, so that it has the desired conductivity properties. Each by material, the organic material can be a thin film, as a cuboid, as a cylinder or in another form be provided.

Each of the memory cells can have the same design.

Alternatively, at least one memory cell can be one of the above have described designs and at least one Memory cell another of the designs described above have so that memory cells in two or more different designs are provided.

The diodes of the decoder circuit can be conventional diodes, for example, conventional semiconductor diodes. The Semiconductor diodes can be in CMOS technology or one similar technology.

Alternatively, for at least one diode, the diode can at least a diode element made of a rectifying organic Have material.

The word line and the WL address line or the bit line and the BL address line, at the crossing point of which the diode is arranged directly to the diode element be coupled.

Alternatively, on the word line (or bit line) facing end of the diode element and at the WL  Address line (or BL address line) facing end of the Diode element one element or a layer of one electrically conductive material, e.g. B. a metal, be arranged.

The diodes of the decoder circuit can be used in particular as Metal / Organic Material / Metal (MOM) heterostructure diodes are formed, each having at least one first metal layer, one formed on the first metal layer from which rectifying organic material existing organic Layer and one formed on the organic layer have second metal layer. In particular, at Invention of a MOM heterostructure diode like that in [2] described can be used as a diode.

Can be used as a rectifying organic material for the diode any organic material with rectifying electrical properties can be used.

In particular, an organic material can be used in the diode asymmetric electrically conductive molecules used that have a suitable spatial asymmetry, so that they have electrically rectifying properties.

The rectifying organic material in the diode can for example, 4-thioacetylbiphenyl.

Of the rectifying organic material can for the Diode, for example, a plurality of individual asymmetric molecules between the corresponding Word line (or bit line) and the corresponding WL Address line (or BL address line) may be arranged, wherein the individual molecules are aligned parallel to each other, so that the molecules form a monomolecular layer is trained. Each of the individual molecules represents one electrically conductive, rectifying connection between the word line (or bit line) and the WL address line (or BL address line).  

Alternatively, the organic material for the diode uses a single rectifying organic molecule between the word line (or bit line) and the WL address line (or BL address line) is aligned.

The word traces and / or the bit traces of the Memory cell array can be planar conductor tracks and can be made of metal or conductive polysilicon be. The word traces and / or the bit traces can be implemented in a conventional CMOS process be. In particular if the memory cell array is a very has a small grid, the word traces and / or the Bit traces by electron beam lithography or a other raster lithography techniques such as AFM (Atomic force microscope) lithography.

Alternatively, the word traces and / or the Bit traces of the memory cell array made of carbon Nanotubes with metallic conductivity. Are used both for the word traces and for the Bit traces used carbon nanotubes, so can Example of a grid of the memory cell array of 10 nm without more can be realized. This makes it possible to Increase integration density of the memory array further.

The word line decoder and / or the Bit line decoders can be implemented in CMOS technology. Alternatively, the word line decoder and / or the Bit line decoder using a raster lithography technique be made. The word lines and / or the bit lines the decoder circuit can be planar conductor tracks and can be made of metal or conductive polysilicon be.  

Alternatively, the word lines and / or the bit lines the decoder circuit made of carbon nanotubes metallic conductivity. When using of metallically conductive carbon nanotubes as Word lines and / or bit lines is the Integration density of the memory arrangement is particularly high.

The grid of the memory cell array is preferably possible chosen small, the smallest possible grid by the Technology is specified in which the memory cell array is made.

Likewise are the grid of the word line decoder and that Grid of the bit line decoder is preferably as small as possible chosen, the smallest possible grid again by the Technology is specified in which the word or Bit line decoder is manufactured.

The memory cells in the memory cell array are preferred arranged in a grid that has a periodicity of at most 200 nm, preferably at most 100 nm and thereby again preferably has 10 nm.

The memory cells of the memory cell array can be too Memory cell pairs, each with a first memory cell and a second memory cell, the Memory content of the second memory cell equal to the inverse Memory content of the first memory cell is. So if the Memory content of the first memory cell of a logical "1" corresponds, the memory content corresponds to the second Memory cell of a logical "0" and vice versa.

To determine the memory content of a memory cell Memory cell pair are preferably both memory cells read out of the memory cell pair. The read one Memory content of the second memory cell and the inverse of the read memory contents of the first memory cell  compared with each other. If the comparison is none If there is a match, an error handling routine be started. Agreement means that the read memory content of the second memory cell and that Inverse of the read memory content of the first Memory cell is either both logic "1" or both are logical "0". As an error handling routine For example, the readout results are caused discard. Additionally or alternatively, can be arranged that a second read cycle is started in which each of the two memory cells is read out again.

A computer arrangement has: a processor, a Memory arrangement and a control logic for delivering Word signals and bit signals for operating the Storage arrangement. The storage arrangement can, for example according to any of the above Embodiments can be formed. The processor and the Control logic are in a CMOS structure or one of them alternative semiconductor structure, e.g. B. on Compound semiconductor base, implemented. The Memory arrangement is in the CMOS structure or alternative Integrated semiconductor structure.

The integration of the memory arrangement into a conventional one CMOS or alternative structure offers the advantage that the Storage arrangement with little effort in the Computer arrangement can be integrated, so that Computer arrangement with the storage arrangement inexpensive and can be produced efficiently.

Preferably, the CMOS or alternative structure at least two conductive levels, each with conductive Structures based on different conductive levels are predominantly electrically isolated from each other. Are the control logic with the exception of connecting lines on the one hand and the storage arrangement on the other hand in  arranged at different conductive levels. The WL Address lines and the BL address lines of the Storage arrangement are each corresponding to the Connection lines connected to the control logic. The So connecting lines in particular form one electrical connection between different conductive Levels.

The decoder circuit in diode logic offers especially for Storage arrangement with extremely small line grid decisive advantages. By using diodes at of the decoder circuit, the decoder circuit is special compact design. Thus, with the decoder circuit in Diode logic can also be controlled with memory cell fields a conventional decoder circuit no longer controlled can be.

Embodiments of the invention are in the figures are shown and explained in more detail below. Show it:

Fig. 1 is a schematic representation of a preferred embodiment of a memory device according to the invention;

Fig. 2 is a schematic representation of a preferred embodiment of a diode according to the invention with an organic material;

Figure 3 is a schematic representation of a memory device according to the prior art.

Fig. 4 is a schematic representation of three conductor tracks which extend in a memory cell array, a transition region and a decoder circuit; and

Fig. 5 is a partial schematic view of a computer having a memory device according to the invention and a control logic for operating the memory array, according to a preferred embodiment of the invention.

Fig. 1 is a schematic representation showing a preferred embodiment of a storage arrangement 1 according to the invention.

The memory arrangement 1 has a memory cell array 2 and a decoder circuit 7 .

The memory cell array 2 has an arrangement of eight by eight memory cells 3 in a square arrangement, each of which has a memory element 6 with a changeable memory content. As a memory element 6, a 10 nm thick film of an organic material selected from 3-Nitrobenzal- malononitrile molecules (NBMN) and 1,4-phenylenediamine molecules (PDA) is used.

Furthermore, the memory cell array 2 has eight word conductor tracks 4 and eight bit conductor tracks 5 crossing the word conductor tracks 4 , the memory cells 3 being arranged at locations of the intersections of word conductor tracks 4 and bit conductor tracks 5 . A memory cell 3 is arranged at each intersection. Each word line 4 and each bit line 5 is formed from an electrically conductive carbon nanotube. The diameter of each of the nanotubes is approximately 2 nm. Alternatively, another conductive nanotube can be used.

The distance between adjacent word conductor tracks 4 is 10 nm. The distance between adjacent bit conductor tracks 5 is also 10 nm. the grid of the memory cell array 2 is 10 nm.

The decoder circuit 7 is provided for reading out the memory cells 3 and has a word line decoder 8 and a bit line decoder 11 .

The word line decoder 8 has eight word lines 9 . Each of the word lines 9 is electrically coupled to one of the word conductor tracks 4 of the memory cell array 2 . Furthermore, six WL address lines 10 are provided for applying a word address to the word lines 9 . Each WL address line 10 is electrically coupled to four of the eight word lines 9 via a diode 15 . Each WL address line 10 has a different combination of four word lines 9 with which it is electrically coupled. The diode 15 is switched from the WL address line 10 to the word line 9 in the reverse direction. A word signal a, a, b, b, c or c can be applied to each WL address line 10 by a control logic (not shown). Here, a is the word signal inverse to a, b the word signal inverse to b and c the word signal inverse to c. Word signals a, b and c can each have the value of a logic "0" or a logic "1". If a has the value "0", inevitably a has the value "1" and vice versa. The same applies to b, b, c, c. Each sequence of word signals "aabbcc" represents a word address for selecting a predetermined word line 9 from the word lines 9 .

With the arrangement of the diodes 15 in the word line decoder 9 shown in FIG. 1 and the type of control shown with the word signals a, a, b, b, c, c, each word line can be uniquely selected by means of an associated word address "aabbcc".

The bit line decoder 11 has eight bit lines 12 . Each of the bit lines 12 is electrically coupled to one of the bit lines 5 of the memory cell array 2 . Furthermore, six BL address lines 13 are provided for applying a bit signal to the bit lines 12 . Each BL address line 13 is electrically coupled to four of the eight bit lines 12 via a diode 15 . Each BL address line 13 has a different combination of four bit lines 12 with which it is electrically coupled. The diode 15 is switched from the BL address line 13 to the bit line 12 in the reverse direction. A bit signal d, d, e, e, f and f can be applied to each BL address line 13 by a control logic (not shown). Here d is inverse to d, e inverse to e and f inverse to f. Each bit signal d, e and f can have the value of a logic "0" or a logic "1". Each sequence of bit signals "ddeeff" represents a bit address for selecting a predetermined bit line 9 from the bit lines 9 .

With the arrangement of the diodes 15 shown in FIG. 1 in the bit line decoder 11 and the type of control shown with the bit signals d, d, e, e, f, f, each bit line can be uniquely selected by an associated bit address "ddeeff".

In addition, the memory arrangement 1 has a read-out output 14 for reading out the memory content of each individual memory cell 3 , an output V _out reflecting the memory content of a predetermined individual memory cell 3 being output to the read- _out output 14 by the selection of a predetermined word line 9 and a predetermined bit line 12 .

Furthermore, each word line 9 is electrically coupled to a supply voltage source V _DD via an associated resistor R ₁ .

Each bit line 12 is connected to the readout output 14 via an associated readout diode 16 . The readout diode 16 is switched from the bit line 12 to the readout output 14 in the forward direction. The readout output 14 is electrically coupled to the inverting input 20 of an operational amplifier 19 . The output 21 of the operational amplifier 19 is electrically coupled to the inverting input 20 via a feedback resistor R ₂ .

Adjacent word lines 9 have a spacing of 10 nm, that is to say the same spacing as neighboring word conductor tracks 4 of the memory cell array 2 .

Adjacent bit lines 12 have a spacing of 10 nm, that is to say the same spacing as neighboring bit conductor tracks 5 of the memory cell array 2 .

Adjacent WL address lines 10 and adjacent BL address lines 13 are each at a mutual distance of 180 nm.

The mode of operation of the memory arrangement 1 according to the preferred embodiment of the invention described above with reference to FIG. 1 is described below.

For each memory cell 3 , the memory _content can alternatively have two different memory values, R _z1 and R _z2 .

A word signal a, a, b, b, c and c is applied to each of the word lines 9 . In addition, the supply voltage V _{DD is} applied to each of the word lines 9 via the associated resistor R ₁ .

If the value of the word signal in a specific WL address line 10 corresponds to a logic "1", all four diodes which are electrically coupled to the specific WL address line 10 are electrically conductive. As a result, in the four word lines 9 , which are each coupled to the particular WL address line 10 with one of the four diodes 15 , the supply voltage V _DD drops in each case via the diode 15 . Correspondingly, the four word lines 9 are at the potential U ₀ , U _{0 being} the forward voltage of the respective diode 15 . The four word lines are thereby defined as not selected.

If, on the other hand, the value of the word signal in a specific WL address line 10 corresponds to a logic “0”, all four diodes which are electrically coupled to the specific WL address line 10 are electrically blocked. As a result, no voltage drops across the respective diode 15 in the four word lines 9 , which are each coupled to one of the four diodes 15 to the specific WL address line 10 .

However, the supply voltage V _DD is only present on a single word line 9 if all three diodes 15 , which are electrically coupled to the word line 9 , are blocked.

Each word address of the form "aabbcc" defines exactly one word line 9 in which all three diodes 15 are blocked. The supply voltage V _DD (minus losses) is maintained on this word line 9 . This word line 9 is the selected word line.

Corresponding considerations as set out above for the word line decoder 8 apply to the bit line decoder 11 .

Correspondingly, exactly seven bit lines 12 are connected to the forward voltage U ₀ by the diodes 15 through each bit address of the form "ddeeff", while exactly one bit line 12 is connected to the forward voltage U by the operational amplifier 19 , the feedback resistor R ₂ and a readout diode 16 _{0 is} placed. This exactly one bit line 12 is the selected bit line.

The operational amplifier 19 supplies an output voltage V _out <0 at its output 21. As can be shown, the value of the output voltage V _out reflects the memory _content R _z1 or R _{z2 of} the selected memory cell 3 .

In a further preferred embodiment of the memory arrangement, the memory is operated in such a way that two adjacent memory cells 3, as a pair of memory cells, form a memory location for storing a bit of data. In this case, inverted memory values are stored in the two memory cells 3 of a single pair of memory cells. I.e. in the other memory cell 3 of the memory cell pair is stored _z1 (z. B. "0") in the one memory cell 3 of the memory cell pair, the storage value R, then the memory value R _z2 (z. B. "1") are stored, and vice versa.

In this further preferred embodiment, the relationship between V _out and the memory content can be represented relatively easily.

The number of bit lines is equal to n. The total resistance R _{zp of} the parallel connection of the memory resistances of all n memory cells 3 in a single word line 9 is the same, regardless of the memory contents stored in the memory cells 3

R _zp = (R _z1 ^-1 + R _z2 ^-1 ) ^-1 .2 / n (1)

The current flowing in the selected word line current I _tot 9 is thus equal to

I _tot = (V _DD - U ₀ ) / (R ₁ + R _zp ) (2)

Consequently, the selected word line 9 is at the potential

U _WL = V _DD - R ₁ (V _DD - U ₀ ) / (R ₁ + R _zp ) = = (R _zp V _DD + R ₁ U ₀ ) / (R ₁ + R _zp ) (3)

R _z0 is now the resistance value of the selected memory cell 3 . A current thus flows through the memory element 6 of the selected memory cell 3

I _out = (U _WL - U ₀ ) / R _z0 (4)

The magnitude of the output voltage V _out at the output 21 of the operational amplifier 19 is thus obtained

| V _out | = R ₂ (U _WL - U ₀ ) / R _z0 = = R ₂ R _zp (V _DD - U ₀ ) / [R _z0 (R ₁ + R _zp )] (5)

The desired resistance value R _{z0 of} the selected memory cell 3 can thus be determined by measuring V _out .

If the memory content of an individual memory cell 3 is read out, it is preferred that the memory content of the second memory cell 3 of the corresponding memory cell pair is also read out.

In the preferred method for reading out a memory arrangement 1 , the memory content of the first memory cell 3 is read out. As a result, a first analog read-out value V _{out is} supplied, from which a read-out first memory content (= read-out memory content of the first memory cell 3 ) is determined. In addition, the memory content of the second memory cell is read out. As a result, a second analog read-out value V _{out is} supplied, from which a read-out second memory content (= read-out memory content of the second memory cell 3 ) is determined. The read memory content is either "0" or "1". The read-out first memory content is compared with the inverse of the read-out second memory content. If it is determined during the comparison that the read-out first memory content does not match the inverse of the read-out second memory content, there could be a readout error and an error handling routine is initiated.

For example, in the error handling routine Error messages are issued by a user informs you that there is an error.

Alternatively, the memory content of the first memory cell 3 can be read out again in the error handling routine, as a result of which a new first analog read value V _{out is} supplied, from which a newly read first memory content (= read memory content of the first memory cell 3 when read again) is determined and can the memory content of the second memory cell can be read out again, whereby a second analog readout value V _{out is} supplied, from which a second memory content read out again (= read memory content of the second memory cell 3 when read out again) is determined.

If read again in the error handling routine the read out can be made in any case Memory contents from the first reading are discarded and the re-read memory content from the new one Readout can continue to be used.

Alternatively, for the first memory content and the second Memory content according to a certain weighing criterion be determined that either the read Memory content or the re-read memory content is discarded. As a weighing criterion, for example Criterion to be used in which is weighed which Selection result, that from the first reading or that from reading again, appears more credible.

For example, the read or re-read memory content is defined as logical "0" if the analog or renewed analog read- _out value V _out is smaller than a predetermined threshold value V _th . The read or the newly read memory content, on the other hand, is defined as logic "1" if the analog or renewed analog read value V _out is greater in amount than the predetermined threshold value V _th .

In this case, for example, the read-out memory content can be discarded if the new analog read-out value V _{out has} a greater distance from the predetermined threshold value V _th than the analog read-out value V _out , and the reread read-out memory content can be discarded if the new analog read-out value V _{out has} a smaller distance from the predetermined threshold value V _th than the analog readout value V _out .

With the read- _out value V _out , which has a smaller distance from the threshold value V _th , the probability is higher that the definition of the memory content based on the read-out value V _out as "0" or "1" is incorrect and therefore the read-out memory content is not correct with the actual one Memory content matches.

As an alternative to discarding either the memory content read out or the memory content read out again, an average value from the analog value | V _out | for the read-out memory content and the analog value | V _out | for the re-read memory content. If the mean is greater than the predetermined threshold V _th , the memory _content is defined as a logic "1". If the mean is less than the predetermined threshold V _th , the memory _content is defined as a logic "0".

The decoder circuit 7 can be manufactured as follows. A layer of the organic material is provided in the entire area of the word line decoder 8 and the bit line decoder 11 . The layer is structured in such a way that the layer remains at locations where a diode 15 is to be present and the layer is destroyed at the other locations. The structuring can be carried out, for example, using electron beam lithography. Alternatively, a self-organizing process can be used, in which the organic material automatically arranges itself only at the locations where a diode 15 is to be provided. Alternatively, a combination of structuring at desired locations and self-organized processing can be used, the self-organizing processes taking place at selected locations and prepared by structuring.

In an alternative preferred embodiment of the memory arrangement according to the invention, 1024 × 1024 memory cells are arranged to form a memory cell array. Correspondingly, there are 1024 word conductor tracks, 1024 bit conductor tracks, 1024 word lines and 1024 bit lines in the memory arrangement, each of which has a grid of 10 nm. The word line decoder in this case has 20 WL address lines and the bit line decoder has 20 BL address lines. The WL address lines and the BL address lines each have a raster of 200 nm. In this embodiment, the memory cell array has an area of approximately 10 μm × 10 μm, and the word line decoder and the bit line decoder each have an area of approximately 4 μm × 10 µm.

In further alternative preferred embodiments of the memory arrangement according to the invention, 2 ⁿ (2 high n) word conductor tracks, bit conductor tracks, word lines and bit lines and 2 ⁿ × 2 ⁿ memory cells are provided; in such a case, the word line decoder has 2 n (2 times n) WL address lines and the bit line decoder has 2n (2 times n) BL address lines. Here n is a non-negative integer (n = 0, 1, 2, 3,...).

In the embodiment described above with 1024 × 1024 Memory cells and 20 word / BL address lines, for example is n = 10.

The larger the integer n, the greater the difference between the number 2 ⁿ of word lines (corresponding to word lines 9 in FIG. 1) etc. (see above) on the one hand and the number 2 n of WL address lines (corresponding the WL address lines 10 in FIG. 1) or BL address lines on the other hand.

Therefore, the invention offers in particular Storage devices with a large storage capacity, i. H. with a large number of memory cells, crucial Advantages.

A computer arrangement according to the invention has: a processor, a memory arrangement 1 and a control logic for supplying word signals and bit signals for operating the memory arrangement. For example, the memory array may be configured in accordance with any of the embodiments described above. The processor and the control logic are in a CMOS structure or an alternative semiconductor structure, e.g. B. implemented on a compound semiconductor basis. The memory arrangement is integrated in the CMOS structure or alternative semiconductor structure.

Fig. 5 is a partial schematic view showing a computer with a memory device according to the invention and a control logic for operating the memory array, according to a preferred embodiment of the invention.

In this preferred embodiment of the computer, the CMOS-like structure has a first conductive level 501 with conductive structures and a second conductive level 502 with conductive structures. The first conductive level 501 and the second conductive level 502 are predominantly electrically insulated from one another. The control logic 503, with the exception of connecting lines 504, is arranged in the first conductive level 501 . The WL address lines 10 of the memory arrangement are arranged in the second conductive level 502 . Fig. 5 shows two WL address lines 10. Each of the WL address lines 10 of the memory arrangement 1 is connected to the control logic 503 by a corresponding one of the connecting lines 504 . In Fig. 5 a connection line 504 is illustrated. The BL address lines 13 are preferably arranged in a third conductive level, which is different from the first conductive level 501 and from the second conductive level 502 (not shown in FIG. 5), and each of the BL address lines 13 of the memory arrangement 1 connected to the control logic 503 by a corresponding one of the connecting lines 504 (not shown in FIG. 5). The connecting lines 504 thus form in particular an electrical connection between the first conductive level 501 and the second conductive level 502 .

The term "conductive level" is to be understood such that in the "conductive level" layer-like electrically conductive Structures are formed. The term is not too understand that the "conductive level" consistently of one electrically conductive material is formed. Between different conductive levels are on the one hand arranged electrically insulating materials, for example Oxides and / or nitrides and / or glasses, and on the other hand Connection lines (e.g. so-called "vias"), by means of which different conductive levels with each other electrically are coupled.

A memory arrangement 1 itself typically has at least two conductive memory levels. For example, the word conductor tracks 4 , the word lines 9 and the bit line (BL) address lines 13 are arranged in a first conductive memory layer and the bit conductor tracks 5 , the bit lines 12 and the word line (WL) are arranged in a second conductive memory layer. - Address lines 10 arranged. Memory resistors used as memory elements 6 of the individual memory cells 3 represent conductive connections between the first conductive memory level and the second conductive memory level. In the word line decoder 8 and in the bit line decoder 11 , the diodes 15 provide conductive connections between the first conductive memory level and the second conductive memory level.

The following publications are cited in this document:
[1] HJ Gao et al., Phys. Rev. Lett. 84, 1780 ( 2000 )
[2] C. Zhou et al., Appl. Phys. Lett. 71, 611 ( 1997 )

Reference symbol list

Fig.

1

1

Storage arrangement

2nd

Memory cell array

3rd

Memory cell

4th

Word trace

5

Bit line

6

Storage element

7

Decoder circuit

8th

Word line decoder

9

Word line

10th

WL address line

11

Bit line decoder

12th

Bit line

13

BL address line

14

Readout output

15

diode

16

Readout diode

17th

-

18th

-

19th

Operational amplifier

20th

inverting input of the operational amplifier

21st

Output of the operational amplifier

Fig.

2nd

201

first layer of metal

202

organic layer

203

second metal layer

Fig.

3rd

301

Storage arrangement

302

Memory cell array

303

Memory cell

304

Word trace

305

Bit line

306

-

307

Decoder circuit

308

Word line decoder

309

Word line

310

WL address line

311

Bit line decoder

312

Bit line

313

BL address line

314

Readout output

Fig.

4th

401

Memory cell array

402

Transition area

403

Decoder circuit

404

Conductor track

Fig.

5

501

first conductive level

502

second conductive level

503

Control logic

504

Connecting line

Claims (17)

1. Storage arrangement ( 1 ) with
a memory cell array ( 2 ) with a plurality of memory cells ( 3 ), each having a memory element ( 6 ) with a memory content, with a plurality of word conductor tracks ( 4 ) and with a plurality of bit conductor tracks ( 5 ) crossing the word conductor tracks, the memory cells ( 3 ) are arranged at locations of the intersections of word conductor tracks ( 4 ) and bit conductor tracks ( 5 ), and
a decoder circuit ( 7 ) for reading out the memory cells ( 3 )
a word line decoder ( 8 ) which has a plurality of word lines ( 9 ) which are electrically coupled to one word line ( 4 ) and a plurality of WL address lines ( 10 ) which are electrically coupled to at least one word line ( 9 ), via which a word signal is applied the at least one word line ( 9 ) coupled to the WL address line ( 10 ) can be applied, the WL address line ( 10 ) and the word line ( 9 ) being electrically coupled to one another via a diode ( 15 ),
a bit line decoder ( 11 ) which has a plurality of bit lines ( 12 ) which are electrically coupled to a bit line ( 5 ) and a plurality of BL address lines ( 13 ) which are electrically coupled to at least one bit line ( 12 ), each of which receives a bit signal the at least one bit line ( 9 ) coupled to the BL address line ( 13 ) can be applied, the BL address line ( 13 ) and the bit line ( 12 ) being electrically coupled to one another via a diode ( 15 ), and
a readout output ( 14 ) for reading out the memory content of each individual memory cell ( 3 ), an output to the readout output ( 14 ) reflecting the memory content of a predetermined individual memory cell ( 3 ) being selected by the selection of a predetermined word line ( 9 ) and a predetermined bit line ( 12 ) ) can be output. 2. Memory arrangement ( 1 ) according to claim 1, in which a memory resistor with a variable conductivity is used for the memory element ( 6 ), through which memory resistor the word conductor path ( 4 ) and the bit conductor path ( 5 ) are connected to one another, wherein the conductivity of the storage resistor can optionally take at least a first conductivity value and a conductivity value different from the first conductivity value. 3. Storage arrangement ( 1 ) according to claim 1 or 2, in which an organic film is used as the storage element ( 6 ), which has an organic material, wherein the conductivity of the organic film can be changed by applying a suitable electric field to the organic film. 4. Memory arrangement ( 1 ) according to one of claims 1 to 3, in which at least one memory cell ( 3 ) has at least one transistor. 5. Memory arrangement ( 1 ) according to one of claims 1 to 4, in which for at least one diode ( 15 ) the diode ( 15 ) has at least one diode element made of a rectifying organic material. 6. The memory arrangement ( 1 ) according to claim 5, wherein the rectifying organic material comprises 4-thioacetylbiphenyl. 7. Memory arrangement ( 1 ) according to one of claims 1 to 6, in which the word conductor tracks ( 4 ) and / or the bit conductor tracks ( 5 ) are made of carbon nanotubes with metallic conductivity. 8. Memory arrangement ( 1 ) according to one of claims 1 to 7, in which the word lines ( 9 ) and / or the bit lines ( 12 ) are made of carbon nanotubes with metallic conductivity. 9. Memory arrangement ( 1 ) according to one of claims 1 to 8, in which the memory cells ( 3 ) are arranged to form memory cell pairs, each with a first memory cell ( 3 ) and a second memory cell ( 3 ), the memory content of the second memory cell ( 3 ) is equal to the inverse memory content of the first memory cell ( 3 ). 10. A method for reading out a memory arrangement ( 1 ) according to claim 9,
in which
the memory content of the first memory cell ( 3 ) is read out, whereby a first analog read-out value is supplied, from which a read-out first memory content is determined,
the memory content of the second memory cell ( 3 ) is read out, as a result of which a second analog readout value is supplied, from which a read second memory content is determined, and
the read-out first memory content is compared with the inverse of the read-out second memory content and, if it is determined during the comparison that the read-out first memory content does not match the inverse of the read-out second memory content, an error handling routine is initiated. 11. The method according to claim 10, where in the error handling routine a Error message is issued.   12. The method of claim 10 or 11, wherein in the error handling routine, the memory content of the first memory cell ( 3 ) is read again, whereby a new first analog read value is supplied, from which a newly read first memory content is determined, and the memory content of the second Memory cell ( 3 ) is read out again, whereby a second analog readout value is supplied, from which a second memory content read out is determined. 13. The method according to claim 12, in the case of the error handling routine for the first Memory content and the second memory content according to one Weighing criterion is determined that either the read memory content or the reread Memory content is discarded. 14. The method according to claim 13, in which the read or the reread Memory content is defined as logical "0" when the analog or renewed analog readout value according to the amount is less than a predetermined threshold, and at which the memory content read or reread is defined as logical "1" if the analog or renewed analog readout value is greater than the predetermined threshold. 15. The method according to claim 14, where the read memory content is discarded, if the renewed analog read-out value has a larger distance of the predetermined threshold than the analog one Readout value, and at which the reread Memory content is discarded if the new analog Read out a smaller distance from the predetermined one Has threshold value as the analog readout value.   16. Computer arrangement with
a processor,
a memory arrangement ( 1 ) according to one of claims 1 to 9 and
a control logic ( 503 ) for supplying word signals and bit signals for operating the memory arrangement ( 1 ),
wherein the processor and the control logic ( 503 ) are implemented in a CMOS structure or an alternative semiconductor structure and the memory arrangement ( 1 ) is integrated in the CMOS or alternative structure. 17. The computer arrangement as claimed in claim 16, in which the CMOS or alternative structure has at least two conductive levels ( 501 , 502 ) each having conductive structures, the first conductive level ( 501 ) and the second conductive level ( 502 ) being predominantly electrically insulated from one another the control logic ( 503 ) with the exception of connecting lines ( 504 ) and the memory arrangement ( 1 ) are arranged in different conductive levels ( 501 , 502 ), the WL address lines ( 10 ) and the BL address lines ( 13 ) each are connected to the control logic ( 503 ) by means of corresponding connecting lines ( 504 ).