DE10103546A1 - Method for controlling a peripheral device by means of a central device and devices for using the method - Google Patents

Abstract

The invention relates to a method for controlling a peripheral device using a central device and also to apparatuses for carrying out the method, where the method involves using a communication bus to transfer control information in the form of a data word containing an associated address statement from the central device to the peripheral device. In the method, to change control bits in the peripheral device, the control information is used to stipulate which at least one of the control bits is set or reset and which at least one of the control bits needs to be left unchanged, the control bits being changed by means of at least one write operation.

Description

The invention is in the field of data exchange between devices of integrated circuit arrangements, especially the control of a peripheral device, for example, a host peripheral device a central facility.

State of the art

Integrated circuit arrangements such as central devices often use so-called host interfaces to control and to modify operations in the integrated Circuit arrangement on a host peripheral device access. As a rule, within the scope of access Control words read from the host peripheral, after a transmission via the host interface to the integrated circuit arrangement in this changed in the changed form via the host interface to the host Peripheral device passed, and into the host device written. Since the frequency at which host Peripheral devices are usually clocked, often less than the clock frequency of the integrated Circuitry is, make the requests of the integrated circuitry on the host device a limit on the working speed of the integrated Circuit arrangement as a whole.

A known host interface is partially shown in FIG . Components which are provided only once in the host interface are shown in FIG. 2 on the left side of a chain line. On the right-hand side of the chain line, components are shown that are present in the host interface for each address, which can be accessed in the host peripheral device by means of the integrated circuit arrangement (central device).

In the host peripheral device, the information which the integrated circuit arrangement can access via the host interface is stored in registers or memory cells, only one register cell 1 being shown in FIG. 2 to simplify the description. Usually eight, sixteen, thirty-two or more register cells are assigned to an address word. The information is stored in the register cell 1 in that the address belonging to the register is applied to an address input 2 and is decoded in the host interface by means of an address decoder 3 . In connection with a write signal which is generated via an OR gate 4 and a NOT OR gate 9 , the writing of the register cell 1 is made possible. When the write signal is activated, data which are present at a data input 5 are transferred into the register cell 1 .

Register cell 1 is still connected to a clock input 6 .

In order to read the information from the register, the address belonging to the register is also applied to address input 2 and decoded by means of address encoder 3 . The decoded address is combined with a read signal generated via a further OR gate 7 and a NOT OR gate 1 C. As a result, a first three-state component 11 is released so that the information can be read from the register cell 1 and sent to an internal communication bus. Another three-state component 8 also ensures that the information read from the register cell 1 can be read out via the data line 5 .

The described reading method and the described writing method are used to read or write complete control words which are stored in the registers of the host peripheral device. After reading a control word, this is transferred to the integrated circuit arrangement, which is connected to the host interface and accesses the host peripheral device, in order to change one or more control bits in the control word. The control word changed in this case is then transferred from the integrated circuit arrangement to the host peripheral device in which the register is located. In the host peripheral device, the changed control word is then written into register cell 1 and further register cells corresponding to the bit width of the register (not shown in FIG. 2). In this case, the control word is always read completely from the registers of the host peripheral device, transferred to the integrated circuit arrangement, changed in the integrated circuit arrangement and then completely returned to the host peripheral device for writing. This means that the integrated circuit arrangement is dependent on the operating frequency of the peripheral device.

invention

The object of the invention is to provide an improved method for Controlling a peripheral device using a Central facility and a device for using the To create a process that the dependence of Central facility when performing operations from the Performance of the peripheral device reduced.

According to the invention, the object is achieved by a method claim 1, a peripheral device according to the  Claim 9 and a central device according to the Claim 14 solved.

The essential idea of the invention lies in particular based on a to the peripheral device Submit tax information specifying which Control bits set in the peripheral device, reset or should be left unchanged. The Control information is then in the peripheral device implemented by means of a write operation in which Control bits set or reset or unchanged be left. With the new process it is therefore in Not necessary compared to the state of the art, all Read control bits from the peripheral device to which Central device to transmit and control bits after a change in the central facility again everyone to transmit the peripheral device and there write. This way the burden of a Communication bus reduces the data over which between the central device and the peripheral device be replaced.

In total, the number of accesses of the Central device on the peripheral device by means of new procedure reduced. This can Real-time applications in the central facility more efficiently work.

In addition, compared to the prior art Advantage that no loss of information can occur like him in the known method between reading and writing the control bits can occur. Especially when using it a dynamic register, for example one Interrupt register, can be between reading and Write information (bits) will be lost since the Control bits completely between the central facility and the peripheral device must be transmitted several times.  

For easy control of the write operation in the Peripheral device sees appropriate further training the invention that with the help of a Peripheral device transmitted set / reset information it is determined whether the at least one write operation as a set-write operation, which the setting of the at least comprises a control bit to be set, or as one Reset write operation is performed that the Resetting the at least one control bit to be reset includes. That in today's integrated circuits in large Number of available address and data bits used only to a small extent, so with the help this development of the invention is a simple one Control possibility is created that the existing Hardware uses without the additional connections provided Need to become.

The control information may be preferred Embodiment of the invention with regard to the required Time requirements are transmitted efficiently that the Control information as a parallel information stream is transmitted.

The lines used to carry out the process or connections can be advantageous Embodiment of the invention can be minimized in that the control information as a serial information stream is transmitted.

Another reduction in the execution of the Process lines or connections required can an appropriate embodiment of the invention be achieved that the set / reset information series is transmitted serially with the control information.  

The parallel transmission of the set / reset information and implement the control information in a simple manner can see a preferred development of the invention that the set / reset information about a set / Reset information line and the control information on a data input line can be transmitted in parallel.

The transmission of the set / reset information is at one expedient embodiment of the invention thereby with the help simple control commands possible that the setting / Reset information line a set line via which the set information for specifying the set write operation, and includes a reset line through which the Reset information for setting the reset Write operation is transferred.

The transfer of the full information content of the Control information in the registers or storage devices the peripheral device is preferred. Training of the invention achieved in that the at least one write operation at least one write includes one of the control bits to be left unchanged.

The under the dependent device claims disclosed developments of the invention have the in Connection with associated procedural claims listed Advantages accordingly.

drawings

The invention is based on Exemplary embodiments with reference to drawings explained.

Show it:

Figure 1 is a schematic representation of portions of a host interface between a central device and a peripheral device.

Fig. 2 is a schematic representation of a known host interface between a central device and a peripheral device;

Fig. 3 is a schematic diagram showing the order of transmission of information in a host interface;

FIG. 4 shows a schematic illustration in which, in comparison to FIG. 3, set / reset information is integrated in the sequence of the information;

Fig. 5 is a schematic diagram showing the order of transmission of information in another host interface;

FIG. 6 shows a schematic illustration, a set / reset information being integrated in the order of the information in comparison to FIG. 5; and

FIG. 7 shows a schematic illustration, the set / reset information being at least partially transmitted serially in comparison to FIG. 6.

embodiments

Fig. 1 is a diagram showing an interface between a central device and a peripheral device, which is preferably a host-peripheral device. The illustration shows the structure of the interface as an example for a register cell 20 connected to a clock input 19 . Components that can be used in connection with the reading and / or writing of several register cells or registers are shown on the left side of a chain line. The components 21 , 22 , 23 , 24 , 37 must be provided for each register cell in accordance with the register width, while the further components 19 , 25-29 , 32-34 need only be provided once per peripheral device. Components which are provided for the register cell 20 and for each further register cell (not shown) in the peripheral device are shown in FIG. 1 on the right side of the chain line.

If one or more control bits in the peripheral device are to be changed in the course of an operation of the central device which provides for the inclusion of the peripheral device, control information is transmitted from the central device to the peripheral device via the interface. In this context, a data word bit comprised by the control information is applied to a data input 21 . If the data bus width relates to 16 bits, for example, 16 data inputs 21 (not shown) are provided. The data word specifies which control bits of a control word stored in the registers of the peripheral device are to be set and which control bits of the control word are to be left unchanged. This determination is made by setting the control bits to be set to one and the control bits not to be changed to zero in the data word. In another case, the data word present can be used to determine which of the control bits are to be reset and which of the control bits are to be left unchanged. In this case, the control bits to be reset are set to one and the control bits to be left unchanged are set to zero.

A multiplexer device 22 is connected to the data input 21 , in particular via an OR gate 23 and an AND gate 24 . The OR gate 23 is used in connection with the setting of control bits, whereas the AND gate 24 is used in connection with the resetting of control bits. In addition, the multiplexer device 22 is connected to a set line 25 and a reset line 26 . The output of the multiplexer device 22 is coupled to the data input of the register cell 20 and, in the event that the peripheral device has a plurality of registers, is connected to the corresponding register cells of these registers. This is indicated in FIG. 1 by further connecting lines shown in broken lines. The enable signal ENA for the individual register cell ensures that only the addressed register cell is ever written.

As is known from the host interface described at the beginning in connection with FIG. 2 (cf. gate 4 and further gate 7 in FIG. 1), a write or read signal is generated via gates 27 , 35 and further gates 28 , 36 1, with the aid of the arrangement shown in FIG. 1 it is possible to carry out the change of control bits in the registers, for example the register cell 20 in the peripheral device by means of an exclusive write operation.

If control bits are to be set using the write operation, the data word is first applied to the data inputs 21 , the control bits to be set being set to one and the control bits to be left unchanged being set to zero. In addition to the data word, address information associated with the data word is applied to the address inputs 29 and is decoded with the aid of an address decoder 30 . The control information which is transmitted via the interface in the course of the access of the central device to the peripheral device thus includes the data word and the associated address information. In the event that the address bus has a width of 16 bits, 16 address inputs 29 are provided (not shown).

To change the control bits, the setting of which is determined by means of the data word bit applied to the data input 21 , the set line 25 is set to one by means of set information generated by the central device, and the reset line 26 is set to zero on the same side. The OR gate 23 sets the associated bit via the multiplexer device 22 , the setting of which was defined in the data word bit at the data input 21 . Via a three-state gate 31 , the information about the state of the control bits to be left unchanged is fed back in such a way that, in the context of such a set / write operation in which the fixed control bits are set, the control bits to be left unchanged are also set as defined in the data word the data input 21 are overwritten, the state of which is not changed. As a note it is mentioned that the further three-state gate 37 remains blocked in this phase, so that no conflict can arise between the level present at data input 21 and the state stored in the register cell.

If a data word is present at the data inputs, in which it is determined which of the control bits in the peripheral device are to be reset and which of the control bits are to be left unchanged, the write operation for making these changes, which can be referred to as a reset-write operation, is thereby initiated. that the reset line 26 is set to one by means of reset information and at the same time the set line 25 is set to zero. With the inclusion of the AND gates 24 , the control bits to be reset and the control bits to be left unchanged are then written, the information about the state of the control bits to be left unchanged for writing being fed back again using the three-state gate 31 .

The multiplexer device 22 is set with the aid of the set information obtained via the set line 25 and with the aid of the reset information received via the reset line 26 , which ensures the setting via the OR gate 23 or the reset via the AND gate 24 , Additional gates 32 , 33 , 34 , 36 enable the tri-state gate 31 to be released during the set / reset write operation to change the control bits.

According to the method described in connection with FIG. 1, the data word and the set / reset information are transmitted in parallel via the data input 21 or the set / reset line 25 , 26 . However, the new method can also be used in connection with interfaces that use serial transmission, for example via an I2C bus. The advantages resulting from the method are even greater in this case because the serial data transmission takes place more slowly and therefore the reading out from the peripheral unit, transferring to the central unit, changing, retransferring and writing to the peripheral unit, which is necessary according to the known solution, takes longer and therefore more time can be saved.

The sequence of the information to be transmitted in connection with an I2C interface is shown schematically in FIG. 3. After start information 40 , address information 41 is transmitted. After read / write information 42 , data 43 are transmitted, with an acknowledgment signal 44 being transmitted in each case.

FIG. 4 shows how set / reset information 45 can be inserted into the information stream according to FIG. 3, by means of which it is determined in the peripheral device whether the write operation to be carried out to change the control bits is carried out as a set write operation or as a reset write operation ,

FIG. 5 schematically shows the sequence of a known information flow similar to the representation in FIG. 3, with information about a subaddress 46 also being inserted. In comparison to the known information stream in FIG. 5, the information about the subaddress 46 in the illustration shown in FIG. 6 has been supplemented by the set / reset information 45 . If the sub-address e.g. B. 6 bits required, the two remaining bits in the 8-bit word can be used for the set / reset information.

However, as is shown schematically in FIG. 7, it is also possible to transmit the information about the subaddress 46 and the set / reset information 45 one after the other and in separate fields.

Claims (14)

1. A method for controlling a peripheral device by means of a central device, in which control information is transferred as a data word with a corresponding address from the central device to the peripheral device via a communication bus, characterized in that the control information is used to change control bits in the peripheral device. which at least one of the control bits is set or reset and which at least one of the control bits is to be left unchanged, the changing of the control bits being carried out by means of at least one write operation. 2. The method according to claim 1, characterized in that with the help of a peripheral device transmitted set / reset information is set, whether the at least one write operation as a set Write operation, which is the setting of the at least one control bits to be set, or as a reset Write operation is performed that will reset the comprises at least one control bit to be reset. 3. The method according to claim 1 or 2, characterized characterized in that the control information as a parallel Stream of information is transmitted. 4. The method according to claim 1 or 2, characterized characterized in that the control information as serial Information stream is transmitted and before application in the peripheral device converted serial / parallel becomes.   5. The method according to any one of the preceding claims, characterized in that the set / reset information mation transmitted serially with the control information becomes. 6. The method according to any one of claims 1 to 5, characterized in that the set / reset information via a set / reset information line ( 25 , 26 ) and the control information via a data input line ( 21 ) are transmitted in parallel. 7. The method according to claim 6, characterized in that the set / reset information line ( 25 , 26 ) comprises a set line ( 25 ) over which the set information for setting the set-write operation is transmitted, and a reset line ( 26 ) over which the reset information for specifying the reset write operation is transmitted. 8. The method according to any one of the preceding claims, characterized in that the at least one Write operation a writing of the at least one of the control bits to be left unchanged. 9. Peripheral device that can be used when executing a method according to one of claims 1 to 8, with:
Processing means ( 23 , 24 , 22 , 30 ) for the electronic processing of control information received as a data word with an associated address, such that for changing control bits in the peripheral device it can be electronically detected from the received control information which at least one of the control bits in the peripheral device should be set or reset and which at least one of the control bits in the peripheral device should be left unchanged; and
Write means ( 27 , 35 , 22 ) for performing at least one write operation, which comprises setting the at least one control bit to be set or resetting the at least one control bit to be reset. 10. Peripheral device according to claim 9, characterized in that the processing means comprise connection means ( 25 , 26 ) for receiving set / reset information, the connection means being connected to set / reset information line means, and in that the received set / reset information using the Processing means ( 22 ) can be processed such that the write operation is determined depending on the received and processed set / reset information as a set-write operation which comprises the setting of the at least one control bit to be set, or as a reset-write operation, which comprises resetting the at least one control bit to be reset. 11. Peripheral device according to claim 10, characterized characterized in that the set / reset information line means a set line connection and a Have reset line connection, each with the Processing means are connected. 12. Peripheral device according to one of claims 9 to 11, characterized by feedback means ( 31 ) which are connected to the writing means ( 27 , 35 , 22 ), so that information on the writing means ( 27 , 35 , 22 ) for the writing operation at least one of the control bits to be left unchanged can be made available. 13. Peripheral device according to one of claims 9 to 12, characterized in that the processing means ( 23 , 24 , 22 , 30 ) comprise a multiplexer device ( 22 ). 14. Central device that can be used when executing a method according to one of claims 1 to 8, in particular in connection with a peripheral device according to one of claims 9 to 13, with:
Generating means for generating control information such that, in order to change control bits in a peripheral device, the control information can be used to determine which at least one of the control bits is set or reset and which at least one of the control bits is to be left unchanged; and
a connection for a communication bus, so that the control information can be transmitted via the communication bus as a data word with an associated address to the peripheral device.