DE10085375T1 - Verfahren und Einrichtung für einen pipeline-verschachtelten Multi-Thread-Befehlsdecodierer - Google Patents
Verfahren und Einrichtung für einen pipeline-verschachtelten Multi-Thread-BefehlsdecodiererInfo
- Publication number
- DE10085375T1 DE10085375T1 DE10085375T DE10085375T DE10085375T1 DE 10085375 T1 DE10085375 T1 DE 10085375T1 DE 10085375 T DE10085375 T DE 10085375T DE 10085375 T DE10085375 T DE 10085375T DE 10085375 T1 DE10085375 T1 DE 10085375T1
- Authority
- DE
- Germany
- Prior art keywords
- instruction decoder
- thread instruction
- nested multi
- pipeline
- pipeline nested
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/475,105 | 1999-12-30 | ||
US09/475,105 US6609193B1 (en) | 1999-12-30 | 1999-12-30 | Method and apparatus for multi-thread pipelined instruction decoder |
PCT/US2000/041927 WO2001050249A2 (en) | 1999-12-30 | 2000-11-06 | Method and apparatus for multi-thread pipelined instruction decoder |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10085375T1 true DE10085375T1 (de) | 2002-12-05 |
DE10085375B4 DE10085375B4 (de) | 2007-01-25 |
Family
ID=23886242
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10085375T Expired - Fee Related DE10085375B4 (de) | 1999-12-30 | 2000-11-06 | Verfahren und Einrichtung für einen pipeline-verschachtelten Multi-Thread-Befehlsdecodierer |
Country Status (8)
Country | Link |
---|---|
US (2) | US6609193B1 (de) |
CN (2) | CN100361073C (de) |
AU (1) | AU4302801A (de) |
DE (1) | DE10085375B4 (de) |
GB (1) | GB2374177B (de) |
HK (1) | HK1046970B (de) |
TW (1) | TW497072B (de) |
WO (1) | WO2001050249A2 (de) |
Families Citing this family (70)
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FR2728559B1 (fr) * | 1994-12-23 | 1997-01-31 | Saint Gobain Vitrage | Substrats en verre revetus d'un empilement de couches minces a proprietes de reflexion dans l'infrarouge et/ou dans le domaine du rayonnement solaire |
US6845445B2 (en) * | 2000-05-12 | 2005-01-18 | Pts Corporation | Methods and apparatus for power control in a scalable array of processor elements |
US6754808B1 (en) * | 2000-09-29 | 2004-06-22 | Intel Corporation | Valid bit generation and tracking in a pipelined processor |
JP3607209B2 (ja) * | 2001-03-08 | 2005-01-05 | 松下電器産業株式会社 | クロック制御方法及び当該クロック制御方法を用いた情報処理装置 |
WO2002077799A1 (en) * | 2001-03-22 | 2002-10-03 | Infineon Technologies Ag | Program-controlled unit employing a stop instruction |
US20030120896A1 (en) * | 2001-06-29 | 2003-06-26 | Jason Gosior | System on chip architecture |
JP3564445B2 (ja) * | 2001-09-20 | 2004-09-08 | 松下電器産業株式会社 | プロセッサ、コンパイル装置及びコンパイル方法 |
US20040025012A1 (en) * | 2002-07-30 | 2004-02-05 | Burks David Patrick | System for processing coded content and associated decoding instructions on a removable storage medium |
WO2004049152A1 (en) * | 2002-11-26 | 2004-06-10 | Mplicity Ltd. | A processor capable of multi-threaded execution of a plurality of instruction-sets |
US7496921B2 (en) * | 2003-08-29 | 2009-02-24 | Intel Corporation | Processing block with integrated light weight multi-threading support |
US7263599B2 (en) * | 2004-02-06 | 2007-08-28 | Infineon Technologies | Thread ID in a multithreaded processor |
US7418582B1 (en) | 2004-05-13 | 2008-08-26 | Sun Microsystems, Inc. | Versatile register file design for a multi-threaded processor utilizing different modes and register windows |
US20060009265A1 (en) * | 2004-06-30 | 2006-01-12 | Clapper Edward O | Communication blackout feature |
US7290116B1 (en) | 2004-06-30 | 2007-10-30 | Sun Microsystems, Inc. | Level 2 cache index hashing to avoid hot spots |
US7519796B1 (en) | 2004-06-30 | 2009-04-14 | Sun Microsystems, Inc. | Efficient utilization of a store buffer using counters |
US7509484B1 (en) | 2004-06-30 | 2009-03-24 | Sun Microsystems, Inc. | Handling cache misses by selectively flushing the pipeline |
US7366829B1 (en) | 2004-06-30 | 2008-04-29 | Sun Microsystems, Inc. | TLB tag parity checking without CAM read |
US7543132B1 (en) | 2004-06-30 | 2009-06-02 | Sun Microsystems, Inc. | Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes |
US7523330B2 (en) * | 2004-06-30 | 2009-04-21 | Sun Microsystems, Inc. | Thread-based clock enabling in a multi-threaded processor |
US7571284B1 (en) | 2004-06-30 | 2009-08-04 | Sun Microsystems, Inc. | Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor |
US7890735B2 (en) * | 2004-08-30 | 2011-02-15 | Texas Instruments Incorporated | Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture |
US8756605B2 (en) * | 2004-12-17 | 2014-06-17 | Oracle America, Inc. | Method and apparatus for scheduling multiple threads for execution in a shared microprocessor pipeline |
US7430643B2 (en) * | 2004-12-30 | 2008-09-30 | Sun Microsystems, Inc. | Multiple contexts for efficient use of translation lookaside buffer |
US7934079B2 (en) | 2005-01-13 | 2011-04-26 | Nxp B.V. | Processor and its instruction issue method |
JP4749431B2 (ja) * | 2005-03-04 | 2011-08-17 | ヒューレット−パッカード デベロップメント カンパニー エル.ピー. | パイプラインスループットを促進するための方法及び装置 |
US8195922B2 (en) | 2005-03-18 | 2012-06-05 | Marvell World Trade, Ltd. | System for dynamically allocating processing time to multiple threads |
US20060212853A1 (en) * | 2005-03-18 | 2006-09-21 | Marvell World Trade Ltd. | Real-time control apparatus having a multi-thread processor |
US7987342B1 (en) | 2005-09-28 | 2011-07-26 | Oracle America, Inc. | Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer |
US8015359B1 (en) | 2005-09-28 | 2011-09-06 | Oracle America, Inc. | Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit |
US7849292B1 (en) | 2005-09-28 | 2010-12-07 | Oracle America, Inc. | Flag optimization of a trace |
US7953961B1 (en) | 2005-09-28 | 2011-05-31 | Oracle America, Inc. | Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder |
US7966479B1 (en) | 2005-09-28 | 2011-06-21 | Oracle America, Inc. | Concurrent vs. low power branch prediction |
US8499293B1 (en) | 2005-09-28 | 2013-07-30 | Oracle America, Inc. | Symbolic renaming optimization of a trace |
US8051247B1 (en) | 2005-09-28 | 2011-11-01 | Oracle America, Inc. | Trace based deallocation of entries in a versioning cache circuit |
US7937564B1 (en) | 2005-09-28 | 2011-05-03 | Oracle America, Inc. | Emit vector optimization of a trace |
US7953933B1 (en) | 2005-09-28 | 2011-05-31 | Oracle America, Inc. | Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit |
US7949854B1 (en) | 2005-09-28 | 2011-05-24 | Oracle America, Inc. | Trace unit with a trace builder |
US7783863B1 (en) | 2005-09-28 | 2010-08-24 | Oracle America, Inc. | Graceful degradation in a trace-based processor |
US7877630B1 (en) | 2005-09-28 | 2011-01-25 | Oracle America, Inc. | Trace based rollback of a speculatively updated cache |
US8032710B1 (en) | 2005-09-28 | 2011-10-04 | Oracle America, Inc. | System and method for ensuring coherency in trace execution |
US8037285B1 (en) | 2005-09-28 | 2011-10-11 | Oracle America, Inc. | Trace unit |
US8370576B1 (en) | 2005-09-28 | 2013-02-05 | Oracle America, Inc. | Cache rollback acceleration via a bank based versioning cache ciruit |
US8024522B1 (en) | 2005-09-28 | 2011-09-20 | Oracle America, Inc. | Memory ordering queue/versioning cache circuit |
US8019944B1 (en) | 2005-09-28 | 2011-09-13 | Oracle America, Inc. | Checking for a memory ordering violation after a speculative cache write |
US7870369B1 (en) | 2005-09-28 | 2011-01-11 | Oracle America, Inc. | Abort prioritization in a trace-based processor |
US7676634B1 (en) | 2005-09-28 | 2010-03-09 | Sun Microsystems, Inc. | Selective trace cache invalidation for self-modifying code via memory aging |
US7814298B1 (en) | 2005-09-28 | 2010-10-12 | Oracle America, Inc. | Promoting and appending traces in an instruction processing circuit based upon a bias value |
US20070101102A1 (en) * | 2005-10-27 | 2007-05-03 | Dierks Herman D Jr | Selectively pausing a software thread |
US7797517B1 (en) | 2005-11-18 | 2010-09-14 | Oracle America, Inc. | Trace optimization via fusing operations of a target architecture operation set |
US7444499B2 (en) * | 2006-03-28 | 2008-10-28 | Sun Microsystems, Inc. | Method and system for trace generation using memory index hashing |
US8010745B1 (en) | 2006-09-27 | 2011-08-30 | Oracle America, Inc. | Rolling back a speculative update of a non-modifiable cache line |
US8370609B1 (en) | 2006-09-27 | 2013-02-05 | Oracle America, Inc. | Data cache rollbacks for failed speculative traces with memory operations |
US8402253B2 (en) | 2006-09-29 | 2013-03-19 | Intel Corporation | Managing multiple threads in a single pipeline |
US7975272B2 (en) | 2006-12-30 | 2011-07-05 | Intel Corporation | Thread queuing method and apparatus |
EP2159701A4 (de) * | 2007-06-19 | 2011-08-10 | Fujitsu Ltd | Cache-steuereinrichtung und cache-steuerverfahren |
JP5168277B2 (ja) * | 2007-06-20 | 2013-03-21 | 富士通株式会社 | 命令制御装置及び制御方法 |
US20090044159A1 (en) * | 2007-08-08 | 2009-02-12 | Mplicity Ltd. | False path handling |
US9035957B1 (en) * | 2007-08-15 | 2015-05-19 | Nvidia Corporation | Pipeline debug statistics system and method |
US8868888B2 (en) * | 2007-09-06 | 2014-10-21 | Qualcomm Incorporated | System and method of executing instructions in a multi-stage data processing pipeline |
CN101425053B (zh) * | 2007-11-02 | 2010-08-18 | 北京中电华大电子设计有限责任公司 | 一种cpu周期寄存器的实现方法 |
US8543796B2 (en) | 2008-11-05 | 2013-09-24 | Intel Corporation | Optimizing performance of instructions based on sequence detection or information associated with the instructions |
US9710277B2 (en) * | 2010-09-24 | 2017-07-18 | Intel Corporation | Processor power management based on class and content of instructions |
US9710275B2 (en) | 2012-11-05 | 2017-07-18 | Nvidia Corporation | System and method for allocating memory of differing properties to shared data objects |
US9417880B2 (en) | 2013-03-15 | 2016-08-16 | Intel Corporation | Instruction for performing an overload check |
CN105263023B (zh) * | 2015-10-26 | 2018-08-03 | 西安电子科技大学 | 基于高速解码平台的网络码流实时接收方法 |
CN105654383B (zh) * | 2016-01-07 | 2019-12-10 | 中国科学院信息工程研究所 | 基于流水线架构的低时延fast行情解码装置和方法 |
US10325341B2 (en) | 2017-04-21 | 2019-06-18 | Intel Corporation | Handling pipeline submissions across many compute units |
US10269088B2 (en) * | 2017-04-21 | 2019-04-23 | Intel Corporation | Dynamic thread execution arbitration |
WO2020009989A1 (en) | 2018-07-05 | 2020-01-09 | Mythic, Inc. | Systems and methods for implementing an intelligence processing computing architecture |
US10891995B2 (en) * | 2019-01-15 | 2021-01-12 | SK Hynix Inc. | Command generation method and semiconductor device related to the command generation method |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5539911A (en) | 1991-07-08 | 1996-07-23 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
US5357617A (en) * | 1991-11-22 | 1994-10-18 | International Business Machines Corporation | Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor |
US5983339A (en) | 1995-08-21 | 1999-11-09 | International Business Machines Corporation | Power down system and method for pipelined logic functions |
US5778246A (en) * | 1995-12-27 | 1998-07-07 | Intel Corporation | Method and apparatus for efficient propagation of attribute bits in an instruction decode pipeline |
US6026476A (en) | 1996-03-19 | 2000-02-15 | Intel Corporation | Fast fully associative translation lookaside buffer |
US5890008A (en) | 1997-06-25 | 1999-03-30 | Sun Microsystems, Inc. | Method for dynamically reconfiguring a processor |
US5913049A (en) | 1997-07-31 | 1999-06-15 | Texas Instruments Incorporated | Multi-stream complex instruction set microprocessor |
US6385719B1 (en) * | 1999-06-30 | 2002-05-07 | International Business Machines Corporation | Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor |
US6357016B1 (en) * | 1999-12-09 | 2002-03-12 | Intel Corporation | Method and apparatus for disabling a clock signal within a multithreaded processor |
US6594755B1 (en) * | 2000-01-04 | 2003-07-15 | National Semiconductor Corporation | System and method for interleaved execution of multiple independent threads |
US6754808B1 (en) * | 2000-09-29 | 2004-06-22 | Intel Corporation | Valid bit generation and tracking in a pipelined processor |
-
1999
- 1999-12-30 US US09/475,105 patent/US6609193B1/en not_active Expired - Fee Related
-
2000
- 2000-11-06 DE DE10085375T patent/DE10085375B4/de not_active Expired - Fee Related
- 2000-11-06 WO PCT/US2000/041927 patent/WO2001050249A2/en active Application Filing
- 2000-11-06 CN CNB2005100926862A patent/CN100361073C/zh not_active Expired - Fee Related
- 2000-11-06 CN CNB008192596A patent/CN1222868C/zh not_active Expired - Fee Related
- 2000-11-06 AU AU43028/01A patent/AU4302801A/en not_active Abandoned
- 2000-11-06 GB GB0214930A patent/GB2374177B/en not_active Expired - Fee Related
- 2000-12-12 TW TW089126479A patent/TW497072B/zh not_active IP Right Cessation
-
2002
- 2002-11-20 HK HK02108397.0A patent/HK1046970B/zh not_active IP Right Cessation
-
2003
- 2003-07-08 US US10/615,918 patent/US6931516B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20040107336A1 (en) | 2004-06-03 |
US6931516B2 (en) | 2005-08-16 |
CN1222868C (zh) | 2005-10-12 |
WO2001050249A3 (en) | 2002-05-02 |
HK1046970B (zh) | 2004-12-31 |
GB2374177B (en) | 2004-07-07 |
DE10085375B4 (de) | 2007-01-25 |
CN1725176A (zh) | 2006-01-25 |
TW497072B (en) | 2002-08-01 |
AU4302801A (en) | 2001-07-16 |
GB2374177A (en) | 2002-10-09 |
WO2001050249A2 (en) | 2001-07-12 |
US6609193B1 (en) | 2003-08-19 |
WO2001050249A9 (en) | 2002-08-01 |
HK1046970A1 (en) | 2003-01-30 |
GB0214930D0 (en) | 2002-08-07 |
CN1437725A (zh) | 2003-08-20 |
CN100361073C (zh) | 2008-01-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8364 | No opposition during term of opposition | ||
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |
Effective date: 20140603 |