DE10060060A1 - Device for converting MPEG-2 transport signals into video signal has logic that uses commonalities between transport stream and video interfaces to produce additional signals - Google Patents

Abstract

The conversion device contains logic (2) that uses the commonalities between a transport stream interface and a video interface to produce additional signal field select or vertical sync signals required for the conversion from a packet sync-signal and a clock signal present at the inputs of a counter.

Description

The invention relates to a device for converting MPEG-2 transport stream signals into a format that largely resembles a video signal according to CCIR 656 , in particular for devices for video processing.

MPEG-2 encoded signals are becoming increasingly important as in digital TV or with the DVD.

On the other hand, there is a great need for MPEG-2 signals to process in various ways.

It is essential that a suitable input interface with sufficient Data bandwidth and high cost efficiency is available.

State of the art are special solutions for transport stream processing on the one and elaborate adaptation facilities on the other.

Special solutions offer an interface for transport flows, but are open a special application tailored and therefore not universally applicable. Adaptation devices for other interfaces are usually right complex and cost-intensive.

The invention has for its object to show a device that Disadvantages of known devices eliminated and conversion of MPEG-2 Transport stream signals in a format that is already available in a variety of ways Video processing equipment (DSP, PC video processing, multimedia PCI Bridges) can be processed.

According to the invention, this is achieved in that the field select or vertical sync signals additionally required for conversion by logic, taking advantage of the common features of a transport stream interface and a video interface, of a packet sync signal present at one input of a counter and a clock signal present at the other input be generated. The counter consists on the one hand of a toggle flip-flop chain with a downstream D flip-flop, for converting the packet sync signal present at one input into a field select signal and on the other hand of an XOR gate, two D flip-flop s and four subordinate NAND gates, for converting the clock signal present at the other input into a vertical sync signal. By gradual division into powers of two of the packet sync signals down via the toggle flip-flop chain, the output signal at the end of the toggle flip-flop chain with a D flip-flop again with the packet If the sync signal is synchronized, a field select signal is present at the video interface at the output of the counter's D flip-flop. A D flip-flop, coupled to an XOR gate, always generates a signal when the field select signal has a high or low edge, which by clocking with the byte clock lasts a byte clock period and by a subordinate one D flip-flop is delayed by a further clock and a subsequent circuit consisting of four NAND gates, depending on the status of the field select signal, either switches through a delayed or a non-delayed signal and thus after every 2 ^L-1 horizontal Sync signals or packets or lines a vertical sync signal is present at the output of the counter at the video editing system.

This conversion has the advantage that there is no intermediate buffer for those to be transferred Transport stream data is required for the field mechanism to Realization of double buffering is used and that a variety of Video processing equipment as transport stream processing equipment can be used.

The invention will be explained in more detail using an exemplary embodiment.

In the accompanying drawings:

Fig. 1 is a simplified block diagram for the format conversion,

Fig. 2 is a block diagram of the logic,

Fig. 3 shows the time course of the signals to the transport stream interface,

Fig. 4 shows the time course of the signals to the video interface according to CCIR 656,

Fig. 5 shows the timing of sync signals,

Fig. 6 shows a circuit of the counter Fig. 1 shows a simplified block diagram for the format conversion, consisting of a transport stream source 1, a logic unit 2 and a video input 3.

As can be seen from FIG. 2 in connection with FIGS. 3 and 4, both the transport stream interface 4 and the CCIR 656 video interface 5 are synchronous clocked interfaces with 8 data signals D0. , .D7 and a clock signal CLK. So 1 byte per clock cycle is transmitted.

While the transport stream interface 4 uses a packet sync signal P-SYNC, which marks the start of a packet, the video interface 5 uses a horizontal sync signal H-SYNC according to CCIR 656 , which marks the start of a video line. The transport stream interface 4 uses a data enable signal DEN which identifies the valid data byte and distinguishes the 188 useful bytes of the transport stream packet from the parity bytes which are not to be transmitted.

At the video interface 5, this signal corresponds to the pixel qualifier signal PXQ, which also identifies the valid and to be transmitted data bytes. The optional error signal ERR has no equivalent on the video interface 5 . Referring to FIG. 2, the corresponding signals are directly connected. This ensures that each transport stream packet is interpreted by the video interface 5 as a video line with 94 pixels (at 2 bytes per pixel in 4: 2: 2 format). The beginning of the packet is reliably recognized and the parity bytes are automatically hidden.

The advantage here is that there is no buffer for transport stream data is required. The error signal ERR is not processed. The transport stream offers the possibility to set an error flag within the data, so that this signal can be dispensed with.

So that the video interface 5 can work properly, a vertical sync signal V-SYNC is required, which indicates the beginning of a video field and with the aid of which a certain number of packets or lines are combined to form a field (corresponds to one field).

For this purpose, a counter 6 is used according to FIG. 2, which generates a field select signal FS or a vertical sync signal V-SYNC from the packet sync signal P-SYNC and the clock signal CLK.

The circuit structure for generating a field select signal FS is shown in the upper part of the circuit of the counter 6 according to FIG. 6. The logic circuit then divides the packet sync signal P-SYNC stepwise into powers of 2 via a toggle flip-flop chain 7 down. At the end of the toggle flip-flop chain 7 , the output signal is synchronized again with the packet sync signal P-SYNC using a D flip-flop 8 . This is necessary because the divider cascade causes a significant delay that depends on the length of the cascade. A field select signal FS is present at the output of the D flip-flop 8 , which changes the level with a cascade length of L toggle flip-flops after every 2 UI horizontal sync signals H-SYNC. This simple circuit is sufficient for video processing devices whose interface can process such field select signals FS. It is advantageous that plate cascades ("ripple counters") are available as standard ICs.

The circuit structure for generating a vertical sync signal V-SYNC required by the video processing device shows the lower part of the circuit of the counter 6 according to FIG. 6. Then the D flip-flop 11 , coupled to an XOR gate 9 , generates a signal whenever the field select signal FS has a high or low edge. Due to the clocking with the byte clock, this signal lasts for one byte clock period. The downstream D flip-flop 12 delays the signal by a further clock. The subsequent circuit, which is composed of 4 NAND gates 10 , switches through either a delayed or a non-delayed signal to the Vertical Sync V-SYNC output, depending on the status of the field select signal FS. A vertical sync signal V-SYNC is thus generated after every 2 ^L-1 horizontal sync signals H-SYNC or packets or lines. The video processing device can distinguish the (video) fields on the basis of the different alternating phase position of the vertical sync signal V-SYNC. This means that the video interface 5 always understands N = 2 ^L-1 packets between 2 V-SYNC events as a video field (field). However, the counter 6 must alternately generate two different V-SYNC pulses according to N and 2N packets so that two fields or fields can be distinguished.

This offers another advantage. Double buffering is automatically implemented by the field mechanism. While a field with N packets is being transferred into the input buffer of the video interface 5 , the previously transferred field can also be processed with N transport stream packets by the following processing stage without inconsistencies in the data. In addition, the processor can usually be automatically informed of the arrival of a field.

FIG. 5 shows two variants of the pulse sequence for generating the vertical sync signal V-SYNC and the field select signal FS by the counter 6. The first variant is a vertical sync signal V-SYNC, which is used by many video interfaces. A V-SYNC PULSE is generated after every N H-SYNC pulses. These pulses are output alternately in phase and not in phase with the horizontal sync signal H-SYNC. This makes it possible to distinguish between the two video fields. The second variant uses a field select signal FS as a replacement for the vertical sync signal V-SYNC to identify the video fields (fields). The field select signal FS simply changes the state after every N H-SYNC pulses. The video interface 5 reacts to both level changes and simply recognizes the field from the state of the signal.

An application example for the invention is the use of a DSP Video processing as a transport stream processor. The video input format of the DSPs is set to 94 pixels per line in 4: 2: 2 format and to 256 lines per field (512 Lines per picture).

Two buffers with 48128 bytes each (188.256) are created for the fields. The divider is designed so that it has a field select signal FS with N = 256 generated. This can be done very easily with a binary counter.

As a result, 256 transport stream packets are sequentially divided into the two Input buffer transferred. After each "field" an interrupt is sent to the DSP Posted. This can now access the 256 packets in the input buffer and process these while the other input buffer with 256 further packets is described.  

Reference symbols used

1

Transport power source

2

logic

3

Video Input

4

Transport Stream Interface

5

Video Interface

6

counter

7

Toggle flip-flop chain

8th

D flip-flop

9

XOR gate

10

NAND gate

11

D flip-flop

12

D flip-flop
CLK clock signal
D0. , .D7 data signal
P-SYNC packet sync signal
THE Data Enable signal
H-Sync Horizontal Sync signal
V-Sync Vertical Sync Signal
PXY pixel qualifier signal
FS Field Select signal
ERR error signal

Claims (4)

1. Device for converting MPEG-2 transport stream signals into a format that largely resembles a video signal according to CCIR 656 , in particular for devices for video processing, characterized in that additionally required signals Field Select (FS) or Vertical Sync (V-SYNC ) by logic ( 2 ), taking advantage of the common features of a transport stream interface ( 4 ) and a video interface ( 5 ), consisting of a packet sync signal (P-SYNC) present at one input of a counter ( 6 ) and one present at the other input Clock signal (CLK) are generated. 2. Device according to claim 1, characterized in that the counter ( 6 ) on the one hand from a toggle flip-flop chain ( 7 ) with a downstream D flip-flop ( 8 ), for converting the pending at the one input Packet sync signal (P-SYNC) in a field select signal (FS), and on the other hand consists of an XOR gate ( 9 ), two D flip-flop s ( 11 , 12 ) and four subordinate NAND Gates ( 10 ) for converting the clock signal (CLK) present at the other input into a vertical sync signal (V-SYNC). 3. Device according to claim 1 and 2, characterized in that a gradual division into powers of two of the packet sync signal (P-sync) via the toggle flip-flop chain ( 7 ) takes place downwards, at the end the toggle flip-flop chain ( 7 ) output signal is synchronized with a D flip flop ( 8 ) again with the packet sync signal (P sync), so that at the output of the D flip flop ( 8 ) of the counter ( 6 ) a field select signal (FS) is present at the video interface ( 5 ). 4. Device according to claims 1-3, characterized in that a D flip-flop ( 11 ), coupled with an XOR gate ( 9 ), always generates a signal when the field select signal (FS) is high or has a low edge, which lasts one byte clock period due to the clocking with the byte clock and is delayed by a further clock by a downstream D flip-flop ( 12 ) and a subsequent one consisting of four NAND gates ( 10 ) Circuit, depending on the status of the Field Select signal (FS), switches through either a delayed or a non-delayed signal and thus a vertical sync signal after every 2 ^L-1 horizontal sync signals (H-SYNC) or packets or lines (V-SYNC) is present at the output of the counter ( 6 ) on the video interface ( 5 ).