DE4309343C1 - Switching output clock signal between two async. input pulse signals - switching between input clock signals triggered by switching signal sync. with rising edge of output signal - Google Patents

Abstract

The clock switching method switches between two asynchronous input clock signals (AC, BC). Switching between clock signals is triggered by a switching signal (C) which is synchronous with the rising edge of the actual output clock signal (RC). A hold state of the output signal corresponding to a logical "1" state follows the rising edge of the clock. The hold state is cancelled on the first rising edge of the input clock signal which is being switched through. ADVANTAGE - Requires only one signal for switching between input clock signals.

Description

The invention relates to a method for switching the output clock signal a switching device between the two mutually asynchronous on gang clock signals of this switching device.

Becomes a logic device or a microprocessor with an output clock a switching device operated, at the inputs of two to each other asynchronous input clock signals are present, so when switching, caused by the constantly changing phase between the two Input clock signals, conditions occur in the output clock signal disruptive to the operation of the logic arrangement or the microprocessor Act. Especially when caused by switching in the output clock signal pulses occur with a duration that is in the range of the Logic circuit or the microprocessor predetermined minimum low or High dwell times, or shortfalls, can be unpredictable Logic arrangement or microprocessor reactions occur. At such short pulses may be part of the logic or micro processor that is less than the dwell time specified in the specifications he needs to respond to the impulse while other parts don't react because their minimum dwell time has not been reached.

From US 4,229,699 a switching device of an output clock signal known between two or more input clock signals, in which one The minimum dwell time of the state log. "1" as follows is avoided. The changeover is triggered by a set signal pulse a rising edge of the output clock signal begins. over this set signal pulse is a counter to a predetermined delay time and the output clock signal for this delay time on one Stop state with log. "1" held. The selection of after the delay time applied clock signal is carried out by a selection signal indicating its state changes during the set signal pulse.  

The disadvantage of this switching device is that it has a rising edge of the output clock signal beginning set signal pulse by him triggered hold state "1" the duration of the log. State "0" shortens that to Switching two signals are required, which are against each other in a be agreed timing must be, and that it is the set signal impulse is an impulse, the duration of which does not depend on the adjacent Output clock signal can be derived.

It is therefore an object of the invention to provide a method by which the Switching takes place so that the minimum dwell time of both signal states is not undercut and only a signal for switching is required.

The invention solves this problem in that with a predetermined ten, d. H. with the rising or falling clock edge of the current output clock signal of the switching device synchronously generated switching signal Switchover and a logical state following this clock edge corresponding, d. H. when switching is initiated by the increasing clock edge the state log. "1" and when switching is initiated by the falling clock edge the state log. "0", hold state of the output clock signal is initiated, and this hold state due to the first on the order circuit following rising or falling clock edge of the input clock i gnals that has been switched to is canceled.

With the synchronize to the output clock signal and thus to an input clock Switchover signal is also the switchover in synchronism with this input clock initiated and until the same clock edge arrives (rising or falling) of the other input clock signal, the output clock signal is on one fixed value, which is then also by the other input clock signal to the next (falling or rising) clock edge is maintained.

In an advantageous development of the invention, the switching signal with the first rising or falling edge following the switchover of the output clock signal reset. The switching process takes place with this a defined degree.  

Short pulses that indicate the operation of logic operated by the output clock signal circuit or a microprocessor can not interfere occur.

An embodiment of a circuit arrangement for performing the The invention is explained in more detail below with reference to the drawings. In this demonstrate:

Fig. 1 is a circuit diagram of a switching device,

Fig. 2 is a state diagram for a switching process of a Schaltungsanord voltage of FIG. 1.

Fig. 1 shows a circuit diagram of a switching device 20 , in which the output of a first switch 22 , at whose inputs the input clock signals AC, BC supplied via input terminals 24 , 26 are connected to the first input of an OR circuit 28 , the output of which is connected the output clock signal RC delivers and the second input of which is connected to the output of an AND circuit ( 30 ), the first input of which has the inverting output Qn of a first D flip-flop 32 and the second input of which has an input terminal 34 which is connected to the switchover signal C, which is also connected to the data input D of the first D flip-flop. The switchover signal C is generated by a logic circuit 50 , which is only shown as a block and is synchronized by the output clock signal RC.

The clock input of the first D flip-flop 32 is connected to the output of a second switch 36 , at whose inputs the two input clock signals AC, BC are also present and that of the inverting output Qn of a second D flip-flop 38 is controlled, whose data input D is connected to the non-inverting output Q of a third D flip-flop 40 and whose clock input, like that of the third D flip-flop 40 , is connected to the output of the AND circuit 30 , wherein the inverting output Q of the third flip-flop 40 is connected to the data input D of this D flip-flop 40 and a control input of the first switch 22 .

The function of the circuit arrangement in FIG. 1 is described in more detail below with reference to the state diagram of FIG. 2, the signal emitted by the inverting output Qn of the first D flip-flop 32 with CDn, the output signal of the first switch 36 with CC, the output signal of the second D flip-flop 38 with SCn, the output signal of the non-inverting output of the third D flip-flop with SR, the output signal of the invert the output of the third D flip-flop are denoted by SRn and the output signal of the AND circuit 30 by H. The signal throughput time of D flip-flops, AND / OR circuits, switches and logic circuit 50 was assumed to simplify the illustration with the same, not to scale, value.

Up to the time t1, the input clock AC is switched through as the output clock signal RC of the switching device 20 . Logic circuit 50 generates a switchover signal C in synchronism with rising edge a of the output clock signal (step 1). Due to the AND operation with the output signal CDn of the first D flip-flop 32 , the signal H changes from log. "0" on log. "1" (step 2). By ORing this signal H with the output signal AB of the first switch 22 , the output clock signal RC, regardless of the state of the output signal AB, to log. "1" switched.

With the rising edge of the signal H, the output signal SRn of the D flip-flop 40 changes its state of log. "1" on log. "0" (step 3) and thus switches the output of the switch 22 with the input clock signal BC (step 4).

With this switchover rising clock edge b of the clock signal CC, which corresponds to the input clock signal BC at this point in time, the switching signal C present at the data input D of the flip-flop 32 is adopted (step 5) and the signal H at the output the AND link 30 changes back to log. "0" (step 6). The state of the output clock signal RC is again determined by the state of the output clock signal of the changeover switch 22 and thus of the input clock signal BC. The falling edge of the signal H causes the D flip-flop 38 to take over the state of the D flip-flop 40 (step 7) and the switch 36 which is present at the clock input of the D flip-flop 32 Clock signal CC changes from an input clock signal BC to the input clock signal AC (step 8) and thus prepares the next switchover signal that follows.

If the changeover signal C is withdrawn with the next rising edge (c) of the output clock signal RC (step 9), the D flip-flop 32 is also brought into its idle state again with the subsequent rising edge of CC, thus completing the changeover process is.

This circuit arrangement according to FIG. 1 can also be easily modified by slight changes in the components used so that the steps described above are initiated by falling edges, and the state of the output clock is not at log. "0" but on log. "1" is held.

Claims (4)

1. Method for switching an output clock signal (RC) between two mutually asynchronous input clock signals (AC, BC), in which with one for the rising clock edge (a) of the current output clock i gnals (RC) synchronously generated switching signal (C) the switching as well a logic state "1" following the rising clock edge corresponding hold state (HOLD) of the output clock signal (RC) is initiated, and in which this hold state (HOLD) due to the first the rising clock edge (b) of the input following the switchover clock signal (AC, BC) that has been switched to is canceled. 2. Method for switching an output clock signal (RC) between two asynchronous input clock signals (AC, BC), with which a falling clock edge of the current output clock signal (RC) synchronously generated changeover signal (C) the changeover as well as the on the falling clock edge following logical state "0" corresponding Hold state (HOLD) of the output clock signal (RC) is initiated, and at which this hold state (HOLD) due to the first switchover following falling clock edge of the input clock signal (AC, BC), on the has been switched over, is canceled. 3. The method according to claim 1 or 2, characterized in that the Changeover signal (C) with the first step following the changeover Returning or falling edge of the output clock signal (RC) is set. 4. Circuit arrangement for performing the method according to claim 1, characterized in that the output of a first switch ( 22 ), at the inputs of which are applied via input terminals ( 24 , 26 ) A input clock signals (AC, BC), with the first input one first logic circuit ( 28 ) is connected, the output of which provides the output clock signal (RC) and the second input of which is connected to the output of a second logic circuit ( 30 ), the first input of which is connected to an output (Qn) of a first flip-flop ( 32 ) and the second input of which is connected to an input terminal ( 34 ) at which the switchover signal (C) is applied, which is also connected to a data input (D) of the first flip-flop ( 32 ), the clock input of which Output of a second switch ( 36 ) is connected, at the inputs of which the two input clock signals (AC, BC) are also present and which is signaled by an output (Qn) of a second flip-flop ( 38 ) is euert, whose data input (D) to a first output (Q) of a third flip-flop's (40) is connected and whose clock input as that of the third flip-flop's (40) to the output of the second logic circuit (30 ) is connected, a second output (Q) of the third flip-flop ( 40 ) being connected to the data input (D) of this flip-flop ( 40 ) and a control input of the first switch ( 22 ).