DE10053671A1 - Self adjusting process for forming field effect transistors comprises a multiple step process in which a low ohmic connection metallization is finally applied to the source, drain and gate - Google Patents

Abstract

Self adjusting process for forming field effect transistors comprises establishing the outer limit of a source and drain region on a substrate (1) using mesa etching, by depositing a dielectric layer (2) and self-adjusting removal of the layer from the mesa; forming a dummy gate (4) on the mesa to define a gate; laterally separating metal implants (5), contact implants (6) and gate (12) by shrink etching the dummy gate; inserting an implant in the source and drain region and producing a silicide; planarizing up to the upper surface of the dummy gate; etching the gate and inserting the gate; and applying a low ohmic connection metallization to the source, drain and gate. Preferred Features: The gate is a Schottky, MOS, MIS, MES or junction gate. The dielectric layer is made from a thermal oxide.

Description

The invention relates to a method for producing a field effect transistor according to the preamble of claim 1.

The invention is used in the manufacture of field effect transistors of all kinds. One is in the production of field effect transistors endeavors to make gate dimensions as small as possible with low gate resistance achieve the steepness of the characteristic curves and the HF behavior of the components  to improve, especially the speed of switching operations. The Structure reductions are, however, due to the conventional lithography procedural limits. There are therefore self-adjusting procedures at Manufacture of various types of field effect transistors used in which the gate or gate-like or dummy gate structures as a mask for subsequent structuring processes for the production of the source and drain Areas are used. This allows the source and drain areas be brought closer to the gate so that because of the shorter Supply lines reduced parasitic supply resistance to the channel become. In addition, T-gate structures can be created that lead to a lead to a significant reduction in gate resistance.

So far, photoresist dummy gates and dummy gates are made of dielectric Layers known. Photoresist dummy gates are used in the silicon technology typically between 200 to 900 ° C tempering steps completely destroyed and can be used as a mask in the subsequent process steps Not used. Are more suitable for processes with tempering steps Dummy gates made from dielectric layers. Another The procedure is to lower the maximum temperature load below 400 ° C, so that polyimides can also be used. Appropriate High temperature processes will then turn off after removing the dummy gate Polyimide performed.

US Pat. No. 4,732,871 describes a self-adjusting method in which dummy T-gate structures are produced from double-layer sequences of Si ₃ N ₄ with different etching behavior. The process is limited to the manufacture of MESFETs.

No. 4,711,701 also describes a self-adjusting method under Ver application of a dummy T-gate, with the help of which the source and drain zone including a subsequent passivation top layer. With the one achieved by the deposition characteristics around the dummy gate In this method, layer formation can be achieved through the wedge-shaped Leaving the passivation layer does not exactly define the gate length.

In the publication IBM Technical Disclosure Bulletin, Vol. 28, No. 7 December 1985, pp. 2767 finds an inner side in the MESFET manufacture wandspacer in connection with dummy T-gate structures application. This Process sequence is limited to the production of MESFET structure turen and also leaves no scope for variable gate training.

In US 5391510 a method is specified, although some Self-adjustment method is used, however, spacers continue to be used for masking of the implantations used. This is due to the not arbitrarily selective Spacer etching especially when used on Si / SiGe heterostructures thin silicon cover layers (<10 nm) difficult to control.

The invention has for its object to provide a method with which the most versatile, self-adjusted and therefore exact gate definition under Avoiding the disadvantages contained in the prior art is ensured.

The invention is represented by the features of patent claim 1. The further claims contain advantageous training and further developments of Invention.  

The invention includes a self-adjusting method for the production of Field effect transistors using a dummy gate structure, which is advantageous can shrink by a wet or / and dry chemical selective etching as well as the self-adjusting contacting of the gate area. The height and The material composition of the dummy gate can be varied become.

First, a first thin dielectric layer, with which where appropriate, an MIS gate is formed for a subsequent method step is deposited over the entire surface. With the help of a second dielectric layer the outer boundary of the source and drain area is determined. On then structured dummy gate defines the source-drain distance of the FETs and protects the underlying one during the subsequent process steps channel area. In addition to single layers, there are also multiple layers follow with different composition particularly suitable. In the subsequent process steps, a low-resistance contacting of Prepared source and drain, using the shading effect of the dummy gate is exploited and by so-called shrink etching, a process step that the The size of the dummy gate reduces salicidation and implantation be separated laterally, without any extraordinary demands on the To place implantation conditions. Furthermore, the dummy gate ensures Shrinkage to reduce gate leakage currents to the implantation zones.

A planarization step is used to isolate the component surface Oxide layer deposited, which back to the upper limit of the dummy gate is etched.  

The dummy gate is etched out of this planarized surface and that FET gate introduced. Material is used for the dummy gate, for example combinations of oxide / polysilicon or polyimide are used together Meet requirements and for oxide deposition using PECVD or Salicidation remain temperature stable. There are also suitable wet and dry chemical etching processes which selectively shrink etch to silicon, Allow oxide or metal silicide. The polyimide dummy gate must be in front of the Healing of the implantation can be removed. With these materials is also ensure damage-free removal of the dummy gate in the channel area steadily, since corresponding selective wet and dry chemical processes exist.

The FET gate defined in a last process sequence is optionally called MES, especially Schottky, MIS, especially MOS, or junction gate forms.

In the case of the Schottky gate, the first is after the dummy gate has been etched out dielectric layer in the gate area previously removed and preferably one Metal layer sequence consisting of Pt-Ti-WTi-Al or PtSi-Ti-WTi-Al applied introduced. The lowest Pt or PtSi layer defines the barrier height of the Schottky junction, Ti / WTi the diffusion barrier and Al the low resistance Supply line.

In the case of the MOS gate, the first dielectric layer is considered high quality thermal oxide formed before the dummy gate manufacture, which after Etching out the dummy gate with one on the second dielectric layer layer of polysilicon or metal or one applied in the gate region Combination of both forms the MOS gate. In this case, the dummy Gate polyimide is used, which can be removed from the gate oxide without damage. at  the realization of a junction gate based on the entire area grown layer structure is already the etching of the dummy gate top doping layer removed outside the channel region. In a final process step, a source, drain and gate Connection metallization applied.

A particular advantage of the invention is that it the method according to the invention is a so-called low-temperature method, in which the individual process steps at a comparatively small Temperature. The building made by the process element is particularly suitable for high-frequency components with silicon Germanium layer sequences.

An additional advantage results from the combination of the process steps self-adjustment for source and drain on the implantation and metal silicide level, including the self-adjustment of the gate by the shrink etchings. The thickness of the dielectric is only due to the height of the dummy gate fixed and principally not limited in terms of process technology. Even the free one The design of the gate, which is ultimately T-shaped, serves the HF Optimization of the component.

Another advantage of the invention is the highest possible Flexibility in the design of the gate type.

The invention is based on advantageous embodiment examples with reference to schematic drawings in the figures explained in more detail. Show it:

FIGS. 1a-h process steps for producing a field effect transistor with the dummy gate to laying down the gate definition,

Fig. 2a-c process steps of a Schottky gate field effect transistor with a dummy gate from the gate definition,

FIGS. 3a-h process steps of a MOS field effect transistor gate

In a first exemplary embodiment according to FIGS. 1a to h, the process steps for producing a field effect transistor with a dummy gate are shown up to the definition of the gate definition. It is a typical process sequence for producing an Si / SiGe FET.

Starting from the substrate 1 , the transistors are isolated from one another by a mesa etching masked with photoresist by severing the electrically conductive layers. A distinction is then made between field area 1 a and transistor area on mesa 1 b. The structure is coated with the dielectric layer 2 , the layer thickness corresponding approximately to the mesa height. FIG. 1 a shows the structural cross section after the application of a planarizing photoresist 3. This photoresist layer 3 is etched back until the dielectric layer 2 is exposed on the mesa 1 b and then as an etching mask 3 b for the wet chemical removal of the dielectric layer 2 on the mesa 1 b used (see Fig. 1b).

FIG. 1c, the already completed structured from an entire surface coated polyimide or polysilicon layer dummy gate 4 shows with the mask plane. 5

In FIG. 1d, the result of a self-adjusting silicide formation is by depositing an all-over metal layer, annealing, removal of the unreacted metal from the dummy gate and the field areas and final shrinkage etching. This creates the silicide 5 and the width and height of the dummy gate 4 b is reduced. If a polyimide is used as a dummy gate, the shrinkage occurs when the unreacted nickel is removed in the sulfuric acid / hydrogen peroxide mixture. Nickel has to be used in the case of the polyimide dummy gate due to the necessary temperature reduction.

The subsequent contact implantation 6 is laterally separated from the silicide edge by the shrinkage (see also FIG. 1e) in order to reduce undesired leakage currents. A renewed shrinkage etching in FIG. 1f results in a lateral separation from the contact implantation 6 and the later gate (see in FIG. 2) in order not to generate any undesired gate leakage currents. An insulating layer 7 is then applied by means of a low-temperature CVD process and is leveled by the planarization layer 8 (for example photoresist or polyimide) - as shown in FIG. 1 g. An etching selectivity between the insulating layer 7 and the planarization layer 8 is set from just above one, so that the profile shown in FIG. 1h results after removal of the dummy gate.

Now the implantation heals in a temperature range of approx. 600 to 1000 ° C under an inert gas atmosphere.

The FET gate defined in a last process sequence is, as shown in FIG. 2, optionally designed as an MES, in particular Schottky or, as shown in FIG. 3, as an MIS, in particular MOS, or junction gate.

In the case of the Schottky gate structured in FIG. 2, after etching out the dummy gate 4 d and cleaning the surface or, if appropriate, removing a thin protective layer, a metal layer sequence 11 consisting of Pt-Ti-WTi-Al or PtSi- Ti-WTi-Al applied. The lowest Pt or PtSi layer defines the barrier height of the Schottky junction, Ti / WTi the diffusion barrier and the aluminum the low-resistance supply line. In a final process step, a connection metallization 12 is applied to the source, drain and gate.

In the case of MOS gate according to Fig. 3a-h is a dielectric layer 2 b as a high quality thermal oxide is formed, which after etching out said dummy gate applied with a dielectric on the first layer in the gate region layer 12 of polysilicon or metal or a combination of both forms the MOS gate. If a high temperature oxide is required, this is formed before the dummy gate is manufactured. In this case, polyimide is used for the dummy gate and can be removed from the gate oxide without damage. In a final process step, a connection metallization 12 is in turn applied to the source, drain and gate.

Claims (7)

1. Self-adjusting method for the production of field effect transistors by means of a dummy gate structure and shrink etching, with the following features:

• the outer boundary of the source and drain region is determined on a substrate ( 1 ) with a mesa etching, a deposition of a dielectric layer ( 2 ) and a self-aligned removal of this layer from the mesa ( 1 b),
• a gate ( 4 ) is produced on the mesa ( 1 b) for the gate definition,
• - A lateral separation of metal ( 5 ), contact implantation ( 6 ) and gate ( 12 ) is carried out by shrink etching of the dummy gate ( 4 , 4 b and 4 c),
• an implantation is made in the source and drain area and a silicide is produced,
• a planarization is carried out up to the upper limit of the dummy gate ( 4 ),
• - the dummy gate ( 4 ) is etched out and the gate inserted,
• - A low-resistance connection metallization is applied to the source, drain and gate.

2. The method according to claim 1, characterized in that as a gate Schottky, MOS, MIS, MES or junction gate is produced. 3. The method according to claim 2, characterized in that in the case of the MOS gate, the first dielectric layer ( 2 b) is formed as a high-quality thermal oxide, which after etching out the dummy gate ( 4 ) with one on the first dielectric layer in the gate region ( 2 c) applied layer ( 12 ) made of polysilicon or metal or a combination of both forms the MOS gate. 4. The method according to claim 3, characterized in that the high quality thermal oxide is formed from a low temperature process. 5. The method according to any one of claims 1 to 4, characterized in that polyimide is used for the dummy gate ( 4 ). 6. The method according to any one of the preceding claims, characterized characterized in that in the case of the Schottky gate a metal layer sequence consisting of Pt-Ti-WTi-Al or PtSi-Ti-WTi-Al is used.   7. The method according to any one of the preceding claims, characterized characterized in that a silicide in the source and drain area is a nickel silicide is used.