DE10018871A1 - Semiconducting device has decision feedback correction, dispersion computer that produces compensation signal from dispersion values derived from decision signals, asymmetry compensator - Google Patents

Abstract

The device has a decision feedback correction device for correcting the waveform of a corrected input signal by comparing the signal with a reference level to produce a decision signal with first and second decision values and an error signal. A dispersion computer connected to the decision feedback correction device produces a compensation signal using two dispersion values derived from the decision signals and an asymmetry compensator. An Independent claim is also included for a decision feedback correction device.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a half lead device, and in particular to a semiconductor device device (read channel LSI) in a digital magnetic memory direction using a read signal from a read head error correction or decision feedback equalizer (decision feedback equalizer) demodulated and de encoded, or a semiconductor device in a baseband Transmission device that demodu a received signal and decoded.

A hard disk drive has a read channel IC that contains an A / D (analog-to-digital) converter, which is replaced by a an analog signal read from a hard disk converts to a digital signal, and an equalizer that the digital signal generates a decoded digital signal decoded.

Because the recording density of data and the reading increasing speed, there is more interest in a Ent divorce feedback equalizer (DFE) as a waveform equalizer from PRML (partial response and maximum likelihood Detection) type. The PRML type waveform equalizer is required uses a high-precision digital filter and an equalizer file ter, which is an increase in processing speed and egg Prevent circuit miniaturization. On the other hand the DFE has a relatively simple circuit structure and delivers thus a preferable way to read speed and improve miniaturization.

As shown in Fig. 1, the read head provides a re-produced waveform having a voltage corresponding to a change in a magnetic field on the recording medium. When the bias point of the reproduced waveform is shifted due to any disturbance factor, a reproduced waveform having a vertical asymmetry represented by the broken line in FIG. 3 is formed. When the reproduced waveform has an asymmetry, its electromagnetic conversion characteristic is represented by an approximation curve as shown in FIG. 2. In Fig. 2, the straight line indicates the input / output waveform characteristic of an ideal reproduced waveform.

The asymmetry of the reproduced waveform from the head and the insufficient characteristic setting performance of the Ent zerrers create a deformation in the generated by the DFE equalized waveform. This deformation is called the Dif reference between an equalized target waveform and the deed neuter rectified waveform detected.

The asymmetry of the reproduced waveform also leads to a mistake in a decision made by the equalizer rer is hit, whereby the bit error rate of decoded Si gnale increases. To cope with this disadvantage, kor a conventional read channel LSI rigors the asymmetry of the reproduced waveform using the following Schemes.

Scheme 1: A digital signal from the A / D converter is released, is divided into two components with respect to a Ba line of a predetermined level (e.g., the zero level) divides, and correction values become the two divided di gital signals added.

Scheme 2: The input amplitude is predetermined Number of partial amplitudes divided, and for each part Correction values set in amplitude become the digi tal signal added while the input / output characters Statistical curve in every partial amplitude using poly gonlines is approximated.

These schemes are carried out by the bit error rate an output signal (disk read data) with respect to an on output signals (disk write data) measured and the characters Equalizer based on the measurement result is posed. As it is necessary, the bit error rate again gets to measure and incorporate the characteristics of the equalizer setting takes a considerable amount of time claim.

Scheme 1 only corrects the peak value of a reprodu graced the waveform so that its corrective effect is small is. Since correction values are preset in scheme 2,  this scheme cannot with a change in the input signal bypass.

Japanese Unexamined Patent Application (KOKAI) No. Hei 10-83626 discloses a DFE, which is a forward equalizer (Forward filter), an adder, a code detector (Ent divider unit) and a feedback equalizer (feedback filter). Both the forward equalizer and the Equalizers contain an FIR (Finite Impulse Response) - Filter, and the characteristics of either equalizer or Koef become efficient on the basis of the detection result (Reproduction state) automatically switched on by the code detector poses. This structure reduces reproductive errors that by noise from a head unit (MR head) with a Fer errors or an asymmetrical characteristic be called. This means that this structure suppresses repro production errors caused by factors such as B. Conditions of use conditions, production fluctuations and time-dependent changes be generated.

The forward filter and feedback filter have one similar correlation. The coefficient of the re becomes concrete coupling filter by the characteristics of the forward filter certainly. To change the coefficient of the forward filter, therefore the coefficient of the feedback filter should also be changed. Arithmetic circuits are used around the coefficients of both the forward filter and to change the feedback filter. The number envisaged arithmetic circuits should equal the number of taps be any equalizer. If the number of taps increases takes, the number of arithmetic circuits takes if too, which increases the circuit area of the DFE.

If the gains from both the forward filter and also the feedback filter can be increased to the coefficient If both filters quickly converge, the return coupling loop unstable. An adaptive equalization of the front counter filter and feedback filter stabilized set the feedback loop, but takes time for it Claim that the coefficients converge. To be exact to improve the forward filter, it is desirable to increase the number of forward filters. As the increase in the number of forward filters is the gain of the forward filter  ters enlarged, it is necessary with an abrupt change tion in a filter output.

Furthermore, the maximum likelihood detector, which in the PRML system is used with a soft decision connected, whereas the DFE made a tough decision connected is. This requires that the DFE is enlarged to suppress decision errors. If an unexpected deformation on the input signal of the DFE is superimposed, the number of equalization errors therefore increases to what makes adaptive equalization difficult. As from the As can be seen above, the DFE is having a difficult time Setting connected to converge the coefficients and takes a significant time to complete Optimize setting of the coefficients.

There is a variation in the analog input section Characteristics of the DFE on the input side. To the filters to optimize coefficients according to this variation, the DFE through coefficient training. Because the training work on the forward filter and the feedback filter is time consuming and tedious.

SUMMARY OF THE INVENTION

Accordingly, a first object of the present Invention, a semiconductor device or circuit too create the asymmetry of a reproduced waveform corrected with high accuracy.

A second object of this invention is to provide a Semiconductor device or circuit with a decision to create feedback equalizer, its characteristic is simply set.

In one aspect of the present invention created a semiconductor circuit that made a decision feedback equalizer for waveform equalizing a corri gated input signal and generating a waveform contains equalized signal. The equalizer compares the wel lenform-equalized signal with a predetermined reference pe gel to a decision signal with first and second ent divorce values and an error signal between the waves form-equalized signal and the decision signal  A dispersion value calculator is with the decision feedback equalizer connected, calculates a first dis persion value of the decision signal with the first Ent divorce value and a second dispersion value of the Ent divorce signal with the second decision value below Use the error signal and generate a compensation signal using the first and second dispersions values. An asymmetry compensator is with the decision feedback equalizer and the dispersion value calculator ver bound, receives an input signal and corrects an asym metry of the input signal according to the compensation signal and delivers the corrected input signal to the decision feedback equalizer.

In another aspect of the present invention a semiconductor circuit is created that uses an analog Digital (A / D) converter for converting an analog input signal into a digital input signal with one in between contains reference voltage as a baseline. An ent divorce feedback equalizer equalizes the waveform corrected digital input signal and generates a waveform-equalized signal. The equalizer compares that waveform-equalized signal with a predetermined reference level and generates a decision signal with first and second decision values and an error signal between the waveform-equalized signal and the decision signal. On Dispersion value calculator is with the decision feedback connected equalizer, calculates a first dispersion value of the decision signal with the first decision worth and a second dispersion value of the decision using the second decision value of the error signal and generates a compensation signal under Using the first and second dispersion values. An asym Metry compensator is between the decision feedback tion equalizer and the A / D converter coupled, receives the Compensation signal from the dispersion value calculator, correct under asymmetry of the digital input signal Using the compensation signal and provides the corri gated digital input signal to the decision feedback lung equalizer. A baseline compensation detector is included connected to the decision feedback equalizer and calc  net a baseline compensation value using the waveform-equalized signal. A digital-analog (D / A) - Converter is with the baseline compensation detector and A / D converter connected, generates the intermediate reference limit voltage according to the baseline compensation value and lie produces the intermediate reference voltage at the A / D Converter.

In yet another aspect of the present Er Invention is provided a semiconductor circuit, the one Finite impulse response (FIR) equalizer for equalizing a world lenform of a digital signal contains an equalized generate digital signal. A decision feedback equalizer is connected to the FIR equalizer and compares the equalized digital signal with a predetermined reference limit level to generate a decision signal.

In another aspect of the present invention a decision feedback equalizer is provided which a finite impulse response (FIR) equalizer for equalizing ner waveform of a digital signal contains an ent generate distorted digital signal. A forward filter is connected to the FIR equalizer and filters the equalized di gital signal using a first coefficient to to generate a filtered digital signal. An adder is connected to the forward filter and adds the gefil tert digital signal and a feedback signal to an ad generated signal. A decision circuit is connected to the adder and compares the added signal with a predetermined reference level to make a decision generate signal. A feedback filter is included with the Ent separator circuit and the adder connected, that filters Decision signal using a second coefficient to generate the feedback signal and provides the feedback signal to the adder.

Other aspects and advantages of the invention will be evident from the following description, which is related is made with the accompanying drawings, which exemplify the basics of the invention.  

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, along with its tasks and advantages best share by referring to the following description of the currently preferred embodiments together with the accompanying drawings, in which:

Fig. 1 is a diagram of an electromagnetic Encrypt is lung characteristic representing the relationship between a gnetfeld Ma and the output voltage of a head;

Fig. 2 is a graph showing the relationship between an input amplitude and an output amplitude;

Figure 3 is a waveform diagram of a read data signal.

Fig. 4 is a schematic block diagram of a hard disk device according to a first embodiment of the present the invention;

Fig. 5 is a schematic block diagram of a read channel LSI of the hard disk device of Fig. 4;

Fig. 6 is a schematic block diagram of a dispersion value calculator and a loop filter of the read channel LSI of Fig. 5;

FIG. 7 is a schematic block diagram of an asymmetry compensator of the read channel LSI of FIG. 5;

FIG. 8 is a flow diagram for an asymmetry correcting routine executed by the read channel LSI of FIG. 5;

9A and 9B are histograms representing a dispersion of the amplitude of a reproduced waveform, the un ter use of a reference level was determined.

10 FIGS to 12 are graphs showing the relationship between the Be represent the input range of a read signal and the output voltage.

FIG. 13A to 13C are explanatory diagrams of a hard disk sector format;

FIG. 14 is a schematic block diagram of another example of an asymmetry compensator according to the present the invention;

15 is a schematic block diagram of an LSI Lesekanal- It is Fig according to a second embodiment of the present invention.

. Figure 16 is a flow chart for a baseline Corridor gent routine that is executed by the read channel LSI of Fig. 15;

. 17 is a schematic block diagram of a Signalpro Fig zessors according to a third embodiment of the present invention;

FIG. 18 is a schematic block diagram of a Vorprozes is sors and a DFE of the signal processor of Fig. 17;

Fig. 19 is a schematic block diagram of an FIR equalizer of the preprocessor of Fig. 18;

Fig. 20 is a schematic block diagram of a coefficient calculator of the preprocessor of Fig. 18;

FIG. 21 is a schematic block diagram of a Vorprozes sors and a DFE in accordance with a fourth embodiment of the present invention; and

Fig. 22 is a schematic block diagram of a Nachbil Droppings or Replikatsignalgenerators of the DFE of Fig. 21.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the drawings the same elements are used everywhere same digits used.

First embodiment

Fig. 4 is a schematic block diagram of a hard disk device 11 according to a first embodiment of the present invention. This hard disk device 11 receives data from a host computer 12 and records the data on a magnetic disk 13 in response to a write request from the host computer 12 . The hard disk device 11 reads data from the magnetic disk 13 and supplies the data to the host computer 12 in response to a read request.

The hard disk device 11 includes the magnetic disk 13 , first and second motors M1 and M2, a head unit 14 , a read channel LSI or a signal processor 15 , a servo circuit 16 , a microprocessor unit (MPU) 17 , a memory (RAM) 18 , a hard disk Control Unit (HDC) 19 and an interface circuit 20 , all of which are connected to a bus 21 .

The magnetic disk 13 is rotated by the first motor M1 at a constant speed. The head unit 14 is controlled by the second motor M2 so as to be movable in the radial direction of the magnetic disk 13 . The Kopfein unit 14 contains a write head and a read head, such as. B. magnetoresistive heads (MR heads). The head unit 14 forms 15 magnetic poles on the magnetic disk 13 in response to a write signal WD from the signal processor and generates a read signal RD with a voltage corresponding to changes in the magnetic poles on the magnetic disk 13 in response to a read command from the signal processor 15 .

The signal processor (read / write channel LSI) 15 converts the read signal RD into a digital signal by sampling the read signal RD according to a sampling clock which is synchronous with the read signal. The signal processor 15 decodes the digital signal and generates decoded data.

The servo circuit 16 controls the first motor M1 for ro tieren the magnetic disk 13 at a constant speed. The servo circuit 16 receives the decoded data from the signal processor 15 and controls the second motor M2 to track a target track according to a servo information contained in this decoded data.

The MPU 17 analyzes commands for a read / write process etc. from the host computer 12 according to a program stored in the RAM 18 and outputs control signals. The HDC 19 receives the control signals from the MPU 17 and controls the signal processor 15 and the servo circuit 16 . The HDC 19 also receives a digital signal from the signal processor 15 and generates sector by sector sector data comprising a predetermined number of bytes. The HDC 19 also executes an ECC (error correction code) based on an error correction sector by sector and supplies error-corrected data via the bus 21 to the interface circuit 20 . The interface circuit 20 converts the output data of the HDC 19 into data according to a predetermined communication system and supplies read data to the host computer 12 .

The HDC 19 receives write data from the host computer 12 via the interface circuit 20 and adds the error correction code to the write data. The signal processor 15 writes the output data of the HDC 19 to the magnetic disk 13 via the head unit 14 .

Fig. 5 is a schematic block diagram of the Signalpro zessors 15th Next, the read data demodulating / decoding part of the signal processor 15 will be explained. The signal processor 15 contains an amplifier with automatic gain control (AGC) 31 , an analog filter 32 , an analog-to-digital converter (ADC) 33 , an asymmetry compensator 34 , a DFE 35 , a loop control circuit 36 , a dispersion value calculator 37 , a loop filter 38 and a multiplier 39 .

The AGC 31 amplifies the read signal RD from the read unit and sends the amplified read signal to the analog filter 33 . The AGC 31 controls its own gain factor in accordance with a control voltage output from the loop control circuit 36 .

The analog filter 32 filters the amplified read signal from the AGC 31 and supplies the ADC 33 with a filtered read signal with the suitable frequency characteristic for demodulation and decoding.

The ADC 33 samples the filtered read signal from the analog filter 32 in accordance with a sample clock signal SCK provided by the loop control circuit 36 , and converts the filtered read signal into a digital read signal.

The asymmetry compensator 34 receives the digital read signal from the ADC 33 and corrects the asymmetry of the digital read signal in accordance with compensation information. The compensation information contains a compensation value for segmenting the area of the digital read signal into a plurality of partial areas and changing, partial area by partial area, the conversion gain of the digital read signal. The asymmetry compensator 34 generates new or updated compensation information on the basis of the result of the calculation in the dispersion value calculator 37 and stores the updated compensation information.

Specifically, the asymmetry of the reproduced waveform of the read signal from the head unit 14 increases when the amplitude of the read signal increases. The dispersions of the amplitude value of the reproduced waveform vary at the time an equalized waveform is generated using positive and negative reference levels of a decision circuit 43 of the DFE 35 . When the reproduced waveform has little asymmetry, as shown in Fig. 9A, the two dispersions of the amplitude value of the reproduced waveform, which are obtained by using the positive and negative reference levels, take the form of a normal distribution. However, when the reproduced waveform has an asymmetry as shown in Fig. 9B, the two dispersions of the amplitude value of the reproduced waveform do not take the form of a normal distribution. The dispersion value calculator 37 calculates the difference between the two dispersions, and the asymmetry compensator 34 determines the compensation value for the conversion gain of the digital read signal based on this difference in such a manner that the positive and negative dispersion become uniform. The asymmetry compensator 34 also determines the compensation value in a direction from a subrange close to zero (baseline) to a subrange in which the amplitude gradually increases. Accordingly, the compensation value is determined according to the characteristic of the read signal (the characteristic of the head unit 14 ) whose asymmetry increases as the amplitude gradually increases.

The asymmetry compensator 34 uses the determined compensation value for the partial area as the initial value to determine a compensation value for the next partial area. Assume that each of the positive and negative areas of the read signal is divided into three areas from one near zero to one with a maximum amplitude value. The asymmetry compensator 34 uses the compensation value, which was determined for the first positive partial area, as the initial value for determining a compensation value for the second partial area. This is because the voltage of the read signal changes continuously across the individual sections. Using the compensation value determined for the near zero portion as the initial value reduces the time required to determine the compensation value and increases the accuracy of the compensation value compared to the case where the initial value is e.g. . B. zero is reset.

Assume that the positive area of the read signal is divided into three areas (area 1 , area 2 and area 3 ) as shown in FIG . First, an approximation line for the electromagnetic conversion characteristic is determined in region 1 , and a compensation value is determined for the approximation line. Next, an approximation line is also determined in area 2 , and a compensation value is determined for the approximation line, as shown in FIG. 11. An approximation line is then determined in area 3 , and a compensation value is determined for the approximation line, as shown in FIG. 12. Therefore, the approximation line over the areas 1 to 3 , which is formed by polygon lines, becomes extremely close to the curve of the electromagnetic conversion characteristic. In other words, there is not much difference between the approximation line and the electromagnetic conversion characteristic curve. This suppresses correction errors at the time of correcting the electromagnetic conversion characteristic to an idealistic characteristic.

As discussed above, the asymmetry compensator 34 divides the area of the read signal into a plurality of part areas and approximates the curve of the electromagnetic conversion characteristic with polygon lines to determine compensation values in the individual part areas. The asymmetry compensator 34 changes the conversion gain in accordance with the compensation values to correct the asymmetry of the read signal.

The DFE 35 includes a forward filter 41 , a first adder 42 , a decision circuit 43 , a feedback filter 44 and a second adder 44 .

The forward filter 41 receives a corrected digital read signal from the asymmetry compensator 34 and sends a filtered read signal S1 with the maximum S / N ratio to the adder 42 . The adder 42 adds the filtered read signal S1 from the forward filter 41 to a feedback signal S2 that comes from the feedback filter 44 , thereby generating a waveform-equalized signal S2.

The decision circuit 43 compares the voltage of the waveform equalized signal S3 with predetermined positive and negative reference voltages and sends a decision signal S4 with a value of either "1" or "0" to the feedback filter 44 . The decision signal S4 is sampled in accordance with a sampling clock signal SCK, and decision signals corresponding to recorded data are temporarily stored in a shift register (not shown).

The feedback filter 44 , which is preferably an FIR filter, eliminates any intersymbol interference contained in the decision signal S4 and sends the decision signal S4 without the intersymbol interference as the feedback signal S2 to the adder 42 . The feedback of the decision signal S4 provides a re-produced signal which is free from interference by old bits.

The adder 45 receives the waveform equalized signal S3 from the adder 42 and the decision signal S4 from the decision circuit 43 and adds both signals S3 and S4 to produce an equalization error signal S5. The equalization error signal S5 is supplied to the loop control circuit 36 and the dispersion value calculator 37 .

The loop control circuit 36 includes a PLL (phase locked loop) filter 46 , two digital-to-analog converters (DAC) 47 and 50 , a voltage controlled oscillator (VCO) 48 and an AGC loop filter 49 .

The PLL filter 46 filters the error signal S5 and before provides the first DAC 47 with a filtered error signal. The DAC 47 converts the filtered error signal into an analog voltage and supplies the analog voltage to the VCO 48 as a control voltage. The VCO 48 generates the sampling clock signal SCK at a frequency according to the control voltage and supplies the sampling clock signal SCK to the ADC 33 and the DFE 35 . In this way, a PLL is created which optimizes the frequency of the sampling clock signal SCK (sampling timing) on the basis of the phase error between the waveform-equalized signal S3 and the decision signal S4.

The AGC loop filter 49 filters the error signal S5 and supplies the second DAC 50 with a filtered error signal. The DAC 50 converts the filtered error signal into an analog voltage and supplies the analog voltage to the AGC 31 as a control voltage. The AGC 31 controls its own gain according to the control voltage. In this way, an AGC loop is formed which optimizes the gain of the AGC 31 (the amplitude of the amplified read signal) based on the amplitude error between the waveform-equalized signal S3 and the decision signal S4.

The dispersion value calculator 37 receives the decision signal S4 from the decision circuit 43 and the equalization error signal S5 from the adder 45 , calculates the amplitude value dispersion at an equalization target level using the signals S4 and S5, and generates an amplitude dispersion signal S6.

Specifically, the dispersion value calculator 37 squares the error signal S5, multiplies the square of the decision signal S4 with a decision result "1" (positive) corresponding error signal S5 by a predetermined number (e.g. 100 samples) and multiplies the square of that Error signal S4 with a decision value "0" (negative) corresponding error signal S5 with the predetermined number. This multiplication provides a dispersion value for the decision result "1" and a dispersion value for the decision result "0". The dispersion value calculator 37 calculates the difference between the dispersion value for the decision result "1" and the dispersion value for the decision result "0", whereby an error compensation signal S6 is generated.

The loop filter 38 receives and filters the error compensation signal S6 from the dispersion value calculator 37 , whereby a filtered error compensation signal S7 is generated, the frequency characteristic of which is suitable for the asymmetry compensator 34 .

The multiplier 39 multiplies the filtered error compensation signal S7 from the loop filter 38 by a predetermined coefficient ki, whereby an error compensation signal S8 multiplied by a coefficient is generated. The coefficient ki is determined such that the value of the filtered error compensation signal S7 of the loop filter 38 becomes smaller in accordance with the individual subregions of the asymmetry compensator 34 . This prevents the filtered error compensation signal S7 from causing the asymmetry compensator 34 to overreact.

FIG. 6 is a schematic block diagram illustrating the dispersion value calculator 37 and the loop filter 38 . The dispersion value calculator 37 includes a square circuit 51 , first and second dispersion value calculators 52 and 53 and an adder 54 .

The square circuit 51 squares the error signal S5 from the DFE 35 and supplies the first and second dispersion value computers 52 and 53 with a square signal S11. According to the decision signal S4 with the decision result "1" (positive), the first dispersion value calculator 52 performs a multiplication of the square signal S11 to calculate a dispersion value. In response to the decision signal S4 with the decision result "0", the second dispersion value calculator 53 performs a multiplication of the square signal S11 to calculate a dispersion value.

The first dispersion value calculator 52 contains a gate circuit 55 , an adder 56 and an accumulator (ACC0) 57 . The gate circuit 55 supplies the square signal S11 to the adder 56 when the decision signal S4 is "1". The adder 56 adds the square signal S11 and the output signal of the accumulator 57 and supplies the accumulator 57 with an added signal. The accumulator 57 sequentially stores the added signal from the adder 56 and generates an average of the stored added signals. The middle square of the error signal S5 provides the dispersion value of the amplitude of the reproduced waveform for the decision result "1".

The second dispersion value calculator 53 includes a gate circuit 58 , an adder 59 and an accumulator (ACC1) 60 and provides the dispersion value of the amplitude of the reproduced waveform for the decision result "0" by the middle square of the error signal S5. The adder 54 adds the dispersion value from the first dispersion value calculator 52 and a two's complement (a negative dispersion value) of the dispersion value from the second dispersion value calculator 53 , generating the error signal S6 with a compensation error Verr.

The loop filter 38 includes a multiplier 61 , an adder 62 and a register 63 . The multiplier 61 multiplies the error compensation signal S6 from the dispersion value calculator 37 by a predetermined coefficient .mu., Thereby generating a signal multiplied by a coefficient. The adder 62 adds the signal multiplied by a coefficient and the output signal of the register 63 and generates an added signal. The register 63 stores the added signal from the adder 62 and outputs the added signal as the filtered error compensation signal S7.

Fig. 7 is a schematic circuit diagram of the geometry Asym compensator 34th

The asymmetry compensator 34 contains six partial compensators 711 to 716 corresponding to the respective partial areas and a selector 72 . All Teilkompensatoren 711-716 who to the compensation signal supplied S8 from the adder 39 with a non-corrected read signal X from ADC 33 and.

The first partial compensator 711 contains first and second comparators 73 and 74 , first and second AND gates 75 and 76 , a multiplier 77 and a register 78 . A voltage on the high potential side of the assigned portion is input as a high reference voltage H_Ref_i in the first comparator 73 and a voltage on the low potential side of the assigned portion is input as a low reference voltage L_Ref_i in the second comparator 74 .

The first comparator 73 receives the read signal X and the high reference voltage H_Ref_i (i = 1 to 6) of the assigned partial area and emits an H-level signal when the potential of the read signal X is lower than the high reference voltage H _Refi . When the potential of the read signal X is higher than the low reference voltage L _Refi , the second comparator 74 outputs an H-level signal.

When the output signals of the first and second comparators 73 and 74 both have an H level, the first AND gate 75 sends an output signal with an H level to the second AND gate 76 . When the first AND gate 75 outputs the H level signal (ie when the read signal X is in a range from the high reference voltage H_Ref_i to the low reference voltage L_Re_i), the second AND gate 76 supplies the multiplier 77 with Read signal X. The multiplier 77 multiplies the read signal X by a compensation value αi (α1 for the first partial compensator 711 ; i = 1 to 6), which is based on the compensation signal S8, which is stored in the register 78 , and sends a corrected read signal to selector 72 .

The second to sixth Teilkompensatoren 712-716 ha the same structures ben as the first Teilkompensator 711 and multiply the read signal X, which is in the range of the high reference voltage H_Ref_i (i = 2 to 6) up to the low reference voltage L_Ref_i, with the Kompensati ons value αi to generate corrected read signals S22 to S26.

If the voltage (absolute value) of the read signal X is lower than the set voltage range of the assigned partial compensator, each register 68 stores the compensation signal S8. That is, each register 78 does not store the compensation signal S8 if the voltage of the read signal X is higher than the set voltage range of the assigned partial compensator.

Assume that the voltage ranges are set in the order of the first, second and third partial compensators 711 , 712 and 713 , while the amplitude of the read signal increases from zero. In this case, the register 78 of the second partial compensator 712 stores the compensation signal S8 when the voltage of the read signal X is in the voltage range of the first partial compensator 711 . Therefore, when the voltage of the read signal X comes into the voltage range of the second partial compensator 712 , the second partial compensator 712 uses the compensation value α1 of the first partial compensator 711 , which is stored in its register 78 , as the initial value.

The initial value can be set in each register 78, by a circuit for selectively supplying the Kom pensationssignals S8 to the individual Teilkompensatoren 711 - is provided 716th If the voltage of the read signal X enters the voltage range of a partial compensator, this circuit supplies the compensation signal S8 to the register of this partial compensator, the voltage range of which is higher than the first-mentioned voltage range.

The selector 72 selects one of the corrected read signals S21-S26 by the respective Teilkompensatoren 711-716 accelerator as a selection signal SELi. The value of the selection signal SELi is adjusted so that each time the read signal X capacitors in the voltage range of any of the individual Teilkompen 711-716 occurs, the associated Teilkompensator is selected.

In the above-described manner, each of the corrected Teilkompensatoren 711 - 716 corresponding to the part preparation chen the read signal X using the compensation value .alpha..sub.i and generates the read signal X, which has a symmetry.

The asymmetry correcting routine executed by the read channel LSI (signal processor) 15 will now be explained with reference to the flowchart in FIG. 8.

First, in step 81, the accumulator (ACC0) 57 and the accumulator (ACC1) 60 are deleted.

In step 82 , the decision signal S4 and error signal S5 are generated from the magnetic disk 13 using read data RD. In step 83 , a dispersion calculation is initiated using the decision signal S4 and error signal S5.

In the next step 84 , it is determined whether a current sample number n0 matches a predetermined sample number N. If the number of samples n0 is smaller than the predetermined number of samples N, the process proceeds from step 84 to step 82 . That is, steps 82 through 84 are repeated until the sample number n0 reaches the predetermined sample number N.

When the sample number n0 reaches the predetermined sample number N, the flow advances to step 85 . In step 85 , the difference between the dispersion value for the decision result "1" and the dispersion value for the decision result "0" is calculated. In step 86 , an asymmetry compensation control is then performed based on the difference.

In step 87 , it is determined whether a compensation number m0 matches a predetermined compensation number M.

If the compensation number m0 is less than the predetermined compensation number M, the process proceeds from step 87 to step 81 . That is, steps 81 to 87 are repeated until the compensation number m0 reaches the predetermined compensation number M. This repeated compensation improves the accuracy of compensation values.

When the compensation number m0 reaches the predetermined compensation number M, the flow advances to step 88 . In step 88 , the compensation section is switched to the next section. In step 89 it is determined whether the compensation has been completed for all subareas. If compensation has not yet been completed, the process returns to step 81 . When compensation has been completed, the asymmetry correcting routine is terminated.

The read channel LSI 15 is constructed to avoid the influence of the AGC loop and the PLL while dispersion values are being calculated. This design allows compensation values to be generated quickly with high precision.

Concretely, holding or the signal processor 15 stops the AGC loop and the PLL in such a manner that the first and second DACs 47 and 50 leave constant in the loop control circuit 36 signals. Therefore, since the AGC 31 amplifies the read signal RD with a constant gain, the amplitude of the reproduced waveform does not change. Furthermore, the loop control circuit 36 outputs the sampling clock SCK with a constant period, thereby stabilizing the sampling timing.

The error signal S5 is used to generate the sampling clock SCK and the gain control of the AGC 31 and to calculate dispersion values. If an operation synchronous with the sampling clock SCK or the gain control of the AGC 31 is underway, the sampling timing or the amplitude of the reproduced signal waveform is not stable, so that no accurate dispersion values are determined.

The signal processor 15 can operate to suppress the operation of the AGC / PLL. That is, the signal processor 15 can change the loop constant of the loop control circuit 36 in such a manner that a change in the gain of the AGC 31 and / or a change in the frequency of the sampling clock SCK becomes smaller. This also stabilizes a change in the amplitude of the reproduced waveform and the sampling timing.

The signal processor 15 writes pattern data to stabilize the AGC / PLL on the magnetic disk 13 . The AGC / PLL is likely to be stable when the read data RD read from the magnetic disk 13 has a periodic pattern. On the other hand, if the read data RD has a random pattern, the compensation loop improves the precision of dispersion values.

Fig. 13 (a) schematically shows the recording format of an ordinary sector. A sector 91 contains a preamble area 91 a, a sync byte (SD) area 91 b and a data area 91 c.

In the preamble area 91 , a preamble code is recorded which contains control data which are used to set the gain factor of the AGC 31 and to generate the sampling clock SCK in synchronism with the read signal RD. The preamble belcode can e.g. B. "111000", and the read signal RD of the preamble code has a sine wave. The loop control circuit 36 generates the sampling clock SCK according to the read signal RD with the sine wave. The ADC 33 generates a digital read signal RD according to the sampling clock SCK.

In the sync byte area 91 b, a sync byte code (SB code) is recorded, which is mainly used to detect the beginning of the next data area 91 c. The HDC 19 treats the data in the data area 91 according to the sync byte code as recorded data and processes it on recorded data.

The signal processor 15 in the first embodiment records various patterns in a sector 92 on the magnetic disk 13 in the recording format as shown in Fig. 13 (b). The sector 92 contains a preamble area 92 a, a sync byte area 92 b, a first pattern area 92 c and a second pattern area 92 d. A periodic pattern is recorded in the first pattern area 92 c and a random pattern is recorded in the second pattern area 92 d.

The signal processor 15 stabilizes the first AGC / PLL according to the read data RD of the of the first pattern region 92 c read periodic pattern. Thereafter, the signal processor 15 stops the AGC / PLL and calculates dispersion values with high accuracy using the read data RD of the random pattern read from the second pattern area 92 d.

As an alternative, various patterns can be recorded in a sector 93 in the recording format as shown in Fig. 13 (c). The sector 93 contains a preamble area 93 a, a sync byte area 93 b and it to fourth pattern areas 93 c to 93 f. In the first through fourth pattern regions 93 c- 93 f a peri odic pattern and a random pattern are alternately recorded. According to the periodic and random patterns, the signal processor 15 alternately stabilizes the AGC / PLL and calculates dispersion values.

The signal processor 15 of the first embodiment has the following advantages.

• 1. The dispersion value calculator 37 calculates the dispersion value for the decision result "1" and the dispersion value for the decision result "0" using the error signal S5 between the waveform-equalized signal S2 and the decision signal S4 and generates the two dispersion values a compensation signal S6. The asymmetry compensator 34 divides the range of the input signal into several partial areas and corrects partial area by partial area the asymmetry of the input signal according to the compensation value αi corresponding to the compensation signal S8. Accordingly, the asymmetry of the read data RD is detected and corrected while the read data is being input, thereby ensuring an extremely accurate and effective correction.
• 2. The asymmetry compensator 34 determines the compensation value in a direction from a partial area close to zero (baseline) to a partial area in which the amplitude gradually increases. That is, the compensation value is determined in accordance with the characteristic of the read signal (the characteristic of the head unit 14 ) whose asymmetry increases while the amplitude gradually increases.
• 3. The asymmetry compensator 34 uses the compensation value of a small amplitude determined for one sub-area as the initial compensation value for the next sub-area. The use of the compensation value in this way shortens the time required to determine the compensation value compared to the case in which the initial value is e.g. B. zero is reset.
• 4. During a calculation of dispersion values, the signal processor 15 limits the operation of the loop by stopping or holding the AGC loop and PLL control or changing the loop constant. Accordingly, the dispersion value calculator 37 and the asymmetry compensator quickly provide compensation values with high precision without being affected by the AGC / PLL.
• 5. The signal processor 15 first stabilizes the AGC / PLL according to the read data RD of a periodic pattern read from the first pattern area 92 c and then determines dispersion values according to the read data RD of a random pattern that was read from the second pattern area 92 d. This provides dispersion values with high precision, while reducing the influence of the AGC / PLL on the calculation of the dispersion values.

In the first embodiment, an asymmetry compensator 101 as shown in FIG. 14 can be used. This asymmetry compensator 101 contains three partial compensators 102 a, 102 b and 102 c and a selector 103 . Each of the partial compensators 102 a- 102 c contains partial compensation parts 104 p and 104 n, which are provided symmetrically to the baseline, and a selector 105 . The asymmetry compensator 101 corrects the asymmetry in directions toward the positive amplitude and the negative amplitude from almost zero almost simultaneously. This shortens the time required to correct the asymmetry.

Second embodiment

Fig. 15 is a schematic block diagram of a signal processor or a read channel LSI (signal processor) 111 accelerator as a second embodiment of the present invention. The read channel LSI 111 includes, in addition to the structure of the first embodiment, first and second baseline compensation detectors 112 and 113 , three registers 114 , 115 and 116 and a DAC 117 . The first and second baseline compensation detectors 112 and 113 have the same structure and are provided to determine the need for the baseline correction. In Fig. 15, the AGC 31 , the analog filter 32 , the asymmetry compensator 34 , the loop control circuit 36 , the dispersion value calculator 37 , the loop filter 38 , the multiplier 39 and the adder 35 are not shown.

The first detector 112 includes first and second comparators 121 and 122 , an AND gate 123 and a counter circuit 124 .

The first comparator 121 receives the waveform-equalized signal S3 from the DFE 35 and a first detection area voltage + Ref + Δ and outputs an H-level signal when the voltage of the waveform-equalized signal S3 is lower than the first detection area voltage + Ref + Δ is. The first detection range voltage + Ref + Δ is higher than the positive reference voltage + Ref of the decision circuit 43 .

The second comparator 122 receives the waveform-equalized signal S3 and a second detection range voltage + Ref-Δ from the DFE 35 and outputs an H-level signal when the voltage of the waveform-equalized signal S3 is higher than the second detection range voltage + Ref -Δ is. The second detection range voltage + Ref-Δ is set lower than the positive reference voltage + Ref of the decision circuit 43 .

The AND gate 123 outputs an H level signal when the voltage of the waveform-equalized signal S3 is between the first detection area voltage + Ref + Δ and the second detection area voltage + Ref-Δ.

The counter circuit 124 clears the count in response to an enable signal END having an L level, and counts the sampling clock signal SCK in response to the enable signal END having an H level and the H level signal from the AND gate 123 . The counter circuit 124 counts the number of samples of the waveform-equalized signal S3, the voltage of which lies between the first and second detection range voltages + Ref + Δ and + Ref-Δ. That is, the number of samples of the waveform-equalized signal in the vicinity of the positive reference voltage + Ref is counted. The circuits by the counter 24 counted sample number is first stored in the first regi art 124th

The second detector 113 counts the number of samples of the waveform-equalized signal S3, the voltage of which lies between a first detection range voltage -Ref + Δ and a second detection range voltage -Ref-Δ, and stores the counted second number of samples in the second register 115 . The first detection range voltage -Ref + Δ is set higher than the negative reference voltage -Ref, and the second detection range voltage -Ref-Δ is set lower than the negative reference voltage -Ref.

The MPU 117 receives the first and second sample numbers stored in the first and second registers 114 and 115 via the bus 21 and determines whether a baseline correction is needed, and calculates a compensation value based on these two sample numbers based. Specifically, the MPU 17 determines that a baseline correction is necessary when the difference between the first and second sampling numbers is larger than a predetermined value. The predetermined value is preset according to the tolerance range of the asymmetry. The MPU 17 then calculates a base compensation value based on the difference between the two sampling numbers and updates the compensation value stored in the third register 116 with the calculated one.

The DAC 117 receives the compensation value stored in the third register 116 and supplies the ADC 33 with an intermediate voltage VRM in accordance with the input signal. The ADC 33 receives the filtered read signal RD from the analog filter 32 , the high reference voltage VRH, a low reference voltage VRL and the intermediate voltage VRM from the DAC 117 and converts the filtered read signal RD with the same level as the intermediate voltage VRM into a digital signal a value of zero. Changing the level of the intermediate voltage VRM therefore corrects the level of the filtered read signal RD that is to be converted into a digital signal with a value of zero, or corrects the baseline.

The baseline correcting routine will now be discussed with reference to the flow chart in FIG. 16.

In the first step 131 , the MPU 17 outputs the ENB release signal with an H level, which initiates a measurement for correcting the asymmetry. At step 132, read channel LSI 111 measures an asymmetry error by counting the number of samples near the positive and negative reference voltages. The measured value is passed from the read channel LSI 111 to the MPU 17 .

In step 134 , the MPU 17 determines whether the asymmetry is within the tolerance range based on the measured value. If the asymmetry is outside the tolerance range, the flow advances to step 135 . In step 135 , a compensation value is calculated based on the measured value, and the compensation value in the third register 116 in the read channel LSI 111 is updated with this calculated value. The process then goes to step 133 . If the asymmetry is within the tolerance range in step 134 , the routine is ended. The baseline is corrected by repeating the measurement of the asymmetry error and the adjustment of the compensation value in this way.

Thereafter, the read channel LSI 111 corrects the asymmetry using a polygon line approximation according to the first embodiment.

The baseline correction is for a reproduced world lenform effective, which has a large asymmetry. The means the high-precision correction is made by correcting the Asymmetry achieved to a certain extent by the Ba Sis line correction implemented and then the asymmetry corrective routine of the first embodiment executed becomes.

The read channel LSI 111 according to the second embodiment has the following advantages.

• 1. The first and second baseline compensation detectors 112 and 113 determine dispersion values within predetermined ranges around the reference levels + Ref and -Ref. The MPU 17 calculates compensation values based on the dispersion values. According to the compensation values, the DAC 117 corrects the intermediate reference voltage VRM to determine the zero level to be output from the ADC 33 , or corrects the baseline. Therefore, the asymmetry is measured during data entry, and the base line is corrected based on the result of the measurement.
• 2. If the waveform equalized signal S3 is present within predetermined ranges around the predetermined reference levels + Ref and -Ref, the counter circuit 124 counts the sampling clock SCK. Therefore, based on the count value, dispersion around the reference level is simply measured.

The dispersion values of the waveform-equalized signal can be determined by using four or more reference levels an even number instead of two reference levels + Ref and -Ref be used.

The MPU 17 may directly receive the first and second sample numbers from the first and second detectors 112 and 113 instead of receiving them from the first and second registers 114 and 115 .

Third embodiment

Fig. 17 is a schematic block diagram of a signal processor or a read channel LSI 150 according to a third embodiment of the present invention. Write data supplied by the MPU 17 is supplied to a scrambler 232 via a first interface circuit 231 . The scrambler 232 performs a scrambling process to change the order of bits in the write data according to a predetermined process, and supplies scrambled write data to an encoder 233 . The encoder 233 encodes the scrambled write data according to a predetermined RLL (run length limited) code (specifically, an RLL (1,7) code). The encoder 233 adds control data containing preamble data to the encoded data to control a read operation. The encoder 233 provides the resulting signal to a write precomparator 234 .

The write precomparator 234 receives the encoded data from the encoder 233 and subjects the encoded data to a process of correcting the data write timing on the magnetic disk 13 . The timing correcting process is carried out to prevent the positions of write information ("1", "0") on the magnetic disk 13 from being deviated due to the influence of the adjacent magnetic poles. The write precomparator 234 converts the encoded data into data according to the NRZI format after correction, and then outputs the resulting data.

A write flip-flop (F / F) 235 receives the encoded data from the write precomparator 234 and delivers a write signal WD to the write head 14 a of the head unit 14 , which consists of a coil. The write F / F 235 supplies a current corresponding to the write data to the magnetic disk 13 . This current forms the magnetic poles on the magnetic disk 13, whereby on the magnetic disk 13, an information will be indicative net, the data, the preamble and the sync byte includes.

The read head 14 b of the head unit 14 contains an MR (magnetoresistive) head and supplies a preprocessor 236 with a read signal RD which corresponds to a change in the magnetic poles of the magnetic plate 13 . The preprocessor 236 amplifies and filters the read signal RD, whereby a filtered read signal is generated, the frequency of which is suitable for de-modulation and decoding. Preprocessor 236 converts the filtered read signal to a digital read signal, equalizes the digital read signal, and sends the equalized digital read signal to a DFE 237 .

The DFE 237 performs waveform equalization and determination processes on the equalized digital signal from the preprocessor 236 according to the sampling clock SCK from a PLL circuit 238 and generates a decision signal. The PLL circuit 238 generates the sampling clock SCK synchronized with the read signal RD by using the decision signal from the DFE 237 .

A decoder 239 receives the decision signal from the DFE 237 , decodes the decision signal according to the RLL code, and provides the decoded data to a descrambler 240 . The descrambler 240 performs a descrambling process that rearranges the bits of the decoded data according to a predetermined process, thus producing descrambled decoded data. The descrambled decoded data are supplied to the MPU 17 as read data via a second interface circuit 241 .

Fig. 18 is a schematic block diagram illustrating the pre processor 236 and the DFE 237th The DFE 237 includes a forward filter 237 a, an adder 237 b, a decision circuit 237 c and a feedback filter 237 d.

The forward filter 237 a, which is preferably a FIR (finite impulse response) filter is the equalized di gitale signal received from the preprocessor 236 and filters it in such a manner to adjust the S / N ratio to maximize the digital signal, whereby a filtered digital signal is generated.

The adder 237 b adds the filtered digital signal from the forward filter 237 a and the feedback signal from the feedback filter 237 d, generating a waveform-equalized signal.

The decision circuit 237 c compares the waveform-equalized signal from the adder 237 b with a reference voltage and generates a decision signal with a decision result "1" or "0".

The feedback filter 237 d, which is preferably an FIR filter, receives the decision signal from the decision circuit 237 c and generates the feedback signal S2 by eliminating an intersymbol interference from the decision signal. The feedback signal S2 is supplied from the feedback filter 237 d to the adder 237 b. This feedback loop provides a reproduced signal that is free from interference from old bits.

Referring again to Fig. 17 receives a control data detector 242, the decision signal from the DFE 237, control data is detected (preamble and sync byte) for STEU ren of reading recorded data and information (servo mark) for a servo control, and sends Detekti onssignale to a sequence control unit 243 and the MPU 17 .

The sequence control unit 243 receives the detection signals from the detector 242 and the write / read control signal from the MPU 17 and controls the signal processor 150 according to a predetermined read / write sequence.

When a sync byte detection signal is received after providing a read operation to the signal processor 150 , the MPU 17 processes the read data after the sync byte as recorded data.

As shown in Fig. 18, the preprocessor 236 includes an amplifier with automatic gain control (AGC) 236 a, a low-pass filter 236 b serving as an analog filter, an analog-to-digital converter (ADC) 236 c, an FIR equalizer 236 d and a coefficient update circuit 236 e.

The AGC 236 a amplifies the read signal RD from the head 14 and sends the amplified read signal to the low-pass filter 236 b. The low-pass filter 236 b filters the amplified read signal from the AGC 236 a, thus generating a filtered read signal whose frequency is suitable for demodulation and decoding. The AGC 236 c receives the filtered read signal from the low-pass filter 236 b and converts the filtered read signal into a digital signal by sampling the filtered read signal in accordance with the sampling clock SCK.

The FIR equalizer 236 d equalizes the waveform of the digital signal according to the transmission line Zx from the head unit 14 to the preprocessor 236 and the transmission characteristic of the analog signal from the AGC 236 a to the low-pass filter 236 b, whereby an equalized digital signal Za ( n) is generated in accordance with a predetermined transmission characteristic. It is preferable that the FIR equalizer d 236 should contain an FIR filter.

Fig. 19 is a schematic block diagram of the FIR equalizer 236 d. The FIR equalizer 236 d has a shift register 251 which has a plurality of (in this case five) registers 251 a to 251 e, five multipliers 252 a to 252 e corresponding to the registers 251 a to 251 e and an adder 253 contains.

The registers 251 a-251 e are connected in series, and each of the register samples the digital signal from the ADC 236 c or the digital signal from the previous stage of the register and supplies the sampled data to the next stage of a register. That is, the shift register 251 stores sampled old data.

The multipliers 252 a- 252 e each receive data D1 to D5 stored in the respective registers 251 a- 251 e and predetermined coefficients C1 to C5 provided by the coefficient update circuit 236 e, and multiplies the data D1-D5 in this order with the coefficients C1-C5. The adder 253 receives the multiplication results from the multipliers 252 a- 252 e and adds the five multiplication results, thereby generating an equalized digital signal Za (n).

Referring back to Fig. 18, the coefficient update circuit 236 e calculates the coefficients C1-C5 using an added signal ya (n) output from the adder 237 b and a decision signal yb (n) output from the decision circuit 237 c. The individual coefficients C1-C5 are determined from the following equations using an LMS algorithm (Least Mean Squares).

C1 = C1b + µ.D1.ER

C2 = C2b + µ.D2.ER

C3 = C3b + µ.D3.ER

C4 = C4b + µ.D4.ER

C5 = C5b + µ.D5.ER

where C1b-C5b are coefficients before an update, ER is an error between the added signal ya (n) and the decision signal yb (n) (ya (n) -yb (n)), D1-D5 in the respective registers 251 a - 251 b are data to be stored and µ is a step size.

The coefficient update circuit 236 e includes an error calculation adder 255 and a coefficient calculator 256 . The error calculation adder 255 adds the added signal ya (n) and the decision signal yb (n) with each other, generating an equalization error signal ER (ya (n) -yb (n)). The coefficient calculator 256 receives the equalization error signal ER from the error calculation adder 255 and calculates the mean square error of the equalization error signal ER. The coefficient calculator 256 calculates the coefficients C1-C5 in such a way as to minimize the calculated mean square error. The coefficient calculator 256 includes a plurality of calculation parts which are provided in connection with the coefficients C1-C5.

Fig. 20 is a schematic block diagram of the coefficient calculating part for the coefficient C1. Since the coefficient calculating parts for the remaining coefficients C2-C5 have the same structures as the coefficient calculating part for the coefficient C1, they are not shown in the diagram.

The coefficient calculator 256 includes two registers 256 a and 256 b, a multiplier 256 c, two adders 256 d and 256 e, a gate circuit 256 f, a step size setting circuit 256 g and an initial value setting circuit 256 h.

The first register 256 a samples data D1 stored in the FIR equalizer 236 d in the first register 251 a in synchronism with the sampling clock SCK and supplies the multiplier 256 c with the sampled data D1.

The multiplier 256 c multiplies the sampled data D1 from the first register 256 a with the equalization error signal ER and the predetermined step size µ from the step size setting circuit 256 g and supplies the multiplication result (µ.D1.ER) to the first adder 256 d .

The first adder 256 d adds the multiplication result from the multiplier 256 c and the coefficient C1b before an update from the second register 256 b and sends the addition result (C1b + µ.D1.ER) to the gate circuit 256 f.

If a control signal CT from the MPU 17 has an H level, the gate circuit 256 f sends the addition result from the first adder 256 d to the second adder 246 e.

The second adder 256 e is supplied with an initial value CIN from the initial value setting circuit 256 h when the second adder 256 e performs the first operation, and is supplied with "0" instead of the initial value CIN in subsequent operations.

The second adder 256 e sends the initial value CIN to the second register 256 b in the first operation. In the subsequent operations, the second adder 256 e sends the addition result (C1b + µ.D1.ER) from the first adder 256 d to the second register 256 b.

The second register 256 b samples the addition result from the second adder 256 e in synchronism with the sampling clock SCK and supplies the sampled addition result as a new coefficient C1 (C1b + μ.D1.ER) to the first multiplier 252 a of the FIR equalizer 236 d. The first multiplier 252 a multiplies the data D1 by the new coefficient C1.

The signal processor 150 according to the third embodiment has the following advantages.

• 1. The FIR equalizer 236 d supplies the DFE 237 with the equalized digital signal Za (n), which minimizes the mean square error between the added signal from the adder 237 b and the decision signal from the decision circuit 237 c. The digital signal Za (n) is free from noise that is generated in the analog signal system as a result of conditions of use, manufacturing fluctuations and time-dependent changes. It is therefore unnecessary that Koeffizi ducks of the forward filter 237 a and the feedback filter 237 d, in view of noise derartigem set. In other words, the coefficients of the forward filter 237 a and the feedback filter 237 d only have to be optimized for the characteristics of the FIR equalizer 236 d. This seitigt be the need for a coefficient calculator for the forward filter 237 and a feedback filter 237 is d, so that the circuit area of the DFE 237 is reduced accordingly.
  The coefficient calculator 256 has five coefficient calculating parts in connection with the number of taps of the FIR equalizer 236 d (five in this embodiment). However, the number of taps of the FIR equalizer 236 d is significantly smaller than the number of taps of the forward filter 237 a and the feedback filter 237 d. Therefore, an increase in the circuit area of the DFE 237 connected to the coefficient calculator 256 is suppressed.
• 2. The individual coefficients C1-C5 of the FIR equalizer 236 d are set in order to minimize the mean square error between the added signal ya (n) from the adder 237 b and the decision signal yb (n) from the DFE 237 . That is, since the coefficients C1-C5 of the FIR equalizer 236 d are updated based on the decision result from the DFE 237 , the DFE 237 can make a high-precision decision.

Fourth embodiment

Fig. 21 is a schematic block diagram illustrating a pre-processor 301 and a DFE 237th The pre-processor 301 includes a replica signal generator 258 and an adder 259 . The replica signal generator 258 includes a differential circuit 260 and an FIR filter 261 , as shown in FIG. 22.

The differential circuit 260 contains an adder 260 a and a register 260 b, which serves as a delay circuit. The read signal RD, which corresponds to periodic write data (preamble data) generated by the MPU 17 , is supplied by the head unit 14 to the adder 260 a and the register 260 b and is by the adder 260 a and the register 260 b differentiated.

The FIR filter 261 contains a shift register 262 , which consists of five registers 262 a to 262 e corresponding to the number of taps of the FIR equalizer 236 d, five multipliers 263 a to 263 e, which with the registers 262 a to 262 e are connected, an adder 264 and an output register 265 .

The registers 262 a- 262 e are connected in series, and each register samples the differentiated read signal in synchronism with the sampling clock SCK and supplies the sampled data to the next register and also temporarily holds the sampled data.

The data DA1-DA5 stored in the registers 262 a- 262 e are each supplied to the multipliers 263 a- 263 e. The multipliers 263 a- 263 e each receive the data DA1-DA5 and predetermined coefficients CA1-CA5 and multiply the data DA1-DA5 by the predetermined coefficients CA1-CA5, respectively. The multipliers 263 a- 263 e then deliver the multiplication results to the adder 264 . The coefficients CA1-CA5 are preset in such a way that the read signal RD is equalized in accordance with the write data (preamble data) in accordance with a predetermined target characteristic.

The adder 264 adds the five O 09639 00070 552 001000280000000200012000285910952800040 0002010018871 00004 09520 operation results from the multipliers 263 a- 263 e and supplies the addition result to the register 265 . The addition result of the adder 264 is the digital signal which is determined by equalizing the read signal RD corresponding to the write data (preamble data) in accordance with the predetermined target characteristic.

The register 265 samples the addition result from the adder 264 in synchronism with the sampling clock SCK and supplies the sampled addition result to the adder 259 as a replicate signal zb (n). The replicate signal Zb (n) is the signal that is generated when the DFE 237 equalizes the read signal RD in accordance with known write data with an ideal characteristic.

The adder 259 receives the replica signal Zb (n) from the replica signal generator 258 and the equalized digital signal Za (n) from the FIR equalizer 236 d and generates an error signal err1 (Za (n) -Zb (n)). That is, the adder 259 calculates an error with a value between the replica signal Zb (n) and the equalized digital signal Za (n), which was generated by the FIR equalizer 236 d from the actual read signal RD.

The coefficient calculator 302 receives the error signal err1 from the adder 259 and the equalized error signal ER from the error calculation adder 255 and selects either the error signal err1 or the equalized error signal ER according to a switchover control signal SERC from the MPU 17 . The coefficient calculator 302 calculates the individual coefficients C1-C5 of the FIR equalizer 236 d according to the above-mentioned correlation equations of the LMS algorithm using the selected error signal.

If the error signal is selected err1, the coefficient calculator 302 to calculate each coefficient C1-C5, d to the mean square error between the ent distorted digital signal Za (n) of the FIR equalizer 236 and the replica signal Zb (n) of to minimize the replica signal generator 258 .

If the error signal ER is selected, the coefficient calculator 302 to calculate each coefficient C1-C5, to the mean square error between the ad-founded signal from the adder 237 b in the DFE 237 and the decision signal from the decision circuit 237 c to be minimized.

When the HDC 19 starts to operate and when an error occurs due to an increase in errors, the MPU 17 sets the switching control signal SERC to an H level to select the error signal err1. At this time, when the preamble data is read from the magnetic disk 13 , the MPU 17 of the head unit 14 allows the read signal RD to be supplied to the replica signal generator 258 corresponding to the preamble data. The FIR equalizer 236 d generates the equalized digital signal Za (n) from the read signal RD in accordance with the preamble data and generates an error signal err1 between the equalized digital signal Za (n) and the replicate signal Zb (n). The coefficient calculator 302 calculates the optimal coefficients C1-C5 using the error signal err1.

When the HDC 19 is in normal operation and when there is no error, the MPU 17 sets the switching control signal SERC to an L level to select the equalized error signal ER. At this time, the read signal RD for the preamble data from the head unit 14 is not supplied to the Replikatsi signal generator 258 .

Preprocessor 236 includes AGC loop control circuit 266 and timing recovery PLL 267 . The AGC loop control circuit 266 receives the equalized error signal ER and the error signal err1 and selects one of them according to the switch control signal SERC from the MPU 17 . Based on the selected error signal (on the amplitude error), the AGC loop control circuit 266 adjusts the gain of the AGC 236 a in such a way that the output signal of the AGC 236 a has the optimal amplitude.

When the error signal err1 is selected, the gain of the AGC 236 a is set based on the error signal err1. If the equalized error signal ER is selected, the gain of the AGC 236 a is set on the basis of this equalized error signal ER.

The timing recovery PLL 267 receives the equalized error signal ER (phase error), on the basis of which the timing recovery PLL 267 adjusts the frequency of the sampling clock SCK in such a way that the ADC 236 c performs sampling with the optimal timing.

The signal processor according to the fourth embodiment has the following advantages.

• 1. The replicate signal generator 258 reproduces the equalized digital signal (replicate signal Zb (n)) which was generated from the read signal RD in accordance with the preamble data in accordance with the ideal noise-free characteristic. That is, the replica signal generator 258 generates the ideal noiseless replica signal Zb (n) in synchronism with the equalized digital signal Za (n). If the FIR equalizer 236 d actually generates the equalized digital signal Za (n) from the read signal RD corresponding to the preamble data read by the head unit 14 , this equalized digital signal Za (n) may contain noise that in the Analog system is generated as a result of conditions of use, manufacturing fluctuations and time-dependent changes.

The adder 259 generates the error signal err1 (Za (n) -Zb (n)) between the replicate signal Zb (n) and the actual equalized digital signal Za (n), and the coefficient calculator 302 calculates the optimal coefficients C1- C5 using the error signal err1. Accordingly, the level of the error is accurately determined according to noise. In addition, since the signals do not pass through the DFE 237 , the calculation training time for the coefficients C1-C5 or the time during which the coefficients converge is relatively short.

• 1. The gain of the AGC 236 a is set based on the error signal err1 (Za (n) -Zb (n)), and the time required for the setting is relatively short, since the signals do not go through the DFE 237 .

According to the fourth embodiment, the replicate signal For example, generated according to the sync data instead of the preamble data become. Alternatively, the replicate signal Zb (n) according to who created both the preamble data and the sync data the.

The replicate signal Zb (n) can be generated according to an exclusive training pattern. In this case, the training pattern is prescribed on the magnetic disk 13 . The replica signal generator 258 generates the replica signal Zb (n) from the read signal according to the training pattern.

In the fourth embodiment, the coefficients C1-C5 using the error signal err1 alone be counted.

The calculation of the coefficients C1-C5 can e.g. B. each times when the preamble data is read.  

It should be apparent to those skilled in the art that the above lying invention ver in many other special forms can be embodied without departing from the spirit or scope of the invention to deviate. In particular, it should be understood that the Invention can be embodied in the following forms.

In the third and fourth embodiments, the coefficients C1-C5 of the FIR equalizer may be determined 236 d. In this case, it is preferable to perform a test for setting the coefficients C1-C5 on the basis of the equalized digital signal Za (n) which is free from noise which is caused in the analog signal system due to usage conditions, manufacturing fluctuations and time-dependent Changes are generated.

The third and fourth embodiments may further include a coefficient calculator to adjust the coefficients of the forward filter 237 and a feedback filter of the DFE 237 b 237 by using the equalized error signal ER to have.

This invention can be embodies ver in a semiconductor device, the DFE 237 with the FIR equalizer 236 d has.

The present invention can not only be a celebration plate device, but also to a baseband digital communication system can be adapted with a DFE.

The present examples and embodiments are intended to therefore considered to be illustrative and not restrictive , and the invention is not as set forth herein NEN details limited, but can be within the scope and the correspondence of the appended claims become.

Claims (24)

1. A semiconductor circuit comprising a decision feedback equalizer ( 35 ) for waveform equalizing a corrected input signal and generating a waveform equalized signal, wherein the equalizer compares the waveform equalized signal with a predetermined reference level to a decision signal with first and second decision values and to generate an error signal between the waveform-equalized signal and the decision signal, which semiconductor circuit is characterized by:
a dispersion value calculator ( 37 ) connected to the decision feedback equalizer to calculate a first dispersion value of the decision signal with the first decision value and a second dispersion value of the decision signal with the second decision value using the error signal and a compensation signal using the generate first and second dispersion values; and
an asymmetry compensator ( 34 ) connected to the decision feedback equalizer and the dispersion value calculator to receive an input signal and correct an asymmetry of the input signal according to the compensation signal and to supply the corrected input signal to the decision feedback equalizer. 2. Semiconductor circuit according to claim 1, characterized in that the input signal has a predetermined amplitude den range and the asymmetry compensator ( 34 ) segments the predetermined amplitude range of the input signal into a plurality of sub-areas and corrects the asymmetry of the input signal according to the compensation signal sub-area by sub-area . 3. Semiconductor circuit according to claim 2, characterized in that the asymmetry compensator has a plurality of intended for the respective partial areas partial compensators ( 711 - 716 ) for correcting the asymmetry of the input signal in the respective partial areas. 4. Semiconductor circuit according to claim 3, characterized records that each partial compensator has a compensation value for the input signal with a smaller amplitude than that that of the next section. 5. Semiconductor circuit according to one of claims 1 to 4, characterized in that the dispersion value calculator contains ent:
a square circuit ( 51 ) for calculating a square of the error signal;
a first dispersion value calculator ( 52 ) connected to the square circuit to calculate the first dispersion value by integrating the square and the first decision value of the decision signal;
a second dispersion value calculator ( 53 ) connected to the square circuit for calculating the second dispersion value by integrating the square and the second decision value of the decision signal; and
a calculation circuit ( 54 ) connected to the first and second dispersion value calculators to calculate the compensation signal as the difference between the first dispersion value and the second dispersion value. 6. Semiconductor circuit according to one of claims 1 to 5, characterized by:
an automatic gain control (AGC) loop ( 36 , 49 , 50 ) for receiving the input signal and generating an input signal with an optimal gain using the error signal, wherein the asymmetry compensator receives the input signal with the optimal gain as its input signal; and
a phase locked loop (PLL) ( 46 , 47 , 48 ) for generating a sampling clock using the error signal, wherein the decision feedback equalizer samples the decision signal according to the sampling clock. 7. The semiconductor circuit according to claim 6, characterized records that AGC loop and PLL operations stops or is held while the dispersion value Computer generates the compensation signal.   8. The semiconductor circuit according to claim 6, characterized records that if the dispersion value calculator the compensation tion signal generated, an operation of the AGC loop control is a change in the gain of the input reduce signals, and an operation of the PLL controlled to make a change in the frequency of the sampling clock reduce. 9. A semiconductor circuit according to claim 6, characterized records that the input signal is a first pattern data signal contains that for operations of the AGC loop and the PLL ge is suitable, and a second sample data signal, which is for Opera tioen the dispersion value calculator is suitable. 10. A semiconductor circuit according to claim 9, characterized records that the first pattern data signal is a periodic Contains pattern data signal and the second pattern data signal contains a random pattern data signal. 11. Semiconductor circuit, comprising an analog-to-digital (A / D) converter ( 33 ) for converting an analog input signal into a digital input signal with an intermediate reference voltage as a baseline and a decision feedback equalizer ( 35 ) for waveform equalizing an corrected digital input signal and generating a waveform equalized signal, wherein the equalizer compares the waveform equalized signal to a predetermined reference level and generates a decision signal with first and second decision values and an error signal between the waveform equalized signal and the decision signal, which Semiconductor circuit is characterized by:
a dispersion value calculator ( 37 ) connected to the decision feedback equalizer to calculate a first dispersion value of the decision signal with the first decision value and a second dispersion value of the decision signal with the second decision value using the error signal and a compensation signal using the generate first and second dispersion values;
an asymmetry compensator ( 34 ) connected between the decision feedback equalizer and the A / D converter to receive the compensation signal from the dispersion value calculator, correct an asymmetry of the digital input signal using the compensation signal and the corrected digital input signal at the decision to provide feedback equalizers;
a baseline compensation detector ( 112 , 113 , 17 ) connected to the decision feedback equalizer for calculating a baseline compensation value using the waveform equalized signal; and
a digital-to-analog (D / A) converter ( 117 ) connected to the baseline compensation detector and the A / D converter to generate the intermediate reference voltage according to the baseline compensation value and the intermediate reference voltage to the A / D - deliver converters. 12. A semiconductor circuit according to claim 11, characterized in that the baseline compensation detector contains:
a counter ( 124 ) for counting a sampling clock when the waveform equalized signal is in a predetermined level range around the predetermined reference level; and
a calculation circuit ( 17 ) for calculating the baseline compensation value based on a count value of the counter. 13. Semiconductor circuit, characterized by:
a finite impulse response (FIR) -Entzerrer (236 d) for equalizing a waveform of a digital signal to produce an equalized digital signal; and
a decision feedback equalizer ( 237 ) connected to the FIR equalizer for comparing the equalized digital signal with a predetermined reference level to produce a decision signal. 14. Semiconductor circuit according to claim 13, characterized by:
an amplifier with automatic gain control (AGC) ( 236 a) for amplifying an analog signal to produce an amplified analog signal;
a connected to the AGC analog filter (236 b) for Fil tern of the amplified analog signal to produce a filtered analog signal; and
an analog-digital (A / D) converter ( 236 e) connected to the analog filter and FIR equalizer in order to convert the filtered analog signal into the digital signal and to supply the digital signal to the FIR equalizer, wherein the equalized digital signal generated by the FIR equalizer corresponds to a corresponding transmission line characteristic according to a characteristic of a transmission line from the AGC to the analog filter. 15. A semiconductor circuit according to claim 13 or 14, characterized in that the FIR equalizer generates the equalized digital signal using a predetermined coefficient; and
the semiconductor circuit further includes a coefficient update circuit connected to the decision feedback equalizer and the FIR equalizer to update the predetermined coefficient based on the decision signal and to supply the updated coefficient to the FIR equalizer. 16. A semiconductor circuit according to claim 15, characterized in that the coefficient update circuit contains:
an error calculator ( 255 ) connected to the decision feedback equalizer for calculating an error between the equalized digital signal and the decision signal to generate an error signal; and
a coefficient calculator ( 256 ) connected to the error calculator and the FIR equalizer to calculate the predetermined coefficient using the error signal. 17. A semiconductor circuit according to claim 16, characterized records that the coefficient calculator the predetermined Coefficients calculated so that a mean square Error between the equalized digital signal and the Ent divorce signal is minimized.   18. Semiconductor circuit according to one of claims 13 to 17, characterized in that the decision feedback contains equalization:
a forward filter ( 235 a) connected to the FIR equalizer for filtering the equalized digital signal using a first coefficient in order to generate a filtered digital signal;
an adder ( 237b ) connected to the forward filter for adding the filtered digital signal and a feedback signal to produce an added signal;
an adder connected to the decision circuit (237 c) gene for comparing the added signal with the voted vorbe reference level to the decision signal to erzeu; and
a ver with the decision circuit and the adder bundenes feedback filter (237 d) for filtering the decision signal by using a second coefficient to produce the feedback signal, and supplying the feedback signal to the adder, said first and second coefficients for a characteristic of the FIR - Equalizers are set at the optimum. 19. Semiconductor circuit according to one of claims 13 to 18, characterized in that the FIR equalizer generates the ent equalized digital signal using a predetermined coefficient; and
the semiconductor circuit further comprises a coefficient update circuit ( 258 , 259 , 302 ) for generating an error signal between an equalized digital replica signal corresponding to predetermined pattern data and the equalized digital signal generated by the FIR equalizer and corresponding to the predetermined pattern data, and updating the predetermined coefficient of the FIR equalizer using the error signal. 20. A semiconductor circuit according to claim 19, characterized in that the coefficient update circuit contains:
a replica signal generator ( 258 ) for receiving an analog signal corresponding to the predetermined pattern data and generating an equalized digital replica signal;
an error calculator ( 259 ) connected to the replica signal generator and the FIR equalizer for calculating an error between the equalized digital replica signal and the equalized digital signal from the FIR equalizer to generate the error signal; and
a coefficient calculator ( 302 ) connected to the error calculator and the FIR equalizer to calculate the predetermined coefficient using the error signal. 21. Decision feedback equalizer, characterized by:
a finite impulse response (FIR) -Entzerrer (236 d) for equalizing a waveform of a digital signal to produce an equalized digital signal;
a forward filter ( 235 a) connected to the FIR equalizer for filtering the equalized digital signal using a first coefficient in order to generate a filtered digital signal;
an adder ( 237b ) connected to the forward filter for adding the filtered digital signal and a feedback signal to produce an added signal;
an adder connected to the decision circuit (237 c) gene for comparing the added signal with a reference level vorbe agreed to a decision signal to erzeu; and
a ver with the decision circuit and the adder bundenes feedback filter (237 d) for filtering the decision signal by using a second coefficient to produce the feedback signal, and supplying the feedback signal to the adder. 22. A decision feedback equalizer according to claim 21. characterized in that the first and second Koeffizi optimal for a characteristic of the FIR equalizer are posed. 23. A semiconductor device comprising a decision feedback equalizer ( 35 ) for waveform equalizing a corrected input signal and generating a waveform equalized signal, wherein the equalizer compares the waveform equalized signal with a predetermined reference level to provide a decision signal with first and second To generate decision values and an error signal between the waveform-equalized signal and the decision signal, which semiconductor device is characterized by:
a dispersion value calculator ( 37 ) connected to the decision feedback equalizer to calculate a first dispersion value of the decision signal with the first decision value and a second dispersion value of the decision signal with the second decision value using the error signal and using the first and second Dispersion values to generate a compensation signal; and
an asymmetry compensator ( 34 ) connected to the decision feedback equalizer and the dispersion value calculator to receive an input signal and correct an asymmetry of the input signal according to the compensation signal and to supply the corrected input signal to the decision feedback equalizer. 24. A semiconductor device comprising an analog-digital (A / D) converter ( 33 ) for converting an analog input signal into a digital input signal with an intermediate reference voltage as a baseline and a decision feedback equalizer ( 35 ) for waveform equalizing a corrected one digital input signal and generating a waveform equalized signal, wherein the equalizer compares the waveform equalized signal with a predetermined reference level and generates a decision signal with first and second decision values and an error signal between the waveform equalized signal and the decision signal, which semiconductor device is characterized by:
a dispersion value calculator ( 37 ) connected to the decision feedback equalizer to calculate a first dispersion value of the decision signal with the first decision value and a second dispersion value of the decision signal with the second decision value using the error signal and using the first and second Dispersion values to generate a compensation signal;
an asymmetry compensator ( 37 ) connected between the decision feedback equalizer and the A / D converter to receive the compensation signal from the dispersion value calculator, correct an asymmetry of the digital input signal using the compensation signal, and correct the digital input signal at the decision to provide feedback equalizers;
a baseline compensation detector ( 112 , 113 , 17 ) connected to the decision feedback equalizer for calculating a baseline compensation value using the waveform equalized signal; and
a digital-to-analog (D / A) converter ( 117 ) connected to the baseline compensation detector and the A / D converter to generate the intermediate reference voltage according to the baseline compensation value and to supply the intermediate reference voltage to the A / D converter to deliver.