DE10013553A1 - Delay device for delaying incoming transmission signals in electronic instrument, has delay elements operating on power supply voltages, connected in series, and with a switch unit that outputs one of outputs of delay elements - Google Patents

Abstract

The device comprising delay element (DL) which operates on voltages Vdd and Vss includes addition circuit (ADC) that outputs to output of delay element a predetermined voltage (Vc) that is larger than the voltage Vss and smaller than Vdd. The delay element includes several delay elements in series with each other and several addition circuits, each connected to one of the outputs of the delay elements. A digital circuit included outputs one of the voltages of two possible values in correspondence with the input voltage. The addition circuit outputs a voltage similar to a threshold voltage that the digital circuit output inverts from one of the outputs of the two possible values to another. The addition circuit has a low impedance, smaller than the output impedance of the delay element, and ranges from half to a quarter of the output impedance of the delay element. Independent claims have been made for: 1. Semiconductor testing device for testing semiconductor device; 2. Oscilloscope that visualizes input signal; and 3. Testing device for delaying an incoming signal.

Description

The present invention relates to a ver delay device, a semiconductor test device, a semiconductor device and an oscilloscope, and in particular on a delay device, a Semiconductor test device, a semiconductor device and an oscilloscope with a supplementary scarf device are provided which have a predetermined voltage applies to a delay element.

Fig. 1 shows the delay device D12 as re levante prior art. The delay device D12 contains several delay elements DL in series with one another. The incoming transmission signal is delayed by each delay element DL, which generates a delay time Td.

Fig. 2 shows the current flowing in the delay device D12. After a unit pulse is supplied to the delay device D12 as shown in Fig. 2 (A), the current supplied to the delay element DL changes such that it flows in a pulse burst as shown in Fig. 2 (B). The time period during which the current flows is equivalent to the delay time Td. When successive pulses are supplied to the delay device D12, as shown in FIG. 2 (C), while the initial current generated by the first pulse flows, another current generated by the following pulse also flows, as in FIG. 2 (D) is shown. When the current of two or more delay elements DL changes simultaneously in this way, the sum of the current flowing in the delay device D12 changes as shown in Fig. 2 (E). Since the change in the current changes the power supply voltage Vdd and Vss of the delay device D12, the accuracy of the delay time Td of the delay device D12 is reduced.

Fig. 3 shows another delay device D12 as relevant prior art. The delay device D12 contains several selection elements SEL in series with each other, as well as several delay elements DL, each of which delays the incoming transmission signal and it leads to a subsequent selection element SEL. The delay element DL has one or more inverters in series with one another. The selector SEL selectively outputs the signal that passes through the delay element DL and the signal that does not pass through it. The times of the electrical power consumed in the delay device D12 differ depending on the selection by the selector SEL. If, for example, all selection elements SEL select the output signals of the delay elements DL, the transmission signal proceeds slowly forward; accordingly, when the selector closest to the output terminal SEL consumes the electric power, the selector closest to the input terminal SEL consumes the electric power. That is, the electrical power is consumed with two or more selector elements SEL. The result is a reduction in the accuracy of the delay time because the power supply voltage for the delay device D12 is different when the electric power is consumed with two or more selector elements SEL than when it is consumed with only one selector element SEL.

Fig. 4 shows a circuit which is the delay element DL of FIG. 3 is electrically equivalent. A wiring capacitance CL occurs in the signal line LIN, which connects the driver circuit DR and the receiving circuit RC, while an input capacitance CG occurs at the input terminal of the receiving circuit RC. The input capacitance CG is proportional to the number of receiving circuits RC to be connected, while the wiring capacitance CL is proportional to the length of the signal line LIN. As the input capacitance CG and the wiring capacitance CL increase, passing the signal through the delay device D12 requires a larger current. The increase in the current increases the change in the current as shown in Fig. 2 (E), whereby the accuracy of the delay time Td decreases.

When the power supply voltage changes due to the operation of the driver circuit DR changes sharply,  an electromagnetic wave noise is abge shine. If the change in the power supply current and the power supply voltage increases, because the signal line LIN is long, this takes away from the delay device D10 radiated electro magnetic wave noise too. That from that electronic instrument emitted electromagnetic table wave noise must be below a given Levels, so it is therefore necessary that the Occurrence of electromagnetic wave noise in the one provided with the delay device D10 to prevent electronic instrument.

It is the object of the present invention, a Delay device, a semiconductor test device device, a semiconductor device and an oscilloscope to create the disadvantages of the prior art Overcome technology. This task is performed by the in The combination described in the independent claims solved. The dependent claims define white tere advantageous and exemplary combinations of present invention.

In one aspect of the present invention, ei ne delay device provided that a occurring transmission signal is delayed, and which has: a delay element with the Leis line supply voltages Vdd and Vss is operated and thereby delaying the transmission signal, wherein voltage Vdd is greater than voltage Vss; and a supplementary circuit leading to the output signal of the delay element a predetermined Outputs voltage that is greater than the voltage Vss and is less than the voltage Vdd.

The delay device preferably has white  then several delay elements in series other, and several supplementary circuits, each with one of the outputs of the multiple delay elements elements are connected. Another advantage is that Delay device on: a switch unit, which one of the output signals of the multiple delays outputs elements, the supplementary scarf device the predetermined voltage to the output signal the switch unit outputs.

It is preferred that the delay element is a digital circuit contains that in accordance with an input voltage one of two output outputs voltages of two possible values. The he complementary circuit should also output a voltage which is essentially equal to a threshold voltage which is the output signal of the digital circuit from one of the output voltages of two possible Values to the other of them inverted.

It is preferred that the supplementary circuit approximate has a mean voltage of the voltage Vss and the Output voltage Vdd.

It is preferred that the supplementary circuit is a has low impedance, smaller than the output impedance danz of the delay element. Should be even more preferred te the output impedance of the supplementary circuit in Range from half to a quarter of the off Gang impedance of the delay element.

It is preferred that the supplementary circuit be a stes logic gate, the inverse of an input signal outputs, and contains a feedback circuit, the egg NEN input terminal of the first logic gate and connects an output terminal thereof. Even before  Zugter the delay element can a second logi included gate, the first logic gate ter has a ratio that is essentially the same is the ratio of the second logic gate. In the same way, and more preferably, contains the first logic gates an inverter, a NAND gate and a NOR gate. In the same way and more preferably ent the delay element holds a second inverter, wherein the inverter has a ratio that in We substantially equal to the ratio of the second inv ters is.

The delay device preferably has white further on: several delay elements in series with each other and a selector that is one of the meh selects other delay elements to which the Transmission signal is entered. The supplement circuit gives a predetermined voltage depending from the input transmission signal, which is greater than the voltage Vss and less than the voltage is Vdd.

The delay device preferably has white then on: several capacitors, which the elec store trical charge of the transmission signal that is output by the delay element; and meh rere switches, which the multiple capacitors too switch the output of the delay element. It is more preferred that the capacitor ent holds: a P-type FET in which the voltage Vdd is applied to a gate of the P-type FET where at least the drain or the source of the FET from P type is connected to the gate, and the other of connected to the switch; an FET from N type, in which the voltage Vss to a gate of the N-type FET is applied while at least the  Drain or the source of the N-type FET with the gate and the other of these connected to the switch are.

The capacitor may also include: an FET P-type, in which the voltage Vdd to a gate of the P-type FET, and the switch the Drain and the source of the P-type FET to the output of the delay element switches; a FET from the N- Type in which the voltage Vss is applied to a gate of the FET of the N type and the switch is the drain and the source of the N-type FET to the output of the Delay element switches; an N-type FET, at which the voltage Vss to the drain and the Source of the N-type FET is applied and a gate the N-type FET is connected to the switch; egg N-type FET at which the voltage Vss is on a gate of the N-type FET and a substrate and the switch is the drain and the source of the N-type FET to the output of the delay element switches.

The capacitor can still contain: one P-type FET in which the voltage Vdd on P-type FET gate and substrate applied and a switch switches the drain and source of the P-type FET to the output of the delay element switches; an N-type FET in which the span voltage Vss to the drain and source of the FET from N- Type and a substrate is applied and a gate of the N-type FET is connected to the switch; and egg P-type FET at which the voltage Vdd is on the drain and source of the P-type and FET Substrate is applied and a gate of the P-type FET is connected to the switch.  

According to another aspect of the present invention a semiconductor test device is provided which a semiconductor device tests and has: one Pattern generator that generates a test pattern that is in the semiconductor device is to be input; egg ne delay unit, which a delay clock generates a delay value corresponding to ei operation characteristics of the semiconductor device tung has; a molded test generator ster, which creates a shaped test sample by For of the test sample based on the delay clock rate; a device insertion unit which is used for Attach the semiconductor device and for input the molded test sample is used therein; and a comparator that judges whether the half conductor device is good or not based ge in response to the shaped test specimen of output of the semiconductor device signals.

The delay unit contains a delay element ment, which with two power supply voltages Vss and Vdd is operated, the voltage Vss is less than the voltage Vdd. The delay element delays the input clock by the delay value to generate the delay clock. The Delay unit also contains a supplement circuit that outputs a predetermined voltage, which is greater than the voltage Vss and less than the voltage is Vdd.

It is preferred that the delay unit continue hin contains: several delay elements in series with each other and several supplementary circuits that each with one output of the multiple delay elements are connected.  

It is preferred that the delay element is a digital circuit which contains one of output voltages with two possible values depending outputs from the input voltage. The supplement circuit outputs a voltage that is essentially is equal to a threshold voltage that the output the digital circuit from one of the output span of the two possible values to the other inverted from this.

According to another aspect of the present invention a semiconductor device is provided which a semiconductor test unit that contains the semi-lead device examines which comprises: a semi-lead device unit and a semiconductor test Ness. The latter contains a delay the time behavior of a test sample testifies that ver for testing the semiconductor test unit is applied. This delay unit contains a Delay element with two voltages Vdd and Vss is operated, the voltage Vdd being greater than the voltage Vss, and the time behavior by Delay of the input clock determined. The delays unit also contains a supplementary circuit, which a predetermined voltage depending on outputs the output signal of the delay element, which is greater than the voltage Vss and less than the voltage is Vdd.

It is preferred that the delay unit continue several delay elements and several add contains control circuits with outputs of meh reren delay elements are connected.

It is preferred that the delay element is a  digital circuit that includes one of output tensions of two possible values in agreement output with an input voltage. The compl The control circuit also outputs a voltage that is in the We is substantially equal to a threshold voltage that the output of the digital circuit from one of the Output voltages of the two possible values for the other of them inverted.

According to yet another aspect of the present Er Invention is provided an oscilloscope, which a Makes input signal visible, and which has: a delay unit that has a delay clock generated based on an input clock; one A / D converter, which is an analog / digital conversion of the Input signal based on the time behavior of the delay clock; a time interval lator, which as a delay time differs the time difference between the input signal and the Measures output of delay clock; a processor, of the data which is used to display the input signals based on data from the A / D Converters were generated, and the delay time ver be applied; and a display unit which the Input signal based on that of the process sor generated data displays.

The delay unit contains a delay element ment with two power supply voltages Vss and Vdd is operated, which ver the input clock hesitates to generate the delay clock, where the voltage Vdd is greater than the voltage Vss. The Delay unit also contains a supplement circuit which outputs a predetermined voltage, which are greater than the voltage Vss and less than that Voltage is Vdd.  

It is preferred that the delay unit continue several delay elements and several add control circuit with the outputs of several Delay elements are connected contains. It is more preferred that the delay element a di gitale circuit that contains one of output span of two possible values depending on outputs the input voltage. The supplementary circuit outputs a voltage that is essentially the same a threshold voltage that is the output of the di gital circuit from one of the output voltages of the two possible values to the other of them in vertical.

According to yet another aspect of the present Er a delay device is provided, which delays an incoming transmission signal, and which comprises: a delay element connected with two power supply voltages Vdd and Vss be is driven and that the transmission signal delays device, the voltage Vdd being greater than the voltage Vss is; and a supplementary circuit leading to a Output of the delay element a predetermined Outputs voltage that is greater than the voltage Vss and is less than the voltage Vdd. The supplement circuit includes a P-type FET and an FET of the N type. A forward bias is on a gate of the P-type FET and a gate of the N-type FET placed.

The delay device preferably contains white terhin a cutting circuit, which between the Delay element and the supplementary circuit flow cutting electricity.  

According to yet another aspect of the present Er a delay device is provided, which delays an incoming transmission signal, and which comprises: a delay element connected with Power supply voltages Vdd and Vss operated is and that the transmission signal is delayed, wherein voltage Vdd is greater than voltage Vss; and an additional circuit that leads to an output of the Delay element from a predetermined voltage there that is greater than the voltage Vss and less than the voltage is Vdd. The supplementary circuit contains a voltage source which the predetermined span output.

It is preferred that the supplementary circuit continue contains a low impedance buffer circuit, which is the impedance of the from the voltage source given voltage.

The delay device preferably contains white terhin a cutting circuit, which between the Delay element and the supplementary circuit flow cutting electricity.

According to yet another aspect of the present Er a delay device is provided, which delays an incoming transmission signal, and which comprises: a delay element connected with Power supply voltages Vdd and Vss operated is, and that delays the transmission signal, wherein voltage Vdd is greater than voltage Vss; and an additional circuit which leads to an output of the Delay element from a predetermined voltage there that is greater than the voltage Vss and less than the voltage is Vdd. The supplementary circuit contains a NAND gate and a feedback circuit that  an input terminal of the NAND gate with a Output connector from this connects.

It is preferred that the NAND gate apply control contains a control signal, that between the delay element and the Er complementary circuit current and the Er complementary circuit cuts off flowing current.

According to yet another aspect of the present Er a delay device is provided, which delays an incoming transmission signal, and which comprises: a delay element connected with Power supply voltages Vdd and Vss operated is, and that delays the transmission signal, wherein voltage Vdd is greater than voltage Vss; and an additional circuit which leads to an output of the Delay element from a predetermined voltage there that is greater than the voltage Vss and less than the voltage is Vdd. The supplementary circuit contains a NOR gate and a feedback circuit, which an input terminal of the NOR gate with an off connection from this connects.

It is preferred that the NOR gate apply control has a control signal which is fed between the delay element and the add circuit and the current flowing into the supplement circuit cuts off current flowing.

According to yet another aspect of the present Er a delay device is provided, which delays an incoming transmission signal, and which comprises: a delay element which with Power supply voltages Vdd and Vss operated is and that the transmission signal is delayed, wherein  voltage Vdd is greater than voltage Vss; and an additional circuit that leads to an output of the Delay element from a predetermined voltage there that is greater than the voltage Vss and less than the voltage is Vdd. The supplementary circuit is included connected to one end of the delay element.

The invention is described below with reference to FIGS guren illustrated embodiments he closer purifies. Show it:

Fig. 1 a delay device according to the prior art,

Fig. 2, the signal waves in the Verzögerungsvorrich processing according to FIG. 1,

Fig. 3 shows another delay device in the prior art,

Fig. 4 shows the electrical equivalent circuit of Ver deceleration circuit according to Fig. 3,

Fig. 5 is a semiconductor tester according to the prior lying invention,

Fig. 6 shows the structure of the delay circuit 100 in Fig. 5,

Fig. 7 shows the structure of the delay means D10, which is used for the delay circuit 100,

Fig. 8 shows the signal waves in the Verzögerungsvorrich tung D10 in FIG. 7,

Fig. 9 shows an example of the delay means D10,

Fig. 10 is an example of the delay means D10,

Fig. 11, the operation of the delay means D10,

Fig. 12 through current Ih1 and the Leistungszu tracking current Ih and I1, the device approximately in the tarry flows D10,

Fig. 13 shows the relationship between the input voltage Vin and the power supply current Ih and I1,

Fig. 14 is an equivalent circuit of the delay device D10,

Fig. 15 shows the output signals of the addition circuit and the receiving circuit RC ADC,

Fig. 16 is another delay device D10,

Fig. 17 is a another delay device D10,

Fig. 18 is another delay device D10,

Fig. 19 shows the improvement of the delay means D10 of Fig. 18,

FIG. 20 is another delay device D10,

Fig. 21 shows an example for the switches SW10 and SW12,

FIG. 22 is another delay device D10,

Fig. 23 is an example of the switches SW20 and SW22,

Fig. 24 is an example of the capacitors C10, C12, C14, C16, C18 and C20,

Fig. 25 shows a configuration of the ADC supplement circuit,

Fig. 26 shows a different configuration of the supplementary circuit ADC,

Fig. 27 is a that of FIG. 26 equivalent configuration,

Fig. 28 shows a different configuration of the supplementary circuit ADC,

Fig. 29, the addition circuit ADC, which is provided with the cutting circuit CUT,

Fig. 30, the cutting CUT circuit which is provided with the switch element ANS,

Fig. 31, the addition circuit ADC of FIG. 25, which is provided with the cutting circuit CUT,

32, the addition circuit ADC, which is provided with the cutting circuit CUT contains Fig. The low impedance buffer circuit LOW and the midpoint voltage source EJV,

Fig. 33 is a another delay device D10,

Fig. 34 the configuration of the NAND gate USAGE Denden addition circuit ADC,

Fig. 35 is a another delay device D10,

Fig. 36 is an example provided with the NOR gate circuit to ADC supplement,

Fig. 37 is another supplement circuit ADC,

Fig. 38, the semiconductor device 96 comprising the Halbleiterprüfeinheit 97, devices which checked semiconductor, and

Fig. 39, the configuration of the oscilloscope.

Fig. 5 is a block diagram showing an embodiment of the semiconductor test apparatus. The semiconductor test device includes a pattern generator 90 , a shaped pattern generator 92 , a device insertion unit 94, and a comparator 95 . The shaped pattern generator 92 includes a delay circuit 100 .

The semiconductor device 93 is inserted into the device insertion unit 94 . The pattern generator 90 generates pattern data that are supplied to the semiconductor device 93 and expectation data that the semiconductor device 93 should output in response to the pattern data. The pattern generator 90 outputs the pattern data to the shaped pattern generator 92 and the expectation data to the comparator 95 . Furthermore, the pattern generator 90 outputs a timing signal to the delay circuit 100 to instruct the delay circuit 100 to generate a delay clock with a predetermined delay value depending on the operation characteristic of the semiconductor device 93 .

The delay circuit 100 generates a delay clock having a delay value indicated by the timing signal. The generator 92 forms the pattern data on the basis of the delay provided by the delay circuit 100 clock. The generator 92 outputs the shaped pattern data to the device inserting unit 94 according to the operation characteristic of the semiconductor device 93 . In response to the shaped pattern data, the semiconductor device 93 outputs a signal to the comparator 95 . The comparator 95 judges whether the semiconductor device 93 is good or not by comparing this signal and the expected data.

Fig. 6 shows the structure of the delay circuit 100. The delay circuit 100 has a reference clock generator 120 and a delay device D10. The reference clock generator 120 generates a reference clock. The delay device D10 is supplied with the reference clock data. The delay device D10 also receives the timing signal from the pattern generator 90 . The delay device D10 delays the reference clock by the delay value determined by the time setting signal, whereby the delay clock is generated.

FIG. 7 shows the structure of the delay device D10 used for the delay circuit 100 shown in FIG. 5. In comparison with FIG. 1, FIG. 7 shows the delay device D10 without the circuit that controls the delay time based on the timing signal. The delay device D10 contains a plurality of delay elements DL in series with one another and a plurality of supplementary circuits ADC which are connected to the respective outputs of the delay elements DL. The supplementary circuits ADC contain an inverter INV with a CMOS circuit and an associated feedback circuit NF. The delay elements DL output one of the power supply voltages Vdd and Vss depending on the input signal, the voltage Vdd being larger than the voltage Vss. The supplementary circuits ADC output to the outputs of the delay elements DL a voltage which is approximately in the middle between the voltages Vss and Vdd. Therefore, when the voltage output from the delay element DL is larger than the medium voltage VC, the medium voltage VC is applied to the voltage, thereby hindering the increase in the voltage. Alternatively, when the voltage output from the delay element DL is less than the voltage VC, the medium voltage VC is applied to this voltage, thereby hindering the decrease in the voltage. In this way, the medium voltage VC reduces the change in the voltage output from the delay element DL.

Fig. 8 shows the waves of the current flowing in the delay device D10. After a unit pulse signal is input to the delay device D10 as shown in Fig. 8 (A), the current flows in a pulse burst through the delay device D10 as shown in Fig. 8 (B). Since the supplementary circuit ADC gives the delay element DL the medium voltage VC, the through current Ih1 flows from the voltage Vdd to the voltage Vss. The total current is the sum of this through current and the operating current which flows in the delay elements DL due to the input signal. The addition of the medium voltage VC to the voltage output by the delay element DL reduces the change in this voltage, which results in a decrease in the change in the current consumed to drive the signal compared to the prior art. Even if successive pulses are input as shown in Fig. 8 (C), the amplitude of the current consumed by each pulse is small as shown in Fig. 8 (D). Therefore, the change in the current of the delay device D10 is smaller compared to the prior art, as shown in Fig. 8 (E). Furthermore, the change in the voltage of the delay device D10 is small, which increases the accuracy of the delay time. An improvement in the accuracy of the delay time of the delay device D10 increases the accuracy of the delay circuit 100 , which in turn increases the accuracy of the semiconductor test device shown in FIG. 5. Furthermore, the change in the power supply voltage is decreased, resulting in a decrease in the electromagnetic wave noise radiated from the delay device D10.

Fig. 9 shows an example of the delay means D10. The driver circuit DR and the receiving circuit RC correspond to the delay element DL according to FIG. 7. The signal line LIN is connected to the supplementary circuit ADC. The supplementary circuit ADC contains an inverter with a CMOS circuit and a feedback circuit NF. For a signal transmission at high speed, an overshoot or an undershoot can occur in the signal wave if the signal advancing along the signal line LIN is reflected or absorbed by the receiving circuit RC. In order to reduce any overshoot or undershoot, the supplementary circuit ADC can be connected to the end of the signal line LIN.

Fig. 10 shows an example of the structure of tarry approximately device D10. Both the driver circuit DR and the receiving circuit RC use an inverter INV which is provided with the CMOS circuit. The supplementary circuit ADC can also contain an inverter INV with the CMOS circuit and a feedback circuit NF. This supplementary circuit ADC stabilizes the voltage at the common connection point J of the input and output connection of the inverter INV in order to set it approximately in the middle between the voltages Vdd and Vss. The reason for this follows with reference to FIG. 11.

Fig. 11 shows the direct transfer characteristic Y, ie, the relationship between the input voltage and the output voltage of the inverter INV. Since the inverter INV inverts logically, the characteristic drops around the logic threshold. Here we get a feedback by short-circuiting the input and output connection or by connecting them using a resistor that equalizes the input voltage and the output voltage. Accordingly, by drawing a straight line X with Vin = Vout that overlaps the curved line Y, the output voltage at the intersection of the straight line X and the curved line Y is equalized. The intersection is the point where the output voltage is inverted in the direct transmission characteristic, that is, the point which is equivalent to the logic threshold of the inverter INV. When the on-resistances of the P-type FET Qp and the N-type FET QN are equivalent, the intersection is at the midpoint between the voltage Vss and the voltage Vdd.

Here the on-resistance is not linear. He is ge to put it more precisely, by saying that the Koeffi cient β is used as an index which shows whether the drain current of the FET flows or not. The drain current coefficient β is proportional Constant, which is determined by the size of the MOS FET and whose geometry ratio is determined.

Assuming that the coefficients J3 of the N-type FET Qn and the P-type FET Qp are equal to βn and βp, we get

βn = (W / Leff). (εox / Tox) .µn, eff

βp = (W / Leff). (εox / Tox) .µp, eff

where βn is the drain current coefficient of the FET Qn from N type, βp denotes the drain current coefficient FET Qp designates P type, W designates the gate width, LF denotes the effective gate length, Tox the thickness of the gate oxidation film, εox the Dielek tricity constant of the gate oxidation film net, µn, eff the effective mobility of the electron designated, and µp, eff the effective mobility of the Designated Loches.

Using the coefficient, the drain current of the MOS FET is expressed as follows.

If Vds ≦ Vgs-Vt, Id = β {(Vgs-Vt) Vds- (1/2) (Vds ² )}

If Vds <Vgs-Vt, Id = (1/2) β (Vgs-Vt) ²

For silicon, the mobility of the hole is almost that Half of that of the electrons; therefore if the N-type FET Qn and P-type FET Qp each other are of the same shape on the assumption that the Thresholds are the same as each other in the FET Qn of the N-type current flowing can be twice as large the current flowing in the P-type FET Qp. The one The resistance of the N-type FET Qn is half that that of the P-type FET Qp.

In general, the coefficients βn and βp are set to be the same as each other, or the shapes (W, H) are set to be the same as each other. A change in the beta ratio βR, ie the ratio of the coefficients βn and βp by ten times or one tenth results in the curved line Y1 or Y2 in FIG. 11. Here the curved line Y1 can be set with βn <βp (βR = 10), and the curved line Y2 can be set with βn <βp (βR = 0.1). In this case, setting the ratio βR of the inverter INV in the receiving circuit RC equal to that of the inverter in the supplementary circuit ADC enables the threshold voltage inverting the receiving circuit RC to be equal to the medium voltage Vc. Accordingly, it enables the relationship between the inverter INV in the supplementary circuit ADC and the inverter INV in the receiving circuit RC as described above to be established that the receiving circuit RC processes the incoming signal based on its threshold voltage.

FIG. 12 shows the current Ih or I1 which flows in the driver circuit DR and the supplementary circuit ADC in the delay device D10 according to FIG. 10. The through current Ih1 flowing in the driver circuit DR is also shown. Fig. 12 (A) shows that the input voltage Vin of the driver circuit DR is below the medium voltage Vc. When the input voltage Vin of the driver circuit DR is less than the medium voltage Vc, the current Ih flows from the voltage Vdd of the driver circuit DR to the voltage Vss of the supplementary circuit ADC. At the same time, the through current Ih1 flows from the voltage Vdd of the driver circuit DR to the voltage Vss. Fig. 12 (B) shows that the input voltage Vin of the driver circuit DR is larger than the medium voltage Vc. When the input voltage Vin of the driver circuit DR is greater than the medium voltage Vc, the current I1 flows from the voltage Vdd of the supplementary circuit ADC to the voltage Vss of the driver circuit DR. At the same time, the through current Ih1 flows from the voltage Vdd of the driver circuit DR to the voltage Vss.

FIG. 13 shows the current Ih and the through current Ih1 flowing in the delay device D10 in FIG. 12. Fig. 13 (A) shows the relationship between the voltage Vin and the through current Ih1 flowing from the voltage Vdd of the driver circuit DR to the voltage Vss. Fig. 13 (B) shows the relationship Zvi rule of the input voltage Vin, the current Ih and the current I1. In Fig. 13 (A), when the input voltage Vin is equal to the medium voltage Vc, since the medium voltage Vc is applied to the gates G of the two FETs of the driver circuit DR, the through current Ih1 becomes maximum. Since the input voltage Vin and the medium voltage Vc are the same, no current flows between the driver circuit DR and the supplementary circuit ADC, as shown in Fig. 13 (B).

13 (A), when the input voltage Vin is smaller than the medium voltage Vc, an inverse bias voltage is applied to the gate G of the N-type FET Qn of the driver circuit DR, and a forward bias voltage is applied to the gate G of the P-type FET Qp. The lower the input voltage Vin compared to the medium voltage Vc, the higher the inverse bias voltage, which in turn reduces the through current Ih1. Similarly, the lower the input voltage Vin compared to the medium voltage Vc, the higher the forward bias. The result is that the output voltage of the driver circuit DR becomes larger than the medium voltage Vc. Accordingly, the current Ih flowing from the voltage of the driver circuit DR to the voltage Vss of the supplementary circuit ADC becomes larger.

It follows that, as shown in Fig. 13 (A), when the input voltage Vin is higher than the medium voltage Vc, an inverse bias is applied to the gate G of the P-type FET Qp and a forward bias is applied the gate G of the N-type FET Qn is applied. The higher the input voltage Vin compared to the medium voltage Vc, the higher the inverse bias voltage, which in turn reduces the through current Ih1. The higher the input voltage Vin compared to the medium voltage Vc, the higher the forward bias. The result is that the current Ih flowing from the voltage Vdd of the supplementary circuit ADC to the voltage Vss of the driver circuit DR becomes larger.

Fig. 13 (C) shows the relationship between the input voltage Vin, the through current Ih1 and the current Ih or I1. The sum of the through current Ih1 and the current Ih and the sum of the through current Ih1 and the current I1 are almost constant for the input voltage Vin. Therefore, the change in the current is reduced by outputting the medium voltage Vc from the supplementary circuit ADC to the output of the driver circuit DR.

Fig. 14 shows an equivalent circuit of the delay device D10 shown in Fig. 10. The driver circuit DR is shown equivalent by using the switch SW. Here Rout represents the output impedance of the driver circuit DR. In FIG. 14 the direct resistance of the signal line LIN is neglected. RM denotes the equivalent resistance, which is equal to the output impedance of the supplementary circuit ADC. That is, the supplementary circuit ADC is represented as a circuit in which a resistor is connected to the medium voltage Vc via the equivalent resistor RM. In the driver circuit DR, the switch SW connects to the contact point A and the voltage Vdd is applied to the signal line LIN via the output impedance Rout. At this time, the current I1 flows into the impedance Rt, and a voltage larger than the medium voltage Vc occurs at the common intersection J. By expressing this voltage Vc + E1, the voltage E1 is represented as (Vdd-Vc) Rt / (Rt + Rout).

Alternatively, the switch SW connects to the contact point B and the voltage Vss is sent to the signal line device LIN created. Following this, the current I2 flows into the impedance Rt, and a voltage that is smaller than the medium voltage Vc occurs at the common intersection J. By expressing this span  voltage as Vc + E2, the voltage E2 is expressed as (Vss-Vc) Rt / (Rt + Rout).

Fig. 15 shows the output signals of the supplementary circuit ADC and the receiving circuit RC. The resistance Rt of the equivalent resistance circuit RM is small, with Rt << Rout. Accordingly, the voltages E1 and E2 appearing at the common intersection J are narrow, as shown in Fig. 15 (A). Since the receiving circuit RC works by considering the medium voltage Vc as the threshold value of the inverse function, the receiving circuit RC additionally safely inverts at the voltages Ea and Eb, which are within the voltages E1 and E2. Accordingly, the receiving circuit RC inverts the voltage once at the common intersection J where it crosses the medium voltage Vc. Even if the sum of the wiring capacitance CL and the input capacitance CG is large and the change in the voltage of the signal line LIN is delayed, the output signal of the receiving circuit RC can be transmitted with little distortion as shown in Fig. 15 (C) .

The voltages E1 and E2 are the functions of the Wi Rt and Rout, as explained above de. The smaller the resistance Rt, the smaller are the voltages E1 and E2. However, is required Lich that the resistance Rt within the Signalemp sensitivity of the receiving circuit RC is defined, since the receiving circuit RC the threshold voltage Has. It is assumed that the maximum input voltage VthL of the receiving circuit RC enables a stable low signal or high signal when a low signal is input, and the minimum input voltage VthH enables the Emp capture circuit RC a stable high signal or low  Output rig signal when a high signal is received will.

The input voltage VthL can be defined as the voltage level at which the output signal of the Receive circuit RC begins to change significantly unless the input signal is from the low state is gradually increased. The input voltage VthH can be defined as the voltage level at which the output signal of the receiving circuit RC begins, to change significantly when the input signal gradually decreases from the high state. If e.g. B. the input voltage VthH is equal to Vc + (Vdd-Vc) Is 0.2 and the input voltage VthL is Vc + (Vss-Vc) .0.2 is the ratio of the cons Rt and Rout would preferably be equal or greater as a 1/4 corresponding to the expression of the tensions E1 and E2. The value is even more advantageous by dividing the resistance Rt by the resistance Rout is obtained between 1/2 and 1/4.

Here, the medium voltage Vc not only denotes the medium voltage between the voltage Vdd and the voltage Vss. As described with reference to FIG. 11, the medium voltage Vc denotes an arbitrary voltage between the voltage Vdd and the voltage Vss in accordance with the ratio and is not limited to the medium voltage.

Fig. 16 shows another delay device D10, and Fig. 17 shows the delay device D10 including the circuit which controls the delay time based on the timing signal. Fig. 16 (A) shows the structure of the delay device D10, while Fig. 16 (B) shows the waves in the delay device D10. In Fig. 16 (A), the delay device D10 includes a plurality of delay elements in series with each other, a switch unit SU which selectively outputs one of the output signals of the delay circuits DL in accordance with the selection signal SLS, a supplementary circuit ADC which supplies the medium voltage Vc to the output outputs the switch unit SU, and an inverter INV, which leads the output signal of the switch unit SU to the outside.

Here, the selection signal SLS is an example of the time setting signal shown in FIGS. 5 and 6. The switch unit SU contains a plurality of switches SW which switch the output signals of the delay elements DL to the inverter INV. Each delay element DL delays the input transmission signal to give the input transmission signal to the following the delay element. The supply of the selection signal SLS to the switch unit SU and the selection of one of the output signals of the delay elements DL delays the transmission signal by a desired delay time. The output of the medium voltage Vc to the output of the switch unit SU reduces the change in the power supply voltage, thereby increasing the accuracy of the delay time. After selection by the switch unit SU, the transmission signal is passed to the outside via the inverter INV.

Fig. 16 (B) shows the current wave when successive pulse signals are input to the delay device D10 at a distance of four (4) nanoseconds, each pulse allowing current to flow in the delay device D10 during the four (4) nanoseconds flows. Since the distance at which the pulse signals are supplied is equivalent to the time period during which the current can flow in the delay device D10, the current flows do not overlap each other. Accordingly, the waveform remains constant. The selection of a desired switch SW enables the delay device D10 to change the delay time where it is created by a desired clock signal. Since a large number of switches SW are connected to the output terminals of the switch unit SU, the charging capacity is large.

Accordingly, the operation of the switch SW and changes of the inverter INV the voltage of the delay direction D10. The supplementary circuit ADC gives the Medium voltage from where that from the switch unit SU output voltage is reduced. The result is that any change in the current that occurs in the Delay device D10 flows when the signal changes, diminishes, and continues Change in voltage also decreased. By doing The ADC supplementary circuit is only an example with the Output of the switch unit SU connected; however could if the supplementary circuit ADC with the off gears of the delay elements DL and the inputs the switch SW would be connected to any change in the Electricity can be further reduced.

Fig. 17 shows another delay device D10. In this figure, the delay device D10 includes a circuit which controls the delay time based on the timing signal. The delay device D10 contains a plurality of delay elements DL which delay the transmission signal IN, a plurality of OR gates OR, each of which gives the transmission signal to the following delay element DL, a plurality of AND gates AND, each of which transmits the transmission signal to the following OR gate OR give, after the selection signal SLS has been supplied to them, an inverter INV which gives the transmission signal to the AND gate AND, and a supplementary circuit ADC which outputs the medium voltage Vc to the transmission signal output by the inverter INV. The select signal SLS is an example of the time setting signal shown in FIGS. 5 and 6.

The delay elements DL are in series across that OR-OR connected to the incoming transfer delay the supply signal by a certain time. The total delay time of the delay device D10 is defined by the number of delays elements DL, through which the transmission signal goes through. Accordingly, an assignment of the Selection signal SLS to the delay elements DL the setting of the delay time. For example the selection signal SLS to the highest AND gate AND created. This AND element gives the transfer signal to the next highest OR gate OR. As Next, the OR gate gives the transfer signal to the next highest delay element DL. The transmission signal goes through all delays tion elements DL to lead to the outside become. Therefore, the delay time of the delays d10 the maximum possible delays tion.

The selection signal SLS is sent to the lowest AND gate AND created. This AND element gives the transfer supply signal to the next lowest OR gate OR. Since the lowest OR gate OR no delay Rungselement DL follows, the transmission signal through no delay element DL to go to to be led outside. The creation of the selection si  gnals SLS to the delay element DL in this Way allows the transmission signal without ever de delay is issued. The choice of ver delay element DL to which the selection signal SLS is created, the delay time can be set len. Because a large number of AND gates AND with connected to the output terminals of the inverter INV , the charging capacity is large when the inverter is in Operation is. Accordingly, when the inverter INV and the AND element AND depending on the transfer supply signal work, the voltage of the delay device D10 changed.

The output of the medium voltage Vc reduces the Voltage of Si output from inverter INV gnals. Therefore, any change in the current flowing in of the delay device D10 flows when the Si gnal is changed, reduced, resulting in a decrease everyone, change in tension leads. This improves hence the accuracy of the delay time. By doing The ADC supplementary circuit is only an example with the Output of inverter INV connected, however, the Connection of the supplementary circuit ADC with the off course of the AND-gate AND and the exit of the OR- Member OR continues to make any changes in the current to reduce.

Fig. 18 shows still another delay device D10. In this figure, the delay device D10 is shown without the circuit which controls the delay time based on the timing signal. A large number of receiving circuits RC is connected to the signal line LIN, whereby a large wiring capacity CL and an input capacitance CG are created in the signal line LIN. Accordingly, a change in the signal causes a large current to flow, which changes the voltage. This leads to a large change in the delay time. The supplementary circuit ADC is connected to the signal line LIN, to which the receiving circuits RC, which are suitable for changing the voltage, are connected. This reduces the change in the voltage of the delay device D10 and thereby reduces the change in the delay time.

FIG. 19 shows an improvement of the delay device D10 according to FIG. 18. The supplementary circuit ADC can be connected to any point on the signal line LIN.

Fig. 20 further shows another Verzögerungsvor direction D10. In this figure, a delay device D10 is shown which includes a circuit which controls the delay time based on the timing signal. The delay device D10 comprises a plurality of delay elements DL in series with one another, a plurality of capacitors C10 and C12 which store the electrical charge of the transmission signal output by the delay elements DL, switches SW10 and SW12 which switch the capacitors C10 and C12 to the delay elements DL , and a supplementary circuit ADC, which outputs the medium voltage Vc to the outputs of the delay elements DL. In Fig. 20, the capacitors C10 and C12 are connected to the voltage Vss; however, they can also be connected to the voltage Vdd.

For example, the switching signal SW-CNT1 is provided for the switch SW10 so that the switch SW10 connects the outputs of the delay elements DL and the capacitor C10. Furthermore, the switching signal SW-CNT2 is provided for the switch SW12 so that the switch SW12 connects the outputs of the delay elements DL and the capacitor C12. The entering transmission signal is delayed by the delay element DL to be passed into the following delay element DL. The capacitors C10 and C12 store the electrical charge of the transmission signal, thereby delaying the transmission signal. The selection between switches SW10 and SW12 can set the delay time. For example, if capacitor C10 is selected and capacitor C12 is not selected, since the electrical charge of the transmission signal is only stored in capacitor C10, the delay time becomes shorter than the delay time at which both capacitors C10 and C12 are selected. Here, the switching signals SW-CNT1 and CNT2 SW examples of the time setting signals shown in Fig. 5 and Fig. 6.

The operation of the delay elements DL changes the voltage of the delay device D10. The storage of the electrical charge of the output signal of the delay elements DL in the capacitors C10 and C12 increases the changes in the voltage of the delay device D10. However, the output of the medium voltage Vc decreases the changes in the voltage of the delay device D10, thereby increasing the accuracy of the delay time. Therefore, the delay device D10 shown in FIG. 20 can precisely delay the signal by the supplementary circuit ADC.

Fig. 21 shows an example of switches SW10 and SW12 and capacitors C10 and C12 of Fig. 20. Capacitor C10 includes a P-type FET Qp that connects switch SW10 and voltage Vdd, as well as a FET Qn of N type that connects switch SW10 and voltage Vss. In the P-type FET Qp, the voltage Vdd is applied to the gate G, the source S is connected to the gate G and the drain D is connected to the switch SW10. In the N-type FET Qn, the voltage Vss is applied to the gate G, the source S is connected to the gate G, and the drain D is connected to the switch SW10.

The capacitor C12 contains three P-type and FET Qp an N-type FET Qn. In each P-type FET Qp the voltage Vdd is applied to the gate G, and the Switch SW12 switches the drains D and sources S on the outputs of the delay element DL. That is, the Switch SW12 connects the drains D and sources S with the output of the delay element DL or cut the connection. In the N-type FET Qn the voltage Vss is applied to the gate G which Source is connected to gate G and drain D is connected to the switch SW12. In the FET Qp of the P type and the FET Qn of the N type of the capacitors C10 and C12 is the gate G through the gate Oxidation film isolated from the channel. The Drain D and source S are opposite the substrate SUB isolates due to the fact that they are reversed are biased with respect to the substrate SUB. The according to the capacitors using the FET circuits can be obtained. In addition can by changing the number and position of the condens C10 and C12 the capacity to store the electrical charge can be changed.

Since the supplementary circuit ADC the medium voltage Vc outputs, the change in voltage caused by the condensate formed by the FET circuits  C10 and C12 is realized, can be reduced.

Fig. 22 shows still another delay device D10. In this figure, the delay device D10 is shown to include a circuit which controls the delay time based on the timing signal. The delay device D10 includes a plurality of delay elements DL, a plurality of capacitors C14, C16, C18 and C20 which store the electric charge of the transmission signal, a switch SW20 which switches one of the capacitors C14 and C16 to the output of the delay element DL, a switch SW22, which switches one of the capacitors C18 and C20 to the output of the delay element DL, and a supplementary circuit ADC, which outputs the medium voltage Vc to the output of the delay element DL. In Fig. 22, capacitors C14, C16, C18 and C20 are connected to voltage Vss. However, they can also be connected to the voltage Vdd.

For example, the switch signal SW-CNT3 is applied to the switch SW20 in such a way that the switch SW20 connects the output of the delay element DL and the capacitor C14. Furthermore, the switching signal SW-CNT4 is applied to the switch SW22 in such a manner that the switch SW22 connects the output of the delay element DL and the capacitor C18. The incoming transmission signal is subjected to a delay in the delay element DL and introduced into the following delay element DL. The capacitors C14 and C18 delay the transmission signal by storing the electrical charge. Accordingly, the switches SW20 and SW22 connect one of the capacitors C14 and C16 in parallel to one another and one of the capacitors C18 and C20 to the outputs of the delay elements DL, where adjustment is made by the delay time of the transmission signal. Furthermore, the switch SW20 cannot select either the capacitor C14 or the capacitor C16, and the switch SW22 cannot select the capacitor C18 or the capacitor C20. Here, the switching signals SW-CNT3 and CNT4 SW examples of the time setting signals in accordance with FIGS. 5 and Fig. 6.

The operation of the delay elements DL changes the voltage of the delay device D10. The capacitors C14, C16, C18 and C20 store the electrical charge of the output signals of the delay elements DL, thereby increasing the voltage change of the delay device D10. However, the output of the medium voltage Vc reduces the change in the voltage of the delay device D10, thereby increasing the accuracy of the delay time. Therefore, the delay device C10 shown in Fig. 22 can accurately delay the signal by the supplementary circuit ADC.

Fig. 23 shows an example of the circuits of the switches SW20 and SW22 and the capacitors C14, C16, C18 and C20. Capacitor C14 includes a P-type FET Qp that connects switch SW20 and voltage Vdd and an N-type FET Qn that connects switch SW20 and voltage Vss. In the P-type FET Qp, the voltage Vdd is applied to the gate G, the source S is connected to the gate G and the drain D is connected to the switch SW20. In the N-type FET Qn, the voltage Vss is applied to the gate G and the switch SW20 switches the drain D and the source S to the output of the delay element DL. The capacitor C16 contains an N-type FET Qn. In the N-type FET Qn, the voltage Vss is applied to the drain D and the source S, and the gate G is connected to the switch SW20.

Capacitor C18 includes two P-type FET Qp connecting switch SW22 and voltage Vdd, and two N-type FET Qn connecting switch SW22 and voltage Vss. In one of the P-type FET Qp, the voltage Vdd is applied to the gate G, the source S is connected to the gate G and the drain D is connected to the switch SW22. In the other P-type FET Qp, the voltage Vdd is applied to the gate G, and the switch SW22 switches the drain D and the source S to the output of the delay element DL. In one of the N-type FET Qn, the voltage Vss is applied to the gate G, the source 5 is connected to the gate G and the drain D is connected to the switch SW22. In the other N-type FET Qn, the voltage Vss is applied to the gate G, and the switch SW22 switches the drain D and the source S to the output of the delay element DL. The capacitor C20 has an N-type FET Qn. In this N-type FET Qn, the voltage Vss is applied to the drain D and the source 5 , and the gate G is connected to the switch SW22.

The gate G of each of the P-type FET Qp and the FET N-type Qn in capacitors C14 and C18 is ge opposite the channel through the gate oxidation film iso liert. The drain D and the source S are opposite isolates the substrate SUB due to the fact that they are inversely biased with respect to the substrate SUB are. Accordingly, the capacitors are in use formation of FET circuits. For the condens Sators C16 and C20, since the gate G with the SW20 and SW22 switches are connected, the electri  cal charge stored when a transmission signal is entered that the gate G of the capacitors C16 and C20 inversely biased. In addition, a Change in the number and location of the FET Qp of the P type and the N-type FET Qn of the capacitors C14, C16, C18 and C20 a change in storage capacity the electric charge. Because the supplementary circuit ADC outputs the medium voltage Vc, the change can the voltage generated by the FET circuits formed capacitors C14, C16, C18 and C20 reali is reduced.

Fig. 24 shows examples of the capacitors C10, C12, C14, C16, C18 and C20 of Figs. 20 and 22. Fig. 24 (A) shows an example of the capacitor of the N-type FET Qn. The voltage Vss is applied to the gate G and the substrate SUB, and the switch SW switches the drain D and the source S to the output of the delay element DL. Fig. 24 (B) shows an example of the capacitor of the P-type FET Qp. The voltage Vdd is applied to the gate G and the substrate SUB, and the switch SW switches the drain D and the source S to the output of the delay element DL. Fig. 24 (C) shows an example of the capacitor of the N-type FET Qn. The voltage Vss is applied to the drain D, the source S and the substrate SUB, and the switch SW is connected to the gate G. Fig. 24 (D) shows an example of the capacitor of the P-type FET Qp. The voltage Vdd is applied to the drain D, the source S and the substrate SUB, and the switch SW is connected to the gate G.

In Fig. 24 (A) and (B), the gates G are the FET Qp P-type and the FET Qn N-type through the gate oxidation film insulated from the channels. The drain D and the source S are isolated from the substrate SUB due to the fact that they are inversely biased with respect to the substrate SUB. Accordingly, the capacitors can be formed using FET circuits. In Figs. 24 (C) and (D), the gates G are connected FET Qp P-type and the FET Qn N-type to the switch SW, in which the electric charge is stored, when the transmission signal, the gate G inversely biased. Since the supplementary circuit ADC outputs the medium voltage Vc; the change in voltage realized by the capacitors formed by the FET circuits can be reduced as shown in Figs. 24 (A) to (D).

Figs. 25 and 26 show the improvement in gänzungsschaltung He ADC. As shown in Fig. 25, the supplementary circuit ADC provides the forward bias directly for the gate G of the P-type FET Qp and the N-type FET Qn. This enables the P-type FET Qp and the N-type FET Qn to be kept on. This keeps the voltage at the common intersection J at approximately the medium voltage Vc with low impedance.

Fig. 26 shows the supplementary circuit ADC, which contains a low impedance buffer circuit LOW and a center point voltage source EJV. In the low impedance buffer circuit LOW, the voltage Vdd is applied to the drain D of the N-type FET Qn, the voltage Vss is applied to the drain D of the P-type FET Qp, the gates G of which are connected , The sources S of these are connected, and the medium voltage Vc is applied from the center voltage source EJV to the common intersection J of the gate G.

Fig. 27 shows an equivalent circuit of the supplementary circuit ADC of Fig. 26. It is possible to consider this as a voltage buffer in which the gain = 1, and the N-type FET Qn as well as the P- FET Qp form type, the buffer circuit Niedrigimpedanz- LOW to Fig. 26. The supplementary circuit ADC includes a low impedance buffer circuit LOW as the center voltage source EJV. After the driver circuit DR outputs a low signal, the current I1 flows from the equivalent resistance circuit RM to the signal line LIN. The voltage of the common intersection point J is slightly reduced compared to the medium voltage Vc. At this time, the reception circuit RC outputs a high signal. Alternatively, after the driver circuit DR has output the high signal, the current 12 flows from the signal line LIN to the supplementary circuit ADC. The flow of the current 12 slightly increases the voltage at the common intersection J with respect to the medium voltage Vc. The reception circuit RC outputs a low signal as a result. The resistance RU of the equivalent resistance circuit RM is small with respect to the output impedance Rout of the driver circuit DR, where Rout << Ru. This helps in reducing the change in voltage at the common intersection J, whereby the change in voltage decreases.

Fig. 28 shows another supplementary circuit ADC which uses the midpoint voltage source EJV. In a supplementary circuit ADC with the center voltage source EJV and several low-impedance buffer circuits LOW, it is possible to give the medium voltage Vc to the low-impedance buffer circuits LOW. It is also possible to connect the ADC supplementary circuit to several signal lines LIN. Then the supplementary circuit ADC can supply the medium voltage Vc to the multiple signal lines LIN.

Electricity consumption is almost zero when the Delay device D10 the CMOS circuit in egg has a static state. Accordingly, the Delay device D10 to check this stati current measured. It is checked whether the measured ne current is below a certain value or Not. If the supplementary circuit ADC in the delay device D10 is included, consumes the Supplementary circuit ADC electricity, regardless of whether it is in a static state or Not. Hence the delay device D10, in which the supplementary circuit ADC is contained, not suitable for static current measurement.

Is to solve the problems described above, added to the cutting circuit CUT to the addition circuit ADC in FIG. 29 to 32. The current flowing in the supplementary circuit ADC is cut off for the static current measurement as required by supplying a control signal to the cutting circuit CUT.

Fig. 29 shows the supplementary circuit ADC, which is provided with the cutting circuit CUT. The cutting circuit CUT contains a control connection CT. After a high signal has been fed to the control connection CT, the supplementary circuit ADC is switched on. When the control terminal CT is supplied with a low signal, the supplementary circuit ADC is switched off, as a result of which no electrical power is used. That is, supplying a high signal to the control terminal CT turns on FET Q1 and Q3 and turns off FET Q2 and Q4. Since the FET Q2 is switched on and the FET Q1 is switched off, this corresponds to the case that the FET Q5 is switched on and the FET Q6 are switched off. The supplementary circuit ADC operates with the gates G of the FET Qp and the FET Qn, which are connected to one another via the FETs Q4 and Q5. The application of a low signal to the control terminal CT causes the FET Q1 and Q3 to be turned on while the FET Q2 and Q4 are turned off. Since FET Q1 and FET Q2 are turned off, FET Q5 is turned off and FET Q6 is turned on. That is, since the FET Q4 and Q5 are turned off and the FET Q3 and Q6 are turned on, the FET Qp and Qn are turned off. Here, even when the FET Q1, Q3 and Q6 are turned on, the FET Q2, Q4 and Q5 are turned off so that no current flows into the supplementary circuit ADC. Accordingly, supplying a low rig signal to the control terminal CT enables the static current measurement.

Fig. 30 shows the cutting CUT circuit which includes a switching element ANS. This is commonly referred to as an analog switch. Switching off the switch element ANS switches the FET Qp and Qn off. The static current can therefore be measured by switching off the switch elements ANS.

FIG. 31 shows the supplementary circuit ADC according to FIG. 25, which is provided with the cutting circuit CUT. Turning on the FET Q4 and Q5 by supplying a high signal to the control terminal CT applies the forward bias voltages Vss and Vdd to the gates G of the P-type FET Qp and the N-type FET Qn. This turns on both the P-type FET and the N-type FET Qn to enable them to function as the supplementary circuit ADC. The supply of a low signal to the control terminal CT turns the FET Q4 and Q5 off and the FET Q3 and Q6 on. The result is that the P-type FET Qp and the N-type FET Qn are turned off and do not consume electrical power.

Fig. 32 shows the supplementary circuit ADC, which is provided with the cutting circuit CUT, which contains the low impedance buffer circuit LOW and the center point voltage source EJV. The supplementary circuit ADC of FIG. 10 is used as the midpoint voltage source EJV. The cutting circuit CUT1 turns off the P-type FET Qp1 and the N-type FET Qn1, both of which form the center voltage source EJV. The cutting circuit CUT2 turns off the P-type FET Qp2 and the N-type FET Qn2, both of which form the low impedance buffer circuit LOW. By supplying a high signal to the control terminal CT, the FET Q4-1 and Q5-1 in the cutting circuit CUT1 are turned on. This connects the gates G of the P-type FET Qp1 of the N-type FET Qn1 to each other via the FET Q4-1 and Q5-1. As a result, the medium voltage Vc is output to the intersection J1.

The FET Q4-2 and Q5-2 are switched on in the cutting circuit CUT2. As a result, the gates G of the N-type FET Qn2 and the P-type FET Qp2 are connected via the FET Q4-2 and the FET Q5-2. The medium voltage Vc is given from the center voltage source EJV to the common intersection J2. In this case, the N-type FET Qn2 and the P-type FET Qp2 are similar to those of the low impedance buffer circuit LOW shown in Fig. 26; After the driver circuit DR supplies a signal to the intersection J2, they operate in accordance with the operation explained with reference to FIG. 26. To supply a low signal to the control terminal CT turns the FET Q3-1 and Q6-1 on and the FET Q4-1 and Q5-1 off. This corresponds to that the N-type FET Qn2 and the P-type FET Qp2 are turned off. Accordingly, the supply of the low signal to the control terminal CT leads to a complete shutdown of the current, which enables the static current measurement.

In the above embodiments, the inv ter INV used for the supplementary circuit ADC. in the ADC supplementary circuits are explained below, the circuits other than the INV inverter ten, e.g. B. a NAND gate or a NOR gate.

Fig. 33 shows another delay device D10 according to the present invention. The supplementary circuit ADC contains a NAND element. In particular, the NAND element is connected to the feedback circuit NF. Since the NAND gate has at least two input connections, one of these may be available for the control connection CT.

Fig. 34 shows the configuration of the addition circuit ADC using the NAND gate. The supply of a high signal and a low signal to the control terminal CT switches the supplementary circuit ADC on / off. The supply of a high signal to the control terminal CT turns on the supplementary circuit ADC to output the medium voltage Vc; To carry out a low signal therefore turns off the supplementary circuit ADC to give a high signal. The application of a high signal to the control connection CT switches the FET Q1 on and FET Q4 off. Accordingly, the supplementary circuit ADC operates with the drains D of the FET Q2 and Q3 connected to each other to output the medium voltage Vc.

Alternatively, the supply of a low Signals to the control terminal CT the FET Q1 and the FET Q4. This causes the voltage to rise the common intersection J becomes high. The exam of leakage currents in integrated semiconductors circuits, d. H. static current testing required changes that the output signal of the driver circuit DR to the equivalent tension of the common cut point J is set. The control of the entrance signals for the control connection CT can with the ADC supplementary circuit provided with NAND element /turn off.

Fig. 35 shows a further delay device D10 according to this invention. The supplementary circuit ADC contains a NOR gate. In particular, the supplementary circuit ADC has a NOR gate connected to the feedback circuit NF. Since the NOR gate contains at least two input ports, one of these may be available as the control port CT.

Fig. 36 shows an example of the supplementary circuit ADC provided with the NOR gate. The supply of a high signal and a low signal to the control terminal CT switches the supplementary circuit ADC on / off. The supply of a low signal to the control terminal CT turns on the supplementary circuit ADC to keep the output of the medium voltage Vc. Alternatively, the supply of a high signal to the control connection CT switches off the supplementary circuit ADC, which leads to the output of a low signal. Applying a low signal to the control terminal CT turns the FET Q1 off and the FET Q2 on. Since the drain D of the FET Q3 is connected to the source S of the FET Q2 and the FET Q2 is turned on, the drains D of the FET Q3 and Q4 are connected to each other to operate as the supplementary circuit ADC, thereby outputting the medium voltage Vc becomes.

In contrast, the application of a high signal switches to the control terminal TC the FET Q1 and the FET Q2 off. Since the FET Q1 is on, the Voltage at the common intersection J low. The test leakage currents in integrated half conductor circuits, d. H. the static current test requires that the output signal of the driver scarf tion DR to the equivalent voltage at the common Intersection J is set. The control of the on can signal with the control connection CT the supplementary circuit ADC provided to the NOR gate /turn off.

Fig. 37 shows yet another addition circuit ADC. The supplementary circuit ADC includes a control terminal CT and XCT as the cutting circuit CUT. The supply of a high signal to the control connection CT and a low signal to the control connection XCT turns on the supplementary circuit ADC. Alternatively, the supply of a low signal to the control connection CT and a high signal to the control connection XCT turns off the supplementary circuit ADC, so that no electrical power is consumed. That is, supplying a high signal to the control terminal CT and a low signal to the control terminal XCT turns on the FET Q1 and Q4. This results in the application of the voltage Vdd from the FET Q1 to the FET Q2 and the voltage Vss from the FET Q4 to the FET Q3. Accordingly, the medium voltage Vc is applied to the common intersection J of the gates G of the FET Q2 and Q3. The supply of a low signal to the control terminal CT and a high signal to the control terminal XCT turns off the FET Q1 and Q4. Since neither the voltage Vdd nor the voltage Vss are applied to the FET Q1 and Q4, no current flows into the supplementary circuit ADC. Therefore, supplying the low signal to the control terminal CT and the high signal to the control terminal XCT enables measurement of the static current of the delay device D10.

Here, the medium voltage Vc is not limited to the medium voltage between the Vdd and the voltage Vss. The medium voltage Vc denotes an arbitrary voltage between the voltage Vdd and the voltage Vss in accordance with the ratio. For example, in addition to the mean voltage between the voltage Vdd and the voltage Vss, the medium voltage source shown in FIG. 26 outputs a voltage corresponding to the threshold voltage of the receiving circuit RC.

Fig. 38 shows the semiconductor apparatus 96 comprising the Halbleiterprüfeinheit 97 which Halbleitervor directions examined. The semiconductor device 96 includes the semiconductor test unit 97 and the device unit 98 .

The semiconductor test unit 97 includes a pattern generator 90 , a shaped pattern generator 92, and a comparator 95 . The shaped pattern generator 92 has a delay circuit 100 . The delay circuit is constructed as shown in FIG. 26.

The pattern generator 90 generates test pattern data to be input into the device unit 98, and an expected pattern expected from the that it outputs 98 sterdaten in response to the Mu, the device unit. The pattern generator 90 outputs the pattern data to the generator <07117 00070 552 001000280000000200012000285910700600040 0002010013553 00004 06998BOL <92 for shaped patterns and the expectation data to the comparator 95 . Furthermore, the pattern generator 90 outputs a timing signal to the delay circuit 100 . The timing signal instructs the delay circuit to generate a delay clock that has a certain delay value corresponding to the operational characteristics of the device unit 98 . The delay circuit 100 generates a delay clock having the delay value determined by the timing signal. The generator 92 for shaped pattern formed the pattern data on the basis of the delay provided by the delay circuit 100 clock. This creates shaped pattern data for the device unit 98 according to its operation characteristics. In response to the shaped pattern data, the device unit 98 provides output data to the comparator 95 . The comparator 95 compares the expected data and the output data to judge whether the device unit 98 is good or not. The use of the delay device D10 according to FIGS . 7 to 37 for the delay circuit 100 increases the accuracy of the delay time of the delay circuit 100 , which in turn increases the accuracy of the testing of the semiconductor test unit 97 .

Fig. 39 is a block diagram showing the Oszil loskop. The oscilloscope includes the analog front end 102 , the A / D converter 104 , the memory 106 , the processor 108 , the display unit 110 , the time interpolator 112 and the delay circuit 100 . The delay circuit 100 is formed as shown in FIG. 6. The delay circuit 100 to the A / D converter 104 and the time interpolator 112 to the delay clock, which has a given delay value with respect to the reference clock. In response to the analog signal, the analog front end 102 outputs a trigger signal to the time interpolator 112 . The analog front end 102 also outputs the analog signal to the A / D converter 104 . The A / D converter 104 converts the incoming analog signal into a digital signal based on the delay clock provided by the delay circuit 100 . The digital signal is then output to memory 106 . The memory 106 stores the digital signal provided by the A / D converter 104 .

The time interpolator 112 measures the clock difference between the trigger signal provided by the analog front end 102 and the delay clock supplied by the delay circuit 100 . The time interpolator 112 then outputs the clock difference to the processor 108 .

The processor 108 performs a process that is not manoeuvrable for the analog representation of the data based on the stored data in the memory 106 and the geliefer from the time interpolator 112 th clock difference. The processor 108 then outputs the display data to the display unit 110 . The display unit 110 displays the analog signal in accordance with the display data supplied by the processor 108. The use of the delay device D10 in FIGS. 7 to 37 for the delay circuit 100 improves the accuracy of the delay time, thereby increasing the accuracy of the display of the oscilloscope.

While the present invention is based on the before preferred embodiments has been described the invention is not limited to this. The invention can be embodied in different ways without that of the principle of the invention, as in the appended claims becomes.

As described above, reduced according to the before preferred embodiments, the connection of the Er supplementary circuit ADC with the delay element DL the change in the power supply voltage for the Delay device D10. The result is one Increase the accuracy of the delay time Delay device D10. Continues to change when the power supply voltage changes, the Mit issued by the supplementary circuit ADC telc voltage Vc too. This changes proportions tional to the change in voltage to smolder lenwert of the delay element DL to follow where is made possible by the regular operation. The he supplementary circuit ADC contains a ratio equiva lent to the ratio of the delay element DL and a feedback circuit NF. The supplementary scarf ADC can adjust the voltage according to the logic Generate threshold value of the delay element DL. Furthermore, the change in power delivery voltage reduced so that of the delays emitting device DC radiated electromagnetic Wave noise is also reduced.  

According to the preferred embodiments, light provides the cutting end connection CUT in the circuit, e.g. B. the supplementary circuit ADC and he midpoint voltage source EJV, the cutting off of the current flowing in this circuit. Accordingly, it is possible to prevent the idle current from flowing in such a circuit that allows the idle current to flow in the static state. As a result, it becomes easier to perform the static current measurement when testing a delay device D10 that includes the supplementary circuit ADC or the center voltage source EJV. Furthermore, the application of the delay device D10 according to the present invention to the delay circuit 100 increases the accuracy of the test of the semiconductor test apparatus including the delay circuit 100 . The delay device D10 of the present invention also increases the accuracy of testing the Ge semiconductor device which has the surface applied with the delay circuit 100 leiterprüfeinheit half 97, and the accuracy of the display of the oscilloscope with the delay circuit 100th

As described above, according to the present Invention reducing the change in lei Power supply voltage of the delay device the accuracy of the delay time of the delays increase the device. This is therefore in the La ge, which from the delay device D10 radiated electromagnetic wave noise to redu adorn.

Claims (40)

1. Delay device, which delays an incoming transmission signal, with a delay element (DL), which is operated with a power supply voltage Vdd and a power supply voltage Vss and delays the transmission signal, the voltage Vdd being greater than the voltage Vss, characterized that the delay device further comprises a supplementary circuit (ADC) which outputs a predetermined voltage (Vc) to an output of the delay element which is greater than the voltage Vss and less than the voltage Vdd. 2. Delay device according to claim 1, characterized characterized in that the delay device still several delay elements (DL) in Row with each other and several supplementary scarves tion (ADC), each with one of the outputs of the multiple delay elements connected are. 3. Delay device according to claim 1, characterized characterized in that the delay element (DL) contains a digital circuit which is one of the Output voltages of two possible values outputs according to an input voltage, and that the supplementary circuit (ADC) has a voltage (Vc) outputs that is substantially equal to one Threshold voltage is the output signal the digital circuit from one of the output  tensions from two possible values to the whose inverted of these. 4. Delay device according to claim 1, characterized characterized that the supplementary circuit (ADC) an approximate medium voltage (Vc) between between voltage Vss and voltage Vdd gives. 5. Delay device according to claim 1, characterized characterized that the supplementary circuit (ADC) contains a low impedance that is small ner than an output impedance of the delay elements (DL). 6. Delay device according to claim 5, characterized characterized in that the output impedance of the Er supplementary circuit (ADC) in the range of half te the output impedance of the delay element (DL) is up to a quarter of this. 7. Delay device according to claim 1, characterized characterized that the supplementary circuit (ADC) contains a first logic gate that outputs an input signal inversely, and one Feedback circuit (NF), which has an input circuit of the first logic gate and one Output connector from this connects. 8. Delay device according to claim 7, characterized characterized in that the delay element (DL) contains a second logic gate, and that the first logical gate a ratio ent that is essentially a ratio nis of the second logic gate. 9. Delay device according to claim 7, characterized characterized in that the first logical gate  an inverter (INV), a NAND gate (NAND) or contains a NOR gate (NOR). 10. Delay device according to claim 7, characterized characterized in that the delay element (DL) contains a second inverter and the inverter contains a relationship that essentially equal to a ratio of the second inverter is. 11. Delay device according to claim 2, characterized characterized in that the delay device further includes a switch unit (SU) that one of the output signals of the multiple delays rungselemente (DL) outputs, where the Ergän tion circuit (ADC) the predetermined voltage (Vc) to the output of the switch unit. 12. Delay device according to claim 1, characterized characterized in that the delay device continue several delay element (DL) in Row with each other and a selection element (AND, OR) contains that from the multiple delay elements elements (DL) selects a delay element, in which the transmission signal is entered, whereby the supplementary circuit (ADC) a vorbe voted voltage (Vc) that is greater than the span voltage Vss and less than the voltage Vdd, depending on the entered transfer output signal. 13. Delay device according to claim 1, characterized characterized in that the delay device several capacitors (C10, C12, C14, C16, C18, C20), the electrical charge of the over the delay element (DL) store signal, and multiple switches  (SW10, SW12, SW20, SW22) which the multiple Capacitors to the output of the delay switch elements. 14. Delay device according to claim 13, characterized in that the capacitor (C10, C14, C18) contains a P-type (Qp) FET, where the voltage Vdd is applied to a gate (G) of the P-type FET at least one drain (D) or source ( 5 ) of the P-type FET is connected to the gate and the other of these is connected to the switch (SW10, SW20, SW22). 15. Delay device according to claim 13, there characterized in that the capacitor (C10, C12, C18) contains an N-type (Qn) FET where at the voltage Vss to a gate (G) of the FET from N-type is applied, at least one drain (D) or a source (S) of the N-type FET with the Gate (G) is connected and the other of these connected to the switch (SW10, SW12, SW22) is. 16. Delay device according to claim 13, there characterized in that the capacitor (C12, C18) contains a P-type (Qp) FET, the Voltage Vdd to a gate (G) of the P-type FET is created and the switch (SW12, SW22) is one Drain (D) and a source (S) of the P-type FET to the output of the delay element (DL) switches. 17. Delay device according to claim 13, there characterized in that the capacitor (C14, C18) contains an N-type (Qn) FET, the Voltage Vss to a gate (G) of the N-type FET is created and the switch (SW20, SW22) is one  Drain (D) and a source (S) of the FET N type too the output of the delay element (DL) scarf tet. 18. Delay device according to claim 13, there characterized in that the capacitor (C16, C20) contains an N-type (Qn) FET, the Voltage Vss to a drain (D) and a source (S) of the N-type FET is applied and a gate (G) of the N-type FET with the switch (SW20, SW22) is connected. 19. Delay device according to claim 13, there characterized in that the capacitor has a Contains N-type FET (Qn), where the voltage Vss to a gate (G) of the N-type FET and on Substrate (SUB) is created and the switch (SW) a drain (D) and a source (S) of the FET from the N type to the output of the delay element elements (DL) switches. 20. Delay device according to claim 13, there characterized in that the capacitor has a P-type FET (Qp) contains the voltage Vdd to a gate (G) of the P-type FET and on Substrate (SUB) is created and a switch (SW) a drain (D) and a source (S) of the FET from the P type to the output of the delay element elements (DL) switches. 21. Delay device according to claim 13, there characterized in that the capacitor has a Contains N-type FET (Qn), where the voltage Vss to a drain (D), a source (S) and a N-type FET substrate (SUB) is applied and a gate (G) of the N-type FET with the Switch (SW) is connected.   22. Delay device according to claim 13, there characterized in that the capacitor has a P-type FET (Qp) contains the voltage Vdd to a drain (D), a source (S) and a P-type FET substrate (SUB) is applied and a gate (G) of the P-type FET with the Switch (SW) is connected. 23. Delay device according to claim 1, characterized characterized that the supplementary circuit (ADC) a P-type (Qp) FET and a Contains N type (Qn) and a forward bias to a gate (G) of the P-type FET and to a Ga te (G) of the N-type FET. 24. Delay device according to claim 1, characterized characterized that the supplementary circuit (ADC) contains a voltage source (EJV) which outputs the predetermined voltage (Vc). 25. Delay device according to claim 24, there characterized in that the supplementary scarf device (ADC) continues to have a low impedance Buffer circuit (LOW) contains, which an Impe danz of the voltage source (EJV) voltage. 26. Delay device according to one of the claims 23 to 25, characterized in that the Ver delay device continues a cutting circuit (CUT), which the current, the between the delay element (DL) and the Supplementary circuit (ADC) flows, cuts off. 27. Delay device according to claim 1, characterized characterized that the supplementary circuit (ADC) a NAND gate (NAND) and a feedback circuit (NF) contains an input  connection of the NAND link with an output connection conclusion of this connects. 28. Delay device according to claim 27, there characterized in that the NAND element (NAND) contains a control connection (CT) to which a control ersignal is supplied, which a current intersects that between the delay element (DL) and the supplementary circuit (ADC) flows, as well as one flow in the supplementary circuit the stream. 29. Delay device according to claim 1, characterized characterized that the supplementary circuit (ADC) a NOR gate (NOR) and a feedback circuit (NF) contains an input connection of the NOR gate with an output connection conclusion of this connects. 30. Delay device according to claim 29, there characterized in that the NOR gate (NOR) has a control connection (CT), which a Control signal is supplied which is a current the between the delay element (DL) and the supplementary circuit (ADC) flows, and egg current flowing in the supplementary circuit cuts off. 31. Delay device according to claim 1, characterized characterized that the supplementary circuit (ADC) with one end of the delay element (DL) is connected. 32. Semiconductor test device which tests a semiconductor device and which comprises: a pattern generator ( 90 ) which generates a test pattern to be guided into the semiconductor device ( 93 ), a delay unit ( 100 ) which has a delay clock with a delay value corresponding to one Operational characteristic of the semiconductor device generates, a shaped test pattern generator ( 92 ) that generates a shaped test pattern by shaping the test pattern based on the delay clock, a device insertion unit ( 94 ) for fixing the semiconductor device thereon and for inputting the shaped test pattern in the semiconductor device is used, and a comparator ( 95 ) that judges whether the semiconductor device is good or not based on the output signal output from the semiconductor device in response to the shaped test pattern, the delay unit ( 100 ) delaying gselement (DL), which is operated by two power supply voltages Vss and Vdd and which delays an input clock by the delay value to produce the delay clock, and wherein the voltage Vss is less than the voltage Vdd, characterized in that the delay unit knows further contains an additional circuit (ADC), which outputs a predetermined voltage (Vc), which is greater than the voltage Vss and less than the voltage Vdd, depending on the output signal of the delay element. 33. Semiconductor test device according to claim 32, characterized in that the delay unit ( 100 ) further includes a plurality of delay elements (DL) in series with one another and a plurality of supplementary circuits (ADC), each of which is connected to one of the outputs of the plurality of delay elements. 34. The semiconductor test device according to claim 32, since characterized in that the delay element ment (DL) contains a digital circuit that one of two possible output voltages Values depending on an input span outputs output, the supplementary circuit (ADC) outputs a voltage (Vc) that is essentially is equal to a threshold voltage that the output signal of the digital circuit from one of the output voltages from the two possible values to the other of these inver animals. 35. Semiconductor device which contains a semiconductor test unit ( 97 ) which tests the semiconductor device, with a semiconductor device unit ( 98 ) and a semiconductor test unit ( 97 ) which contains a delay unit ( 100 ) which generates the generation times of a test pattern, which is used to test the semiconductor device unit, the delay unit ( 100 ) includes a delay element (DL) which is operated with two voltages Vdd and Vss and which generates the times by delaying the input clock, and wherein the voltage Vdd is greater than that Voltage Vss, characterized in that the delay unit further includes a supplementary circuit (ADC) which outputs a predetermined voltage (Vc), which is greater than the voltage Vss and less than the voltage Vdd, depending on the output signal of the delay element. 36. Semiconductor device according to claim 35, characterized in that the delay unit ( 100 ) further contains a plurality of delay elements (DL) in series with one another and a plurality of supplementary circuits (ADC), each of which is connected to one of the outputs of the plurality of delay elements. 37. The semiconductor device according to claim 35, characterized characterized in that the delay element (DL) a digital circuit containing one of Output voltages of two possible values in Depending on an input voltage, the supplementary circuit (ADC) being a span voltage (Vc) that is essentially the same a threshold circuit that is the output signal of the digital circuit from one of the Output voltages of two possible values the other of them inverted. 38. Oscilloscope, which makes an input signal visible, with a delay unit ( 100 ), which generates a delay clock based on an input clock, an A / D converter ( 104 ), which performs an analog / digital conversion on the input signal based on the time behavior of the delay clock, a time interpolator ( 112 ) which, as a delay time, behaves a time difference between the time at which the input signal is input and a time behavior at which the delay clock is output, a pro processor ( 108 ) which generates data used to display the input signal based on data generated by the A / D converter and the delay time, and a display unit ( 110 ) which generates the input signal based on the data from indicates data generated to the processor, wherein the delay unit ( 100 ) includes a delay element (DL) that is powered by two power supplies Vss and Vdd be operated and that delays the input clock to generate the delay clock, the voltage Vdd is greater than the voltage Vss, characterized in that the delay unit further includes a supplementary circuit (ADC) which a predetermined voltage ( Vc), which is greater than the voltage Vss and less than the voltage Vdd, depending on the output signal of the delay element. 39. Oscilloscope according to claim 38, characterized in that the delay unit ( 100 ) furthermore contains several delay elements (DL) in series with one another and several supplementary circuits (ADC), each of which is connected to one of the outputs of the plurality of delay elements. 40. Oscilloscope according to claim 39, characterized records that the delay element (DL) a digital circuit which includes an out of output voltages of two possible values in Ab depending on an input voltage, the supplementary circuit (ADC) being a span voltage (Vc) that is essentially the same a threshold voltage that is the output signal of the digital circuit from one of the Output voltage of two possible values too another one of these inverted.