DE10011885C2 - Process for the production of a field effect transistor with sidewall oxidation - Google Patents

Description

The present invention relates to a method for Manufacture of a field effect transistor with sidewall oxides tion and in particular on a method for producing a Field effect transistor with improved charge retention time, such as it can be used in DRAM and FLASH memories.

From the document US 5,972,783 a method for im plant nitrogen ions into the surface of a sub strats and the side walls of a gate stack known where an extremely reliable MOS transistor len. In particular so-called "hot electron injection" - This can reduce defects in a gate oxide layer become, which increases a dielectric strength and the occurrence of leakage currents can be reduced.

A similar procedure is from the S. Kusu reference noki et al "Hot Carrier Resistant Structure by Re-Oxidized Nitrided Oxide Sidewall for Highly Reliable and High Perfor mance LDD-MOSFETs ", IEDM '91, pages 649-652, known where when again a nitrogen implantation to avoid egg deterioration of the characteristic properties nes MOSFETs due to hot charge carriers.

Another comparable process is from printing known US 5,923,983, but no scatter oxide the implantation of the LDD areas is used, but a area of the Si implanted with N ions So-called "channeling" should prevent substrate.  

Furthermore, from the literature reference B. Doyle et al .: "Simultaneous Growth of Different Thickness Gate Oxides in Silicon CMOS Processing", IEEE Electron Dev. Lett., Vol. 16, No. 7, July 1995 , pages 301-302 the effects of nitrogen on the growth of thermal silicon oxide are known, with different thickness gate oxide layers being formed on a substrate by means of a single temperature step.

Especially in integrated circuits for the realization of Memory modules, such as B. DRAM, FLASH, EPROM, etc. Spei Chern to the field effect transistors used therein extraordinarily high requirements with regard to cargo hold tion properties or retention time provides. A possible cause of insufficient charge hold Properties is, for example, that after a Ga te stack structuring of a field effect transistor led a gate insulation layer near the processes Gate stack can damage, causing leakage currents in the Field effect transistor result. Usually Besei such leakage properties, the layer thicknesses of the Insulation layers on the side walls of the gate stack he increases, but at the same time the thickness of a Insulation layer on a semiconductor substrate increased. The Insulation layer on the semiconductor substrate, however, works for a subsequent implantation of source and drain areas as a scattering oxide, which ultimately leads to a short channel behavior ten of the field effect transistor due to the increased implant tion energies worsened.

Another reason for the low charge holding properties of field effect transistors can be, for example, the occurrence of high field strengths at the corners or edges of a gate layer. Fig. 1 shows a simplified sectional view of a conventional field effect transistor for demonstrating such an error cause. In Fig. 1, a gate insulation layer 2 and a gate layer 3 are stacked on a semiconductor substrate 1 . Formed in the semiconductor substrate 1 and reaching the gate insulation layer 2 source and drain regions S and D thus result in a field effect transistor as used, for example, in DRAM, flash, etc. memory cells. So-called spacers or auxiliary layers SP are usually used on the side walls of the gate insulation layer 2 and the gate layer 3 for lateral insulation or for forming heavily doped source and drain regions. However, the sharp edge or corner of the gate layer 3 that occurs in the gate insulation layer 2 is particularly disadvantageous in such a conventional field effect transistor. More specifically, when applying normal operating voltages, such as those used in a memory matrix for selecting rows and columns, very high field strengths E are formed between the gate layer 3 and the source and drain regions S and D due to the sharp-edged shape, as a result of which Leakage currents in the field effect transistor result and thus the charge holding times of memory cells are deteriorated. In particular, this causes a so-called GIDL leakage current (gate induced drain leakage).

Layer to prevent such leakage currents in particular from the high field strengths E at the edges of the gate give 3, a so-called side is usually conducted wall oxidation, whereby substantially the sharp edges or corners of the gate layer 3 rounded who to, and consequently the Field strengths E are standardized or reduced.

Fig. 2 shows a simplified sectional view of a gene tion genei conventional field effect transistor with side wall oxida tion. In FIG. 2, the reference number 1 again designates a semiconductor substrate, the reference number 2 a gate insulation layer and the reference number 3 a gate layer. In the semiconductor substrate 1 , source and drain regions S and D are in turn formed. According to FIG. 2, a gate stack with its sharp edges is now oxidized by a thermal oxidation process in such a way that so-called bird beaks or birds peaks BP are formed on the edges of the gate stack. More specifically, thermal oxidation becomes one. Surface of the semiconductor substrate 1 and a side wall of the gate stack or the gate layer 3 are oxidized in such a way that a uniformly thick electrical insulation layer 5 is formed, which in particular rounds off the sharp edges or corners of the gate layer 3 in its lower region. In this way, the increased field strengths E at the edges or corners of the gate layer 3 can be reduced, which results in a reduction in leakage currents in the field effect transistor. However, the disadvantage of such a sidewall oxidation is that there is a relatively thick insulation layer 5 on the semiconductor substrate 1 , which acts as a scatter insulation layer in a subsequent implantation process.

Especially in the case of highly integrated circuits or in the field effect transistors with a very small structure width of ≦ 1 µm however, this results in such a fuzzy implantation gene offer, which in turn a gripping effect or punch Cause through effect. To avoid such Punch-through effects must therefore either so-called anti Pass-through areas or anti-punch-through areas in the channel offers the field effect transistor to be formed.  

Alternatively, one subsequently removes the thick surface insulation layer 5 formed during the side wall oxidation, then implants the source and drain regions and then carries out thermal oxidation of the semiconductor substrate surface, as a result of which the thin and defined insulation layers required for the process are obtained. A disadvantage of this multi-stage process, however, is again an increased temperature budget, in which the doping regions in particular run and thus in turn cause the previously described deteriorated short-channel properties. Furthermore, such a conventional manufacturing process is extremely complex.

The invention is therefore based on the object of a method for producing a field effect transistor with a side wall to create oxidation in a simple and inexpensive way way field effect transistors with excellent charge holding properties can be formed.

According to the invention, this object is achieved through the measures of Claim 1 solved.

Especially by implanting insulation layers Growth inhibitors in the surface of the semiconductor substrate with the exception of at least one side wall of the gate stack and subsequent thermal forming of a surface chen insulation layer, you get a self-adjusting Process in which particularly simple and inexpensive Strong sidewall oxidation as well as weak Oxidation of the semiconductor substrate surface takes place.

N, N ₂ or a nitride is preferably incorporated as an insulation layer growth inhibitor into the surface of the semiconductor substrate or of the gate stack. Since such implant materials are already implemented in standard processes, the manufacturing process can be implemented without additional effort.

The implantation of the insulation layer growth inhibitor preferably perpendicular to the surface of the semiconductor substrate performed, resulting in an evenly thick insulation layer on the side walls of the gate stack. On the In this way, both the source and the drain side are so-called te bird beaks or birds peaks are formed, whereby significantly reduce or ver the electrical field strengths let uniform.

The implantation of the insulation layer growth inhibitor can but also at an angle to the surface of the semiconductor substrate follow, leaving only one side wall of the gate stack is exposed to strong sidewall oxidation and the white tere side wall experiences a relatively low oxidation. On this way can be selectively one only on source or Leakage current occurring on the drain side can be specifically reduced.

Furthermore, a weakly doped source and drain implant tion before or after implantation of the insulation layer Growth inhibitors are carried out, which results in an opti male adaptation to a particular process. In the same A gate insulation layer can only be partially removed and as a residual insulation layer on the semiconductor sub strat surface remain, which in turn creates an opti Male adaptation to existing manufacturing processes results and in particular the realization of a so-called embedded or embedded processes is enabled.  

In the further subclaims there are further advantageous ones Characterized embodiments of the invention.

The invention is described below with reference to exemplary embodiments len described with reference to the drawing.

Show it:

Figure 1 is a simplified sectional view of a field effect transistor according to the prior art.

Figure 2 is a simplified sectional view of a field effect transistor with Sidewalloxi dation according to the prior art.

Figs. 3A to 3G simplified sectional views for Veran schaulichung of the individual process steps for producing the fiction, modern field effect transistor side wall oxidation according to a first exporting approximately, for example; and

FIGS. 4A and 4B simplified sectional views for Veran schaulichung of essential process steps for fabricating the fiction, modern field effect transistor side wall oxidation according to a second exporting approximately, for example.

FIGS. 3A to 3G show simplified sectional views illustrating respective manufacturing steps of the field effect transistor according to the invention with side wall oxidation according to a first embodiment, wherein like reference characters designate like or similar elements or layers as shown in Figs. 1 and 2 represent and dispensed with below a detail profiled Description becomes.

Referring to FIG. 3A, a semiconductor substrate is first readied rides 1, preferably SiGe, SiC or SOI may be are made of silicon.

Referring to FIG 3B is formed in a subsequent process step, a gate insulation layer 2 over the entire area on the semiconductor substrate α., Preferably distinguishes method, a thermal oxidation of the semiconductor substrate 1 or a chemical Ab (CVD) is used. The gate insulation layer 2 preferably consists of an SiO ₂ layer, which can also be used as a tunnel oxide layer, in particular when realizing FLASH memories.

According to FIG. 3C, an electrically conductive gate layer 3 is formed over the entire area on the gate insulation layer 2 in a subsequent method step and is covered with a mask layer 4 . The mask layer 4 preferably consists of a hard mask such as. B. SiO ₂ , but can also be realized as a paint mask or other masking layer. After patterning of the mask layer 4 of the remaining mask layer 4, both the gate is now using such layer tured constructive that a gate stack GS gives 3 and the gate insulating layer. 2 The structuring of the gate layer 3 and the gate insulation layer 2 is preferably realized by an anisotropic etching process, it also being possible to use all other conventional processes for structuring gate stacks. For example, highly doped polysilicon is used for the electrically conductive gate layer 3 . So-called "dual work function gates" are preferably used, with undoped polysilicon first being formed as gate layer 3 , which is doped together with a source / drain implantation at a later point in time. Further, 3C, wherein struc can turing of Fig. For forming the gate stack GS, the gate insulation layer 2 completely, or only partially removed with a (not shown) remaining isolation layer further covering the surface of Halbleitersub strats. 1

Referring to FIG. 3D is a vertical implantation I _N isolation layer growth inhibitors will now be given x in the surface of the semiconductor substrate 1 as well as in the surface of the Ga-th stack GS, and the mask layer 4. The insulation layer growth inhibitor x have the task of hindering the growth of a thermally formed electrical insulation layer 5 , whereby a self-adjusting process for different oxide thicknesses on the upper surface of the semiconductor substrate 1 and on the side walls of the gate stack GS can be realized.

During the implantation, I _N for implanting insulation layer growth inhibitors x N, N ₂ or nitrides are preferably introduced into the surface of the semiconductor substrate or the gate stack GS. However, all further insulation layer growth inhibitors can be used which can influence the growth of the insulation layer or oxide layer in the case of subsequent thermal oxidation or in the subsequent formation of an insulation layer. However, since the implantation of nitrogen in particular with its growth-inhibiting effect on oxide layers is already known and is already available in standard processes, this implant material is preferably used, which further simplifies production.

According to FIG. 3E, an implantation I _LDD to form weakly doped source and drain regions S and D is now carried out again in a self-adjusting manner using the gate stack GS, which immediately adjacent to the gate insulation layer 2 in the semiconductor substrate 1 be formed. Referring to FIG. 3E, the implant I _LDD to form lightly doped source and drain regions S and D in the semiconductor substrate 1 after the implantation I _N for implanting the insulation layer-growth inhibitors x is performed. However, it can also be carried out in the same way before the implantation I _N for implanting the insulation layer growth inhibitor x, which results in an optimal adaptation to an available manufacturing process. In particular for realizing embedded memory structures in other logic circuits (embedded process), this enables simultaneous production of different circuit modules in a common semiconductor substrate 1 and with the same production method.

According to Fig. 3F follows in a subsequent thermal Oxi now dationsschritt the actual sidewall oxidation, a layer thickness of a thermally formed electrical insulating layer 5 is dependent 3D introduced insulation layer-growth inhibitors of the x in Fig.. Specifically, this means that a surface of the semiconductor substrate 1 and the mask layer 4 has a relatively low oxide growth, since a large number of insulation layer growth inhibitors x or a high concentration of nitrogen is introduced as an oxidation inhibitor. The layer thickness d _{v of} the electrical insulation layer 5 in the vertical direction can therefore be set to very small values. In contrast, the implantation-free side walls of the gate stack GS are exposed to strong oxide growth, which is why an extraordinarily strong oxidation can be realized with the desired formation of bird beaks or birds peaks BP. The layer thickness d _{h of} the electrical insulation layer 5 in the horizontal direction is thus many times greater than the vertical layer thickness of the.

In this way, the sharp edges of the gate layer 3 are rounded off by the strong side wall oxidation or by the formation of the birds peaks BP in such a way that the field strengths occurring in this case (not shown) are substantially reduced and standardized. The occurrence of leakage currents in the field effect transistor according to the invention is thereby significantly reduced, with the charge holding properties in memory modules in particular being greatly improved. In addition, however, the reliability of the gate insulation layer 2 is also improved, which is particularly important in the production of non-volatile semiconductor memory cells with so-called “floating gate” field effect transistors.

According to FIG. 3G, a further implantation I _{S / D} for forming heavily doped source and drain regions S and D is carried out in a subsequent method step, wherein, for example, a self-adjusting process is again carried out using the oxidized gate stack GS. As an alternative to this, however, an auxiliary layer or a spacer can also be formed on the side walls of the gate stack GS, as is customary, as a result of which the heavily doped source and drain regions S and D in the semiconductor substrate 1 result.

What is essential for the present invention, however, is the selectively adjustable size of a scattering oxide SO required for this purpose, which is essentially determined by the vertical thickness d _{v of} the electrical insulation layer 5 . In particular in modern MOS transistor circuits with very small structure sizes, such thin and adjustable stray oxides are of great importance even after formation of a gate stack.

The thermal formation of the electrical insulation layer 5 is preferably carried out using a conventional thermal oxidation method, wherein preferably a polysilicon of the gate layer 3 is converted into SiO _{2 of} the surface insulation layer 5 . Accordingly, in the preferred exemplary embodiment according to FIG. 3, the gate insulation layer 2 , the mask layer 4 and the surface insulation layer 5 consist of SiO ₂ .

FIGS. 4A and 4B show simplified sectional views for illustrating the essential manufacturing steps of the field effect transistor according to a second embodiment of the invention, again like reference characters designate like or similar elements or layers as in Fig. 3A represent up 3G and will not be repeated description to follow.

According to Fig. 4A and 4B, only the essential for the invention process steps of the implantation of isolati x onsschicht growth inhibitors and presented to the thermal forming the electrical insulation layer 5, as they correspond to Figs. 3D and 3F, but more procedural rensschritte as shown in Figure are to apply. 3A-3C, 3E and 3D analog.

According to Fig. 4A is carried out in contrast to the similar Ver method step according to Fig. 3D, in the present second example exporting approximately an oblique implantation I _NS of insulation layer growth inhibitors x on the surface of the semiconductor substrate 1 and the gate stack GS. Such an oblique implantation I _NS can be advantageous, for example, if only a leakage current due to increased field strengths or damage to the gate insulation layer 2 is to be expected on the drain or source side. Further, 4A in FIG. Carried out a patterning of the gate stack GS such that the gate insulating film 2 is not completely removed and a residual insulating film on the semiconductor substrate 1 RI remains. Such a residual insulation layer RI can, for example, be useful as a scattering oxide for an implantation (not shown) of weak source and drain regions. However, it should be expressly pointed out at this point that the use of this residual insulation layer RI can also take place in the first exemplary embodiment according to FIGS . 3A to 3G.

According to FIG. 4A, the oblique implantation I _NS of insulation layer growth inhibitors x, which preferably have N, N ₂ or nitrides, both the surface of the semiconductor substrate 1 and the mask layer 4 and also a side wall of the gate stack GS facing the implantation bombarded with antioxidants. This results in essentially only one side wall free of oxidation inhibitors and a small section of the surface of the semiconductor substrate 1 , which lie in the shadow of the oblique implantation I _NS for implantation of the insulation layer growth inhibitor x.

Referring to FIG. 4B, which substantially corresponds to a method step according to Figure 3F corresponds., In a subsequent Her provision step, preferably by means of a thermal Ver procedure, the electric insulation layer 5 on the surface of the semiconductor substrate 1 and the residual insulation layer RI, and the gate stack GS trained. The electrical insulation layer 5 in turn has a thickness corresponding to the oxidation or growth inhibitors x introduced during the implantation according to FIG. 4A, a thick electrical insulation layer 5 being formed only on the side facing away from the implantation I _NS and otherwise (due to the built-in insulation layer growth inhibitor x) a thin SiO ₂ layer is formed. The surface insulation layer 5 acts here together with the residual insulation layer RI as a scattering layer SO, which can be used in a subsequent implantation process to form the heavily doped source and drain regions S and D.

Further, 4B result shown in FIG. Of birds beak or birds peaks BP and BP 'at the edges or corners of the gate layer 3, which is why, for example, selectively prevents gatein duzierter drain leakage current (GIDL, gate induced drain leakage, respectively) can. In this way, the short-channel properties of a field effect transistor can be further adapted or optimized to the respective requirements of an associated circuit, as a result of which, in particular, embedded charge processes for the formation of dynamic or non-volatile semiconductor memory cells can achieve optimum charge holding properties. Furthermore, the vertical layer thicknesses of scatter insulation layers SO can thereby be set exactly.

The invention has been described above with a polysilicon gate layer described. However, it is not limited to this and rather includes all other electrically conductive gates layers that by thermal oxidation the end enables formation of so-called birds peaks. Further was the invention using a simple field effect transistor structure described. However, it is not limited to this and rather also includes so-called non-volatile fields effect transistor structures with an additional floating or floating gate.

Claims (11)

1. Method for producing a field effect transistor with sidewall oxidation, comprising the steps:

• a) forming a gate insulation layer ( 2 ) on a semiconductor substrate ( 1 );
• b) forming a gate layer ( 3 ) on the gate insulation layer ( 2 );
• c) structuring the gate layer ( 3 ) and the gate insulation layer ( 2 ) to form a gate stack (GS);
• d) implanting insulation layer growth inhibitors (x) into the entire surface with the exception of at least one side wall of the gate stack (GS);
• e) thermally forming an electrical insulation layer ( 5 ) on the surface of the semiconductor substrate ( 1 ) and the gate stack (GS); and
• f) Formation of source and drain regions (S, D) in the semiconductor substrate ( 1 ).

2. The method according to claim 1, characterized in that the im Step d) implanted insulation layer growth inhibitor (x) have N, N2 or nitrides. 3. The method according to claim 1 or 2, characterized in that the implantation of the insulation layer growth inhibitor (x) in step d) perpendicular to the surface of the semiconductor substrate ( 1 ) it follows. 4. The method according to claim 1 or 2, characterized in that the implantation of the insulation layer growth inhibitor (x) in step d) takes place obliquely to the surface of the semiconductor substrate ( 1 ). 5. The method according to any one of claims 1 to 4, characterized in that the implantation of the insulation layer growth inhibitor (x) in step d) directly in the semiconductor substrate ( 1 ) and / or in a residual insulation layer (RI) of the gate Insulation layer ( 2 ) takes place. 6. The method according to any one of claims 1 to 5, characterized in that the training of the electrical insulation layer ( 5 ) in step e) represents a thermal sidewall oxidation. 7. The method according to any one of claims 1 to 6, characterized in that the training that of the source and drain regions (S, D) in step f) one Step to Form Strongly and Weakly Doped Source and draining areas, forming the weak doped source and drain regions (S, D) before or after Implant the insulation layer growth inhibitor (x) in Step d) takes place. 8. The method according to any one of claims 1 to 7, characterized in that the structuring of the gate layer ( 3 ) in step c) using a hard mask ( 4 ). 9. The method according to any one of claims 1 to 8, characterized in that the semi-conductor substrate ( 1 ) has Si. 10. The method according to any one of claims 1 to 9, characterized in that the gate layer ( 3 ) has polysilicon. 11. The method according to any one of claims 1 to 10, characterized in that the gate, residual and surface insulation layer (2, RI, 5) and the hard mask ( 4 ) have a silicon oxide layer.