DD301955A9 - Device for dynamically controlling the number of exchanges during a direct access - Google Patents

Abstract

The invention relates to a device for dynamically controlling the exchange point number in a direct access, which is used in the 16-bit microprocessor systems and microcomputers. The object of the invention is to provide a device for dynamically controlling the exchange point number in a direct access, which allows the execution of byte and word operations. This provides the possibility that the type of operation in direct access automatically during the exchange depending on the output for defining the word exchange of the 8-bit controller for direct access and the input / output devices in any number of bytes to be exchanged and the start address determines the number of digits of the module memory. This has been solved by a means for dynamically controlling the number of replacements in a direct access in which, in byte operations, the 16-bit information rail of the 16-bit microprocessor system is converted into an 8-bit rail and the 8-bit controller for direct access, set its counters with a one. In a word exchange, the 16-bit information rail is not converted and the 8-bit direct access controller sets its two-one counters. The advantages of the invention are that the replacement point number is automatically determined at the beginning of the execution and is not limited by the parity of the start address and the number of bytes to be exchanged. Fig. 1 {Dynamic Control, Exchange Number; 16-bit microprocessor system; direct access; Byte and word operations; Exchange of words; Module memory; Information rail; Parity; Start address}

Description

Circuit for converting the system and a circuit for determining the direction by which the bi-directional buffer for data is controlled. The 8-bit input / output devices and the module memory are associated with the higher -end or never-ending j-jj jtj. Bidirectional information rail, and the 16-bit input / output devices and the module memory are connected to the two information rails. The input for determining the disposition of the 8-bit memory of the unit for determining the configuration is connected to the corresponding outputs of the 8-bit module memories. The input to the memory of the configuration determining unit is in communication with the corresponding outputs of the 8-bit and 16-bit module memories. The input for determining the disposition of the input / output device of the unit for determining the configuration is connected to the corresponding outputs of the 8-bit and the I-bit input / output devices. The process of information exchange in direct access operation is controlled by the 8-bit direct access controller. During direct access, the 16-bit input / output devices and the 16-bit module memory are considered two separate 8-bit input / output devices and two separate 8-bit module memories.

In direct access, the 8-bit and 1-bit input / output devices control their output to determine the disposition of the input / output device, the 8-bit module memory controls its output to determine the disposition of the 8-bit Memory and the 8-bit and 16-bit module memories control their output for the memory type. Depending on the state of these three outputs, the configuration determining unit controls the intermediate buffer and converts the 16-bit microprocessor system information rail from a 16-bit to 8-bit information rail. This allows an exchange between a 16-bit module memory and an 8-bit input / output device, between a 16-bit input / output device and an 8-bit module memory, and between a 16-bit module memory. Input / output device and a 16-bit module memory comes about. The disposition of the 8-bit input / output devices and memory modules of the 16-bit system information rail is irrelevant.

A disadvantage of the device is that the information exchange is only a byte exchange, that is, it has a fixed number of digits. This results in a reduced exchange speed in the operation of direct access to the memory and inadequate use of the pass capability of the le-Cit system information rail. Devices for controlling byte and word exchange in the operation of direct access are known which use 16-bit controllers for direct access (eg 182 258 or MC68450). During initialization, the number of digits of the devices is specified, between which the exchange over the channel for direct access is realized. When the devices are 16-bit devices, the word exchange is realized only at a even initial address of the memory and an even number of bytes to be exchanged.

The disadvantage of these devices is that the number of digits of information exchange is static. It is programmed and can not be changed during the exchange of a data block between the memory and the input / output device. Another disadvantage of these devices is that the number of bytes to be exchanged and the starting address of the memory must be an even number.

Object of the invention

The aim of the invention is to largely avoid the aforementioned disadvantages.

Explanation of the essence of the invention

The object of the invention is to provide a device for dynamically controlling the exchange point number in a direct access, which allows, during the direct access, depending on the conditions, a byte or word exchange, d. H. a variable exchange is realized, and that the number of exchanged bytes and the initial value of the memory can be arbitrary.

According to the invention, the object is achieved by means for dynamically controlling the exchange point number in a direct access, which contains a 16-bit microprocessor system, wherein the highest-digit bidirectional information rail with the 16-bit memory and the 16-bit memory Input / output devices with the bidirectional information rails of an 8-bit memory, 8-bit input / output devices and an 8-bit controller for direct access and with the information input outputs "A" of an intermediate The least significant divisional information of the 16-bit microprocessor system is attached to the tffo r.ie original of the information bar of the 16-bit memory and the 16-bit input / output devices, to the bidirectional information bars of the 16-bit microprocessor 8-bit memory and the 8-bit input / output devices and to the information input / output "B" of the bidirectional buffer for data connected. The address outputs of the 16-B'ii microprocessor system are in conjunction with the address outputs of the 8-bit controller for direct access and with the address inputs of the 16-bit module memory and the 8-bit memory and the 8-bit controller. Input / output devices and the 16-bit input / output device. The zero address bit, the address for direct address access enable, and the input / output for defining the word exchange of the 8-bit direct access controller are associated with the corresponding inputs and the input / output of the controller connected to the exchange of words. The microprocessor channel request output and the microprocessor channel enable input of the 8-bit direct access controller are respectively connected to the corresponding input and output of the 16-bit microprocessor system. The input for the request for operation and the outputs for confirming the request of the 8-bit controller for direct access are corresponding to the corresponding outputs and inputs of the 8-bit input / output devices and the le-bit input / Output device connected. The output for determining the direction and the output for converting the system of the unit to determine the configuration are in communication with the corresponding inputs of the bidirectional buffer for data. The output for determining the disposition of the 8-bit memory is

connected to the corresponding output of the 8-bit memory. The 8-bit memory and 16-bit memory type output is connected to the corresponding input of the configuration-determining unit and the word-exchange control unit. The output for determining the arrangement of the input / output device in direct access of the 8-bit input / output devices and the 16-bit input / output device are in communication with the corresponding input of the unit for determining the Configuration. The output for the type of input / output device in direct access of the 8-bit input / output devices and the 16-bit input / output device are connected to the corresponding input of the control unit of the word exchange. The outputs for determining the replacement type of the 8-bit direct access controller are in communication with the corresponding inputs of the configuration determining unit and the word exchange control unit. The output for enabling a byte exchange and the output for determining the disposition of the byte from the 16-bit memory of the control unit of the word exchange are connected to the corresponding inputs for determining the configuration, and the output for the release of the highest-ranking rail is connected to the corresponding input of the 16 bit memory and the 1 ö bit input / output device. The unit for determining the configuration includes a circuit for blocking, a circuit for the recognizer of disposition of the memory, a circuit for the conversion of the system, and a circuit for determining the direction. The input for the type of memory, the input for determining the disposition of the 8-bit memory and the unit for determining the disposition of the input / output device in direct access of the unit for determining the configuration are inputs of the circuit for blocking , The output for defining the disposition of the cell from the memory of the memory disposition detection circuit is in communication with the corresponding inputs of the system converting circuit and the direction determining circuit. The input for enabling a byte exchange of the configuration determining unit is an input of the blocking circuit, the memory disposition detection circuit, the system converting circuit, and the direction determining circuit. The inputs for determining the replacement type of the unit for determining the configuration are an input for the direction of the circuit for determining the direction. The input for determining the disposition of the bytes from the 16-bit memory of the unit for determining the configuration of an input circuit for the dor F ^r know the disposition of the memory. The output for defining the memory of the circuit for detecting the disposition of the memory is connected to the corresponding inputs of the circuit for determining the direction and the circuit for converting the system. The output for defining the input / output device of the blocking circuit is in communication with the corresponding inputs of the circuit for determining the direction and the circuit for converting the system. The input for knowing the condition for converting the circuit and converting the system is connected to the corresponding input of the circuit for determining the direction whose output for selected direction is an input of the circuit for converting the system. The output for defining the 8-bit memory and the output for defining the 16-bit memory are inputs of the circuit for detecting the disposition of the memory. The output for determining the direction and the output for converting the system of the unit for determining the configuration are corresponding outputs of the corresponding circuits. The control unit of the word exchange includes a circuit for detecting the digit number of the exchange and a circuit for controlling the information rail. The output for the memory type, the output for the type of input / output device for a direct access, the inputs for determining the exchange type, the input for the release of the address in a direct access and the output for the release of a byte exchange The word exchange controller is the input and output of the replacement point number detection circuit. The zero address bit, the output for determining the disposition of the byte from the 16-bit memory and the output for the release of the highest-level rail of the control unit word exchange are input and outputs of the control circuit of the information rail. The input / output for defining the word exchange of the word exchange controller is an input / output of the exchange digit number detecting circuit. The output for enabling a byte exchange of the exchange point number detection circuit is an input of the control circuit of the information rail. The advantages of the invention are that the Austauschstellcnzahl automatically determined at the beginning and that the Stellonzahl of the parity of the start address and the number of bytes exchanged is not limited.

embodiments

On the basis of an exemplary embodiment of the invention, illustrated in the accompanying drawings, this will be explained in more detail. Show it

Fig. 1: a block diagram of the device for dynamically controlling the exchange point number in a direct access Fig. 2: a block diagram of the unit for determining the configuration Fig. 3: a block diagram of the control unit of the word exchange.

The device for dynamically controlling the exchange point number in a direct access (FIG. 1) comprises a 16-bit microprocessor system 1, the low-order bidirectional information rail 2 with the lowest-bidirectional information rail of the 16-bit memory 3 and the leverage. Bit input / output devices 4, with the bidirectional information bars of the 8-bit memory 5, the e-bit input / output devices 6 and 8-bit controller 7 for direct access and with the information input Outputs of the two-way intermediate buffer 8. The highest-order bidirectional information bar 9 of the 16-bit microprocessor system 1 is in communication with the highest-order information bars of the 16-bit memory 3 and the I-bit input / Output devices 4, with the bidirectional information bars of the 8-bit memory 10 and the 8- bit input / output devices 11 and with the information input / outputs " B "of the bidirectional buffer 8 for data. The address outputs 12 of the 16-bit micro-processor system 1 are connected to the address outputs of the 8-bit controller 7 for direct access and to the

Address inputs of the 16-bit memory 3, the first and second 8-bit memories 5 and 10, the 8-bit input-output devices 6 and 11 and the 16-bit input / output devices 4 connected. The zero address bit 13, the random access enable output 14 and the input / output 15 for defining the word exchange of the 8-bit direct access controller 7 are in communication with the corresponding inputs and the input / Output of the control unit 16 of the word exchange. The microprocessor channel request output 17 and the microprocessor channel enable input 18 of the 8-bit direct access controller 7 are respectively connected to the corresponding input and output of the 16-bit microprocessor system 1. The operation request inputs 19 and the outputs 20 for confirming the request of the 8-bit direct access controller 7 are in communication with the corresponding outputs and inputs of the 8-bit input / output devices 6 and 11, respectively and the 16-bit input / output device 4. The direction determining output 21 and the system converting output 22 of the configuration determining unit 23 are connected to the corresponding inputs of the bidirectional intermediate buffer 8 for data. The output 24 for determining the disposition of the 8-bit memory is connected to the corresponding output of the 8-bit memories 5 and 10. The output 25 for the type of memory of the 8-bit memories 5 and 10 and the 16-bit memory 3 is in communication with the corresponding inputs of the unit 23 for determining the configuration and the control unit 16 of the word exchange. The output 26 for determining the disposition of the direct access input / output device, the 8-bit input-output devices 6 and 11, and the 16-bit input / output device 4 are connected to the corresponding input of the unit 23 connected to determine the configuration. The input / output device type output 27 in direct access of the e-bit input / output devices 6 and 11 and the I-bit input / output device 4 are connected to the corresponding input of the control unit 16 of FIG Associated with word exchanges. The inputs 28 for determining the type of exchange of the 8-bit direct access controller 7 are in communication with the corresponding inputs of the configuration determining unit 23 and the word exchange 16. The byte exchange enable output 29 and the byte out prediction output 30 from the 16-bit memory of the word exchange controller 16 are connected to the corresponding inputs of the configuration determining unit 23, and the output 31 for the release of the highest-order rail is connected to the corresponding input of the 16-bit memory 3 and the 16-bit input / output device 4.

The configuration determining unit 23 (Fig. 2) includes a blocking circuit 32, a memory 33 for detecting the disposition of the memory 33, a circuit 34 for converting the system, and a circuit 35 for determining the direction. The input 25 for the type of memory, the input 8 for determining the disposition of the 8-bit memory and the input 26 for determining the disposition of the input / output device in a direct access of the unit 23 for determining the configuration are inputs of Blocking circuit 32. The output 36 for defining the disposition of the cell from the memory of the memory disposition detection circuit 33 is in communication with the corresponding inputs of the system converting circuit 34 and the direction determining circuit 35. The byte exchange enabling input 29 of the configuration determining unit 23 is an input of the blocking circuit 32, the memory disposition detection circuit 33, the system converting circuit 34, and the direction determining circuit 35 , The inputs 28 for determining the replacement type of the configuration determining unit 23 are an input of the direction determining circuit 35. The input 30 for determining the disposition of the byte from the 16-bit memory of the configuration determining unit 23 is an input of the memory disposition detection circuit 33. The output 36 for defining the memory of the memory disposition memory circuit 33 is in communication with the corresponding inputs of the direction determining circuit 35 and the circuit 34 for converting the system. The output 37 for defining the input / output device of the blocking circuit 32 communicates with the corresponding inputs of the direction determining circuit 35 and the system converting circuit 34. The conversion condition detecting output 38 of the system 34 converting circuit 34 is connected to the corresponding input of the direction determining circuit 35 whose output for a selected direction is an input of the system converting circuit 34. The output 40 for defining the 8-bit memory and the output 41 for defining the 16-bit memory are inputs of the circuit 33 for detecting the disposition of the memory. The output 21 for determining the direction and the output for converting the system 22 of the unit 23 for determining the configuration are corresponding outputs of the corresponding circuits 34 and 35th

The word exchange control unit 16 (Fig. 3) includes a replacement position number detecting circuit 42 and a control circuit 43 of the information rail. The type of memory input 25, the type of input-output device input 27 for direct access, the type of replacement input 28, the direct access address release input 14, and the output 29 for the input Release of the byte exchange of the word exchange control unit 16 are inputs and an output of the exchange position number detecting circuit 42. The zero address bit 13, the output 16 for determining the disposition of the byte of 16-bit memories, and the highest-level enable output 31 of the word-exchange control unit 16 are an input and outputs of the control circuit 43 of the information rail. The input / output 15 for defining the word exchange of the word exchange control unit 16 is an input / output of the exchange position number detecting circuit. The byte exchange enable output 29 of the exchange point number detection circuit 42 is an input of the information line control circuit 43.

The operation of the means for dynamically controlling the exchange point number in a direct access is as follows. When one of the e-bit input / output devices 6 or 11 or the 16-bit input / output device 4 activates its operation request output 19, the 8-bit controller 7 takes direct access this and activates its output 17 for the request to occupy the microprocessor. In the first approach, the 16-bit microprocessor system 1 frees the microprocessor channel by activating its output 18 to free the microprocessor channel. From this moment on, the 8-bit controller 7 for direct access is an information exchange control device and activates its output 20 to confirm the request of the corresponding input / output device. Depending on its number of digits, the input / output device controls

in a corresponding manner, its output 27 for the type of input / output device in direct access and its output 26 for determining the disposition of the input / output device in a direct access. The 8-bit direct access controller 7 addresses the cell from memory with which the input / output device will exchange information. Depending on the number of digits of the module memory in which the cell is located, it activates its output 24 for determining the disposition of the 8-bit memory or its output 25 for the type of memory. For a straight address, the 8-bit controller 7 activates its output 15 for defining the word exchange for direct access. Depending on which outputs of the input / output device and the module memory are activated, the configuration determining unit 23 correspondingly controls its output 21 for determining the direction and its output 22 for converting the system, and the control unit 16 of the word exchange its output 15 for defining the word exchange. The configuration determining unit 23 is turned on when the information exchange is a byte exchange, and converts the 16-bit microprocessor information rail into an 8-bit information rail by suitably setting the least significant 2 and the highest 9th Bidirectional information rail connects with each other. The word exchange control unit 16 is turned on when the 8-bit corgi roller 7 for direct access activates its address release output 28. When a request to operate from the 8-bit in / out device 6 or 11 and the cell addressed by the 8-bit direct access controller 7 from the memory belongs to the 8-bit memory 5 or 10, the Input 25 for the type of memory and the input / output device type input 27 are not active upon direct access of the word exchange controller 1C, and it activates its byte exchange enable output 29. The output 26 for determining the disposition of the input / output device in a direct access is active when the request from the e-bit input / output device 11 starts, and the output 24 for determining the disposition of the 8-bit Memory is active when the addressed cell belongs to the 8-bit memory 10. The configuration determining unit 23 converts the 16-bit information rail with a difference in states at the output 37 for defining the input / output device of the blocking circuit 32 and its output 36 for defining the disposition of the cell from the memory of the circuit 33 to recognize the disposition of the memory, d. I). when an exchange between an input / output device and a module memory is realized, connected to different halves of the 16-bit information rail of the 16-bit microprocessor system 1. The block circuit activates its output 37 to define the input / output device, if the input 26 is enabled to determine the disposition of the input / output device upon direct access by the configuration determining unit 33. The storage disposition detection circuit 33 activates its output 36 to define the disposition of the cell to the memory when the disposition disposition input de. 3-bit memory is activated or if, for an active input 25 for the type of memory, the input 30 for determining the disposition of the byte from the 16-bit memory of the unit 23 for determining the configuration is activated.

In an exchange in the operation of a direct access between the 8-bit input / output device 11 and the 8-bit memory 5, the output 26 for determining the disposition of the input / output device is active in a direct access, while the Output 24 is inactive for determining the disposition of the 8-bit memory. The word exchange control unit 16 activates its byte exchange enable output 29 and turns on the configuration determining unit 23. The blocking circuit 32 checks the state of the input 24 for determining the disposition of the 8-bit memory, the type of memory type input 25 and the input 26 for determining the disposition of the input / output device for direct access and activates only theirs Output 37 for defining the input / output device. The memory disposition detection circuit 33 does not assert its output 36 for defining the disposition of the cell from the memory. The system conversion circuit 34 activates the output 38 for detecting the condition for conversion, and turns on the direction determining circuit 35. It starts the monitoring of the state of its inputs 28zum determining the exchange type, and if the 8-bit controller 7 for direct access enabled, _s j _e bcjiimmt the direction of turning on the bidirectional Zwischer.puffers 8 for data, and activates its output 39 for the chosen direction. The system conversion circuit 34 of the configuration determining unit 23 converts the 16-bit information rail of the 16-bit microprocessor system 1, activating its output 22 to convert the system. The data is transmitted via the bidirectional buffer 8 for data from the bidirectional bidirectional information bar 9 of the bidirectional low-level information bar 2, and vice versa, depending on the state of the output 21 for determining the direction of the configuration determining unit 23. The replacement point number detection circuit 42 does not activate the word exchange input 15 of the 8-bit direct access controller 7, in which its counters are only one-one modified.

When exchanged in the operation of direct access between the 8-bit input / output device 6 and the 8-bit memory 10, the output 26 for determining the disposition of the input / output device is not active during direct access while the output 24 is active to determine the disposition of the 8-bit memory. The word exchange control unit 16 and the configuration determining unit 23 function as described. The blocking circuit 32 activates its output 40 to define the 8-bit memory and does not activate its output 37 for defining the input / output device. The memory position detection circuit 33 activates its output 36 to define the disposition of the cell from the memory. The direction of the bi-directional intermediate buffer 8 for data is determined in the opposite manner as described. The 16-bit information rail of the 16-bit microprocessor system 1 is converted and the data is transferred from the low-order bidirectional information rail 2 of the highest-order bidirectional information rail 9 and vice versa.

When exchanged in the operation of direct access between the 8-bit input / output device 6 and the 8-bit memory 5, the input 26 for determining the disposition of the input / output device is in direct access and the input 24 for determining the disposition of the 8-bit memory of the configuration determining unit 23 inactive, the 16-bit information rail of the 16-bit microprocessor system 1 is not converted, and the data is transmitted via the low-level bidirectional information bus 2. *** "

When exchanged in an operation of direct access between the 8-bit input / output device 11 and the 8-bit memory 10, the input 26 for determining the disposition of the input / output device is at a direct

Access and the input 24 for determining the disposition of the 8-bit memory of the configuration determining unit 23 are active, the 16-bit information rail of the IC microprocessor system 1 is not converted and the data has been transmitted via the highest-order bi-directional information rail 9 ,

When exchanged in the operation of direct access between the 8-bit input / output device 11 and the 16-bit memory 3, the output 26 for determining the disposition of the input / output device is in direct access and the output 25 active for memory type. At an address of the memory cell selected by the 8-bit direct access controller 7, the word exchange controller 16 does not assert its output 30 for determining the disposition of the byte from the 16-bit memory. The blocking circuit 32 activates its output 41 to define the 16-bit memory and its output 37 to define the input / output device, while the memory disposition detection circuit 33 does not energize its output 36 to define the disposition of the cell from the memory activated. The configuration determining unit 23 converts the 16-bit information rail of the 16-bit microprocessor system 1, and the data is transmitted through the bidirectional buffer 8 for data from the bidirectional bidirectional information rail 9 of the bidirectional lower information bar 2 and vice versa , depending on the state of the input 21 for determining the direction of the configuration determining unit 23. At an odd address of the selected cell from the memory, the word exchange controller 16 activates its output 30 to determine the disposition of the byte from the 8-bit memory, and the memory disposition detection circuit 33 activates its output 36 to define the disposition of the cell from the store. The configuration timing unit 23 of the configuration converts the 16-bit information rail of the 16-bit micro-processor system 1, and the data is transmitted through the highest-order bidirectional information rail 9.

When exchanged in the operation of direct access between the 8-bit input / output device 6 and the 16-bit memory 3, the output 26 for determining the disposition of the input / output device is not active during direct access while the output 25 for memory type is active. For a straight address of the memory cell selected by the 8-bit direct access controller 7, the word exchange controller 16 does not assert its output 30 for determining the disposition of the 16-bit memory byte. The blocking circuit 32 activates its output 41 to define the 16-bit memory and does not activate its output 37 for defining the input / output device, and the memory disposition detection circuit 33 does not activate its output disposition 36 Cell from the store. The configuration determining unit 23 does not convert the 16-bit information rail of the 16-bit microprocessor system 1 in which the data is transmitted through the low-level bidirectional information rail 2. At an odd address of the selected cell from the memory, the word exchange controller 16 activates its output 30 to determine the disposition of the 16-bit memory byte and the memory disposition detection circuit 33 activates its output 36 to define the disposition of the cell from the store. The configuration determining unit 23 converts the 6-bit information rail of the 16-bit microprocessor system 1, and the data is transmitted through the bidirectional dual-purpose buffer 8 for data from the bidirectional bidirectional information rail 2 of the bidirectional bidirectional information rail 9 and vice versa , depending on the state of the output for determining the direction 21 of the configuration determining unit 23. The high bit-rate enable input 31 of the 16-bit memory 3 is inverted to the zero address bit 13 from the address outputs 12 of the 8-bit direct access controller 7.

If the request to operate on the input 19 originates from the 16-bit input-output device 4 and the cell addressed by the 8-bit direct access controller 7 from memory belongs to the 8-bit memory C or 10 memory type output 25 is not active, and the word exchange controller activates its byte enable enable output 29. The 16-bit input / output device 4 monitors the state of the zero address bit 13 from the address outputs 12 of the 8-bit direct access controller 7 and the high-bit rail release output 31 of the word exchange controller 16 and detects with a difference in their state a byte exchange. In the byte swap, the 18-bit input / output device 4 is converted to one of 8-bit, and accordingly controls the output 26 for determining the disposition of the input / output device, depending on the disposition of the byte to be swapped in it. Device with a direct access. The remaining units and circuits of the device operate according to one of the methods described above.

When the request to operate from the 16-bit input / output device 4 and from the 8-bit controller 7 for a direct addressed cell from the memory belongs to the 16-bit memory 3, the output 25 is for the memory type 25 and the output 27 for type of input / output device 27 active. At a straight address of the selected cell, the 8-bit direct access controller 7 activates its output 15 to define the word exchange, the replacement position detection circuit 42 detects the beginning of the word exchange cycle and does not assert its output 29 for release a byte exchange. The configuration determining unit 23 does not respond. The information rail control circuit 43 asserts its output for the high-end rail release 31. When the 8-bit direct access controller 7 activates its output-determining outputs 28, the replacement point number detection circuit 42 activates its output 15 for defining the word exchange. At the end of the replacement cycle, the 8-bit direct access controller 7 modifies its counters with two and exchanges the word over the 16-bit information rail. At an odd address of the selected cell, the 8-bit direct access controller 7 does not assert its output 15 to define the word exchange. The replacement point number detection circuit 42 activates its byte exchange enable output 29 and the device operates according to the methods described above.

The means for dynamically controlling the exchange point number in a direct access may be implemented as an integrating circuit and allows the system to be powered on by more than one 16-bit module memory and one 16-bit input / output device.

Claims (3)

A device for dynamically controlling the access point number in direct access, comprising a 16-bit microprocessor system, from which the low-bit bi-direction information bar with the low-bit-two-way information bar of a 16-bit memory and from the 16-bit input / Output devices having the bidirectional information rails of an 8-bit memory, e-bit input / output devices, and an 8-bit direct access controller and the information input / outputs "A" of a bidirectional buffer for Data is communicated with the 16-bit microprocessor system's highest-order bi-directional information bar to the 16-bit memory's highest-order information bar and the 1-bit input / output device, the 8-bit memory bidirectional information and the 8-bit input / output devices and to the information input / outputs 'B' ^- the bi-directional buffer rs is connected to data in which the address outputs of the 16-bit microprocessor system with the address outputs of the 8-bit controller for direct access and with the address inputs of the 16-bit memory, the first and second 8-bit memory, the 8-bit input / output devices and the le-bit input / output devices are in communication, the output for the request for occupying the microprocessor channel and the input for the release of the microprocessor channel of the 8-bit controller for correspondingly connected to the corresponding input and output of the 16-bit microprocessor system, characterized in that the zero address bit (13), the address enable output (14) and the input / output (15) for defining the word exchange of the 8-bit controller (7) for direct access with the corresponding inputs and input / output of the control unit (16) of a word exchange in Ve The inputs to the request (19) and the outputs (20) to acknowledge the request of the 8-bit controller (7) for direct access are correspondingly to the corresponding outputs and inputs of the 8-bit input / Output devices (6 and 11) and the 16-bit input / output device (4) connected by the output (21) for determining the direction and the output (22) for converting the system of the unit (23) the input (24) for determining the disposition of the 8-bit memory with the corresponding output of the 8-bit memories (5 and 10) in FIG Connection is in which the output (25) for the memory type of the 8-bit memory (5 and 10) and the 16-bit memory (3) to the corresponding inputs (15) of the unit for determining the configuration and the control unit of the word exchanges s, the output (26) for determining the disposition of the input / output device upon direct access of the 8-bit input / output devices (6 and 11) and the 16-bit input / output device (4) communicate with the corresponding input of the configuration configuring unit (23), while the output (27) of the input / output device type of the 8-bit input / output device (6 and 11) and the 16-bit input / output devices (4) are connected to the corresponding input of the word-exchange control unit (16), the outputs (28) for determining the replacement type of the 8-bit direct access controller (7) are connected to the corresponding inputs of the unit (23) for determining the configuration and the control unit (16) of the word exchange, the output (29) for enabling the byte exchange and the output (30) for determining the disposition of the byte from 16-bit memory d the control unit (16) of the word exchange is connected to the corresponding inputs of the unit (23) for determining the configuration, while the exit (31) for release of the highest-level rail with the corresponding input of the 16-bit memory (3) and the 16-bit input / output device (4) is in communication. 2. The apparatus for dynamically controlling the exchange point number in a direct access according to claim 1, characterized in that the configuration determining unit (23) comprises a blocking circuit (32), a memory disposition memory circuit (33), a circuit ( 34) for converting the system and a circuit (35) for determining the direction in which the input (25) for the memory type, the input (24) for determining the disposition of the 8-bit memory and the input (26) for determining the disposition of the input / output device upon direct access by the unit (23) to Determining the configuration Inputs of the blocking circuit (32) are the output (36) for defining the disposition of the cell from the memory of the circuit (33) for detecting the disposition of the memory to the corresponding inputs of the circuit (34) for converting the system and the direction determining circuit (35), the byte exchange enabling input (29) of the configuration determining unit (23) having an input of the blocking circuit (32), an input of the circuit (33). for detecting the disposition of the memory, an input of the circuit (34) for converting the system and an input of the circuit (35) for determining the direction, while the input (28) for determining the type of exchange of the unit (23) for determining the Configuration (23) is an input for the direction of the direction determining circuit (35), wherein the input (30) determines the disposition of the byte from the 16-bit memory of the unit (23) for determining the configuration is an input of the circuit (33) for detecting the disposition of the memory, wherein the output (36) for defining the memory of the circuit (33) for detecting the disposition of the memory to the corresponding inputs of the circuit (35) for determining the direction in the circuit (34) for converting the system, the output (37) for defining the input / output device of the blocking circuit (32) with the corresponding inputs of the circuit (35) for determining the direction and the circuit (34) for converting the system is in communication, the output (38) for detecting the condition for converting the circuit (34) for converting the system (34) to the corresponding input of the circuit (35) for determining is connected to the direction whose output (39) for the selected direction is an input of the circuit (34) for converting the system, and the output (4Ό) for defining the 8-bit memory and the output (41) for defining the 16-bit memory Inputs of the circuit (33) for detecting the disposition of the memory are by the output (21) for determining the direction and the output (22) Converting the system of the unit (23) for determining the configuration corresponding outputs of the corresponding circuits (34 and 35). 3. A device for dynamically controlling the exchange point number in a direct access, according to claims 1 and 2, characterized in that the control unit (16) of the word exchange, a circuit (42) for detecting the exchange point number (42), and a control circuit (43) information rail containing the memory type input (25), the input / output device type input (27), the replacement type input (28), the input (14) for enabling the address in the case of direct access (14) and the output (29) for the exchange of bytes of the control unit (16) of the word exchange (16) are inputs and an output of the circuit (42) for detecting the exchange point number; the zero address bit (13), the output (30) for determining the disposition of the 16-bit memory byte and the highest-rail enable output (31) of the word-exchange control unit (16), an input and outputs of the control circuit (43) of the information rail, wherein the input / output (15) for defining the word exchange of the control unit (16) of the word exchange is an input / output of the circuit (42) for detecting the exchange point number, and the output (29) for release of the byte exchange of the circuit (42) for detecting the exchange point number is an input of the control circuit (43) of the information rail and an output of the control unit (16) of the word exchange. For this 2 pages drawings Field of application of the invention The invention relates to a device for dynamically controlling the Aiistauschstellen number in a direct access, which is used in the 16-bit microprocessor systems and microcomputers application. Characteristic of the known state of the art There is known a device for controlling byte-serial direct access to the memory of a 16-bit microprocessor system (BG Certificate No. 70026 "Device for Controlling Byte Sequential Direct Access to the Memory of a 16-Bit Microprocessor System ⁴ ) which includes a 16-bit microprocessor system, an 8-bit direct access con fi gurant, bi-directional intermediate data buffer, and a configuration determination unit. The unit for determining the configuration includes a blocking circuit, a memory disposition detection circuit, a circuit