DD297731A5 - METHOD AND CIRCUIT FOR TESTING SAVINGS WITH OPTIONAL ACCESS - Google Patents

Abstract

The present invention is preferably used for the self-test of embedded in user-specific circuits RAM in different life phases and different functional environment. It solves the task of realizing a test of these memories based on sample test sets, passing through several test cycles in which the starting state of the test pattern generator (TMG) used to stimulate the memory with cycle-to-cycle different test vectors is no longer changed by external means Musz. After initialization of the TMG, the current state of the TMG, which switches on after each write operation, is successively written into the addressed memory cells in a first test phase for all address assignments of the memory. Subsequently, in a second test phase, the contents of the addressed memory cells are successively cyclically compared with the phase-corrected state of the TMG for all address assignments of the memory and an error message is output in the event of a mismatch, then the current state of the TMG is written into the addressed memory cells and the TMG is forwarded after each write operation , Fig. 1 {memory, random access; R.A.M; Compact test; Self-test; Pattern method; Sample kit; Error detection probability; Effort acceptance; Pseudo-random generator; Phase shift network, linear}

Description

For this 2 pages drawings

Field of application of the invention

The invention relates to a method and a circuit arrangement for testing Random Access Memory (RAM) using sample test sets, the proposed solution being suitable for conversion to an integrated test arrangement; and preferably for the complete or partial self-test embedded in user-specific circuits read-write memories, but also of highly integrated RAM circuits, in different phases of life and different functional environment is used.

Characteristic of the known state of the art In the course of the production of embedded in user-specific circuits (ASIC) memories (embedded memories) and

microelectronic memory circuits, but also the user, are comprehensive to prove the usability

Tests of the memory cells and the other functional units of the semiconductor memory circuit required. In order to test random access memories (RAM, read-write memory), the pattern methods are generally known

and introduced.

It is based on the proof of the absence of hypothetical errors, i. H. on their stimulation by means of suitable test patterns

and their detection, addressed.

As error models for the stimulation in general sticking errors in memory cells and / or in the control logic and / or

or in the read / write lines, crosstalk between adjacent memory cells as well as pattern-dependent error baselines.

The stimulation can take place in a deterministic or random manner. A variety of methods are known for a deterministic stimulation (see Gavrilov, V. A .: Testy dlja proverki

poluprovodnikovych BIS OZU. Cifrovye ustrojstva i mikroprozessory; 1979; No.3; S.135-152).

They take account of different error classes, resulting in a different algorithmic complexity,

which ultimately determines the necessary test time.

When implementing a self-test method in a circuit arrangement, i. H. the corresponding self-test hardware, is

the algorithmic structure determining for the additional required overhead ("overhead") and thus for its economic acceptance.

Known solutions are therefore also limited error models and relatively simple algorithmic structures

based.

Thus, in EP-Anm. 263312 set out a solution for testing for single bit errors. In this case, the memory cells of a RAM to be tested are successively described by a test circuit and again

read. If the values read out do not correspond with the values written in, ie bit distortions, then a

Error signal generated and output. This very simple error model is limited in other known self-test methods or arrangements

extended by decoder and pattern dependent errors.

A corresponding method is z. B. in EP-Anm. 262867, which relates to the production of a checkerboard pattern

("Chackerboard-pattern") is addressed.

In addition to the single-bit errors, the crosstalk between adjacent cells and selected ones is also determined Decoding error detected. However, for the complete recognition of unrestricted pattern-dependent errors, (3 n (oxp 2) + 2 n) * 2 (exp n) (with

2 (exp n) ... number of memory cells of the memory under test, i. n ... Number of address inputs) Required test steps (see Hayes, J.P .: Testing memories for single-cell pattern sensitive faults IEEE Transactions on computers; C-29 (1980);

P.249). Such an examination is not possible in time.

A good compromise with regard to the required test time, the additionally necessary hardware expenditure and the achievable error coverage can be achieved with the use of random sample test sets.

In this case, a set of test vectors is generated which are not based on a deterministic error model but excite errors with a certain probability, the sufficient amount of which must be secured by the design of the procedure.

The recognition probability ρ for an error i depends on the sample size η and the excitation frequency xi and converges to p (i)> 1-e (exp -nxi).

A sampling test set can be generated relatively simply in terms of circuitry. Another advantage is the potential possibility to stimulate different Fehlerklasson.

Known methods for testing random access memories using random sample sets use pseudorandom maximum cycle length pseudo-random generators to stimulate the successively addressed memory cells of the RAM under test.

In order to achieve a sufficient error coverage usually several addressing cycles are traversed, wherein the stimulation of the memory is required with cycle by cycle different test vectors.

Such a method is z. B. in DD-WP 252 698 described. Here it is proposed to address the memory to be tested pseudorandomly or to describe and describe it with dual bit sequences or to address it in a dual way. For stimulation with varied test vectors in the Einzo'nen address cycles of the starting state of the test pattern generator used is changed by external means.

A disadvantage of the implementation of such methods in integrated self-test arrangements is the associated additional circuit complexity.

Object of the invention

The object of the invention consists in a reduction of the additional hardware required for the realization of integrated self-test arrangements with a test quality which is at least equal to that of known adequate solutions.

Explanation of the essence of the invention

The invention has for its object to develop a method and a circuit arrangement for the test of random access memory, which realize a test based on random sample sets, wherein to increase the error detection probability several test cycles are passed, in which to stimulate the memory of cycle to cycle different test vectors, the starting state of a pseudo-random generator used no longer needs to be changed by external means.

To solve the problem, a method for testing random access memories using random test sets is proposed, wherein at the beginning of the test, a used test pattern generator with the cycle length 2 (exp m) -1 is initialized and thereafter in a first test phase successively for aile 2 (Exp) address assignments of the Spoichers the current state of the test pattern generator written in the addressed memory cells and the test pattern generator is incremented after each write operation.

According to the content of the addressed memory cells is then cyclically successively read in a second test phase cyclically for all address assignments of the memory, compared with the phase-corrected state of the test pattern generator and output an error message in case of non-compliance. Subsequently, the current state of the test pattern generator is written into the addressed memory cells and the test pattern generator is incremented after each write operation.

The cycles of the address assignments in the mentioned test phases are identical, ie. H. In the second test phase, all addresses are generated cyclically one after the other in the same order as in the first test phase.

In an embodiment of the method according to the invention, the phase-corrected state of the test patterngonerator used is derived from the current state of the test pattern generator.

Preferably, for the phase-corrected state used, the current state of the test pattern generator is increased by 2 (exp

n) module 2 (exp m) -1 steps shifted.

The cycle length of the test pattern generator used of 2 (exp m) -1 is the length of the address cycle of 2 (exp n) for each pair of values (n, m) with m; η greater than 1 prime.

This results in the significant advantage of the solution according to the invention that the test pattern generator after a single initialization at the beginning of the test with a state of the maximum cycle, the memory successively stimulated with 2 (exp m) -1 different, 2 (exp n) vectors comprehensive test sets without it It would be necessary to change the starting state of the test pattern generator from cycle to cycle with external means.

To ensure a representative random test, the order of generation of the addresses and test data is adjusted to the internal memory architecture so that no cell, column and diagonal correlations occur.

Further favorable embodiments of the method are obtained by terminating the test before the execution of the maximum test cycle after issuing an error message or after decoding a previously agreed state of the test pattern generator and a previously agreed address assignment.

This results in a further shortening of the test time.

To achieve the object, in the implementation of the method, a circuit arrangement for testing random access memories is proposed, which uses linear feedback shift registers and an address counter, which are connected to clock and initialization signals of the circuit arrangement, wherein outputs of Adreßiählers with the address inputs and the outputs the linear feedback shift register are connected to the data inputs of the memory under test and wherein the data outputs of the circuit arrangement are realized by the data outputs of the memory.

According to the address counter used (n + 1) -stellig (with n ... number of address inputs of the memory to be tested) is configured. Its least significant output is applied to the read / write control input of the memory and a shift clock input of the linear feedback shift register, the remaining outputs are connected to the associated address inputs of the memory. The data outputs of the linear feedback shift register are further applied to the data inputs of a linear phase shift network. The data outputs of the memory and of the linear ^Phasenvers': ebungsnetzwerkes are connected to associated inputs of a comparator, at whose output a signal of the comparison result is generated.

In a first embodiment variant of the circuit arrangement according to the invention, the address counter is a first one

Test end signal leading carry output provided. .,

When the end of an addressing cycle is reached, this is evaluated as a first test end condition.

In a further embodiment variant, the linear feedback shift register is provided with a comparator output leading to a second test end signal.

Thus, a predetermined registor state is decoded at the comparator output as the second test end condition.

A favorable embodiment variant of the invention is obtained by connecting the carry output of the address counter to an input of a trigger, by placing said initialization signal on the second input of the trigger and by generating a status signal "test initialization phase" at the output of the trigger.

At the beginning of the test, the start signal is reset by the initialization signal and a start value from the maximum cycle is set in the linear feedback shift register. At the same time, the trigger is set to the "initialization phase" status, which is output via the status signal.

Triggered by a corresponding control signal coding, the address counter now cycles through all 2 (exp n) addresses of the memory.

With the derived from the least significant Auegang the address counter shift clock, which also acts as a read / write switching signal for the memory, the memory in a first phase of the write / Lose switching signal is read and in the second phase with the data at its inputs current state of the linear feedback shift register described. The linear feedback shift register is incremented by the shift clock signal after each memory write operation.

In this case, in each read cycle, the state at the outputs of the memory is compared with the phase-corrected network phase-corrected state of the linear feedback shift register in the comparator. A detected deviation is output via the signal of the comparison result.

At the end of the first addressing cycle, the first test end signal appears at the carry output of the address counter, which switches the trigger to the "test phase" status, which is output via the status signal.

In all subsequent cycles, which proceed analogously to the described first cycle, a diagnostic signal is generated from the states of the mode control signals, the write read switching signal, the status signal and the signal of the comparison result, via which the test result is output.

This results in an evaluation of the generated at a detected deviation at the output of the comparator signal of the Vergleichsergebnissos only after a complete write cycle.

The end of the test is reached when the two test end signals are active at the same time.

In a further embodiment of the invention, the address counter from a connected to the test clock and the least significant output of the address counter leading 2: 1 binary divider and a clocked by the output of the binary divider and the other outputs realized feedback shift registers configured.

To reduce the additional circuitry required, the linear feedback shift register can be biw by function conversion of data registers controlled via modu & tax signals. the address counter may be configured by function conversion of address registers of the memory.

A further advantageous embodiment variant of the circuit arrangement according to the invention is characterized in that a plurality of memory to be tested on the input side are connected in parallel, that the data outputs of each memory are performed on their associated inputs each having a comparator whose remaining inputs are connected to the associated outputs of the linear phase shift network and that each comparator has an output leading the signal of the respective comparison result.

This can again be achieved a significant reduction in the required for testing a memory relative hardware cost and the relative test time.

exemplary

The invention is explained below with reference to an embodiment, two drawings and two tables. Show

Fig. 1: the circuit arrangement according to the invention

Fig. 2: the configuration of a linear feedback shift register with connected linear Phasonverschiebungsnetzwerk

Tab. 1: the logic table of the linear phase shift network Tab. 2: an excerpt of the test data sequences entered into the memory.

At the beginning, the sequence of the method according to the invention will be explained in more detail:

Before the start of the test, a used test pattern generator having a cycle length of 2 (exp m) -1 is initialized. Thereafter, in a first test phase, successively all 2 (exp n) address assignments are applied to the memory and, for each address assignment, the current state of the test pattern generator incrementing by one step after each memory write operation is written into the addressed memory cells. In a si: h subsequent second test phase

are cyclically successively all address assignments in the same order as in the first test phase b 'witnesses. The successively addressed memory cells are read first, the data read out are compared with the state of the test pattern generator phase-shifted by 2 (expm) modules 2 (expm) -1 steps, and the addressed memory cells are then rewritten with the current state of the test pattern generator. The test pattern generator switches on by one step after each write operation. If a deviation is detected during the comparison, an error message is output. The second test phase is repeated maximally until the memory has been successively stimulated with 2 (exp m) -1 different sets of 2 {expn) vectors. The test can be terminated prematurely if an error message is issued or if the address assignment at the end of a cycle and a predefined state of the test pattern generator have been decoded.

Now, the circuit arrangement according to the invention will be explained in more detail; As shown in FIG. 1, in addition to the memory (RAM) 1 to be tested, it contains a linearly fed-back shift register 2

(hereinafter referred to as LFSR) having a comparator output K, a binary counter used as an address counter 3, which has n + 1 digits (with n ... number of address inputs of the memory 1) and carries a carry output UE, a linear one

Phase shift network 4 (hereinafter referred to as LPVN), a comparator 5 and a trigger 6. Instead of the binary counter 3 is also a circuit of a 2: 1 binary divider with a fed back 'ichieberegister the Cycle length 2 (exp n) usable. Representative of the system integration of the circuit arrangement according to the invention is as address. Shler working Binary counter 3 is not functionally convertible. In contrast, the LFSR 2 is a function-converted Input register of the circuit. The circuit arrangement has m data inputs IN 1 ... INm, m data outputs 0UT1 ... OUTm and η address inputs ADR1 ... ADRn provided. It is supplied with a user clock signal CP, a test clock signal CT, a User mode signal AM and an initialization signal SET driven. Furthermore, she runs a read / write Switching signal R- / W, a signal of a comparison result V, two test end signals TE 1; TE 2 and a status signal "Test / Initialization phase "El. The data inputs IN 1... IN m of the circuit arrangement are related to the data inputs Dl 1... Dl m assigned to them User clock signal CP is applied to the clock input CPI of the LFSR 2. The user mode signal AM is on an input P- / S

for parallel / serial operation switching of the LFSR 2 and the control input / OE of the binary counter 3; the initialization signal

SET is routed to the initialization input SETI of the LFSR2 and the reset input R of the binary counter 3. The clock input C of the binary counter 3 is connected to the test clock signal CT. Its carry output UE carries the first test end signal TE 1, the Comparator output of the LFSR 2, the second test end signal TE 2. The outputs Q2 ... Qn + 1 of the binary counter 3 are via high-impedance switchable driver (not shown) with the associated Address inputs Al 1 ... Al η of the memory 1, which at the same time at the address inputs ADR1 ... ADRn the circuit arrangement

lie, connected.

The low-order output Q1 of the binary counter 3 carries the internal schroib / read switching signal R- / W and is one

high-impedance switchable driver (not shown) to the shift clock input CSI of the LFSR 2 and the inverted write /

Read input / R-Wl of the memory out. Furthermore, the transmission output UE of the binary counter 3 with a set input S of the trigger 6, the reset input R is connected to the initialization signal SET connected. The output of the trigger drives the status signal El. The outputs Q1 ... Qm of the LFSR 2 are related to their data inputs DU ... DIm of the memory 1 and the Data inputs Dl 1 '... Dl m' of the LPVN4 placed. The data outputs D01 ... DOm 'of the LPVN4 and the data outputs D01... DOm of the memory 1 are each connected to inputs of the comparator 5 assigned to them. At theirs Output is the signal of the comparison result, which is tapped to form the test result. The data outputs D01 ... DOm of memory 1 simultaneously provide the data outputs 0UT1 ... OUTm the Circuit arrangement. The mode of operation of the circuit arrangement according to the invention according to FIG. 1 will be described below: The operating modes of the circuit arrangement or the individual phases of the test are coded by the following signal play: Mode AM SET Ü

user mode 1 O X Initialize the test pattern generator undAdreßzählers X 1 X 1st phase: initializing the memory O O O 2nd phase: test O O 1

(with X ... any)

In user mode, the output drivers of the binary counter 3 are high-order; the l.FSR 2 works as a parallel register, where

the data transfer is clocked by the user clock signal CP.

If the initialization signal SET leads to the logical value "1", the binary counter 3 is reset

set in the maximum cycle start word. Trigger 6 is set to the status 'Initialization phase' ¹ , ie the

Status signal El carries the value "0". To carry out the storage test, the control signal coding AM = 0; SET = O set. This will be the parallel Register in the feedback slider register 2 switched. In this mode, it is via its shift clock input CSI from the least significant output Q1 of the binary counter 3 removed write / read switching signal R- / W, the so

also acts as a shift clock, clocked. This will cause the LFSR 2 to increment by one step after each memory write operation.

At the same time, the binary counter 3 counts when the control signal coding AM = 0; SET = O Cyclic all 2 (expn) addresses of the Memory 1 by.

For each address assignment, the memory I is first read and then described with the present at its data inputs Dl 1 ... DIm current state of the LFSR2.

In each Leophase the write '/ read-switching signal (shift clock) while the state of the outputs D01 ... DO m of the memory 1 is compared with the phase-corrected via the LPVN4 state at the data outputs Q1 ... Qm of the LFSR2. At the end of the first complete cycle of the binary counter 3, the first test end signal TE 1 is at the transmission output UE of the binary counter 3. This is at the set input of the trigger 6 and switches it to the status "test phase", ie the status signal El carries the value "1".

In the following cycles, which in their sequence correspond to the first addressing cycle, in addition (not shown) in accordance with the billing rule FM = / AM * R * El * V (with R... Read phase of the write / read switching signal R) / W) generates and outputs a high-active diagnostic signal FM (error magazine).

As a result, an evaluation of the signal generated at a detected deviation at the output of the comparator 6 of the comparison result V only after execution of a complete write cycle.

The end of the test is reached when a test end signal TE formed according to the instruction TE = TE 1 "TE 2 is active. 3 shows the structure of an LFSR 2 with associated LPVN 4 configured to test a 4 * 512 bit RAM. The LFSR 2 is made up of four series-connected register cells 2.1... 2.4, the outputs of the register cells 2.1... 2.4 representing the outputs Q1... Q4 of the LFSR2. In accordance with the selected feedback polynomial, the outputs of the third 2.3 and fourth register cell 2.4 modulo-2 are added to the input of the first register cell 2.1. Thus, the LFSR 2 has a cycle length of 2 (exp 4) - 1 = 15 and cyclically generates the hexadecimal number sequence ...; 1; 2; 4; 9; 3; 6; D; A; 5; B; 7; F; e; C; 8; ... The outputs QL. .0.4 of the LFSR 2 are connected to their associated inputs DU ... DIm of the LPVN4.

The LPVN 4 is designed for a phase shift of 512 modulo 15 = 2. For this purpose the input Dl 3 is connected directly to the output D01 and the input DI4 directly to the output D02. Input Dl 1 is added to input DI4 modulo-2 added to output D03, for output D04 output D03 modulo-2 is connected to input Dl 2. The logic table belonging to the circuit arrangement according to FIG. 2 is shown in Tab. Tab. 2 shows a section of the test sequences entered into the memory.

Table 1 linear phase shift network

entrance Q4 03 02 01 4 exit DO 4 ' D03 ' 509 DO 2 ' DOV H O 0 0 1 H 1 1 0 0 1 O 0 1 0 C 1 0 0 0 2 O 1 0 0 8th 0 0 0 1 4 1 0 0 1 1 0 0 1 0 9 O 0 1 1 2 0 1 0 0 3 O 1 1 0 4 1 0 0 1 6 1 1 0 1 9 0 0 1 1 D 1 0 1 0 3 0 1 1 0 A O 1 0 1 6 1 1 0 1 5 1 0 1 1 D 1 0 1 0 B O 1 1 1 A r. 1 0 1 7 1 1 1 1 5 1 0 1 1 F 1 1 1 0 B 0 1 1 1 e 1 1 0 0 7 1 1 1 1 C 1 0 0 0 F 1 1 1 0 8th Table 2 e test Script address 0 12 3 7 ... 508 510 511 5 6

1 2 4 9 3 6 D A. .. C 8th 1 2 4 9 3 6 D A 5 B. .. 1 2 4 9 3 6 D A 5 B 7 F. .. 4 9 3 6

Claims (13)

A method for testing random access memories using random sample sets, wherein at the beginning of the test, a used test pattern generator having the cycle length 2 (exp m) -1 is initialized and thereafter in a first test phase successively for all 2 (exp n) address assignments the memory of the current state of the test pattern generator is written into the addressed memory cells and the test pattern generator is incremented after each write operation, characterized in that subsequently in a second test phase cyclically successively for all address assignments of the memory, the content of the addressed memory cells compared with the phase-corrected state of the test pattern generator and in the event of a mismatch, an error message is output and the current state of the test pattern generator is now written into the addressed memory cells and the test pattern generator is forwarded after each write operation. 2. The method according to claim 1, characterized in that the used phase-corrected state of the test pattern generator is derived from the current state of the test pattern generator. 3. The method according to claim 2, characterized in that for the used phase-corrected state of the test pattern generator, the current state of the test pattern generator by 2 (exp n) modulo 2 (exp m) -1 steps is shifted. 4. The method according to any one of the preceding claims, characterized in that the test is terminated after the output of an error message. 5. The method according to any one of the preceding claims, characterized in that the test is terminated after decoding a pre-agreed state of the test pattern generator and a previously agreed address assignment. 6. Circuitry for testing random access memories, using linear feedback shift registers and an address counter connected to clock and initialization signals of the circuit, said outputs of the adder having the address inputs and the outputs of the linearly coupled Sc ', live register having the Data inputs of the memory to be tested are connected and wherein the data outputs of the circuit arrangement are realized by the data outputs of the memory, characterized in that the address counter used (3) (n + 1) -stellig (with n ... number of address inputs of the tested Memory) and its least significant output (Q 1) is passed to the write / read control input (/ R-Wl) of the memory (1) and a shift clock input (CSI) of the linear feedback shift register (2) that the data outputs ( Q 1 ... Qm) of the linear feedback shift register (2) in the further au f the data inputs (Dl 1 '... DIm') of a linear phase-shifting network (4) are laid and that the data outputs (D01 ... D0m; DO '1 ... DO'm) of the memory (1) and the linear phase-shifting network (4) are associated with their inputs associated with a comparator (5), at whose output a signal of the comparison result (V) is generated. 7. Circuit arrangement according to claim 8, characterized in that the address counter (3) with a first test end signal (TE 1) leading carry output (UE) is provided. 8. Circuit arrangement according to claim 6 or 7, characterized in that the linear feedback shift register (2) with a second test end signal (TE 2) leading comparator output (K) is provided. 9. Circuit arrangement according to claim 7, characterized in that the carry output (UE) of the address counter (3) with an input (S) of a trigger (6) is connected, that said initialization signal (SET) to a second input (R) of the Triggers (6) is set and that at the output of the trigger (6) a status signal "test / initialization phase" (El) is generated. 10. Circuit arrangement according to one of claims 6 to 9, characterized in that the address counter (2) from oinem connected to a test clock (CT) and the output (Q 1) leading 2: 1 binary divider and one from the output (Q 1) of the binary divider clocked and the outputs (Q2 ... Qn + 1) realizing feedback shift register is configured. 11. Circuit arrangement according to one of claims 6 to 10, characterized in that the linear feedback shift register (2) is controlled by mode control signals (AM) controlled function conversion of data registers of the memory (1) and in that data inputs (IN 1 ... INm ) of the circuit arrangement on them associated data inputs (Dl 1 ... DIm) of the linear feedback shift register 2 are performed. 12. Circuit arrangement according to one of claims δ to 11, characterized in that the address counter (3) d'irch via mode control signals (AM) controlled function conversion of address registers of the memory (1) is configured. 13. Circuit arrangement according to one of claims 6 to 12, characterized in that a plurality of memory to be tested (1) are connected in parallel on the input side, that the data outputs (D01 ... DOm) of each memory (1) to their respective inputs one Comparator (6) are guided, the remaining inputs to the associated outputs (DOT ... DOm ') of the linear phase-shifting network (4) are connected and that each comparator (6) has a signal leading to the respective comparison result output (V).