DD273722A1 - ARRANGEMENT FOR REDUCING THE LATCHUP EFFECT IN INTEGRATED CMOS CIRCUITS - Google Patents

Abstract

The invention relates to an arrangement for reducing the latch-up effect in integrated CMOS circuits. The invention has for its object to provide an arrangement for reducing the latch-up effect, which allows to minimize the n -p distance, without increasing the Stromverstaerkungswerte the parasitic bipolar transistors. According to the invention, the object in integrated CMOS circuits with pn isolators is achieved by arranging an additional guard ring at a corresponding distance around the respective well region and having the opposite conductivity type as the substrate or epitaxial layer. Fig. 3

Description

For this 6 pages drawings

Field of application of the invention

The invention relates to an arrangement for reducing the latch-up effect in integrated CMOS circuits, in particular in highly integrated CMOS circuits mii k! ..! Ien n ^{+ +} p ⁺ intervals.

Characteristic of the known technical solutions

Arrangements for reducing the latch-up effect are known from the literature. So z. As proposed in EP142 258, using a substrate bias to reduce the latch-up effect (thyristor effect).

Another variant is given in EP121096 for an n-well technology. Here, the n-well contact is doped so high and so closely adjacent to the p ⁺ source region that a tunnel diode becomes active which biases the n-well slightly toward the p ⁺ regions in the reverse direction.

In EP 213425 an arrangement is proposed which uses a substrate bias in conjunction with a Schottky diode to reduce the latch-up effect.

The solution according to EP197730 uses special well contacts to this. To reduce the effect and in WO 85/04525 a special well arrangement is specified with a specific impurity distribution in the tubs.

Other papers that consider the latchup effect are known from the journal literature. So describe A.W. Wieder

et al. in "Design model for bulk CMOS scaling enabling accurate latchup prediction" in ED-30 (1983) No.3, pp 240-245 a double-well CMOS process, the highly doped n ⁺ substrate with a 3 μπι thick η Among other things, it is stated that an epitaxial layer is mandatory for good latch-up security, and the low-resistance substrate greatly reduces the substrate resistance over that of a CMOS bulk process, thereby increasing latchup safety

AG Lewis also came to this conclusion in "Latchup suppression in finedimension shallow p-well CMOS circuits" in ED-31 (1984), No. 10, pp. 1472-1481, investigating epitaxial layer thicknesses of 1 to 5 pm with concentrations between 2 ... 4 · 10 ¹⁵ cm " ³ .

In IEDM 86, pp. 243-251, he published further investigations on the latch-up effect, which have a three-dimensional model as a basis. In order to increase the latchup holding voltage, epitaxial layers are also proposed here.

MC Chen et al., In "A high performance submicron CMOS process with self-aligned chan-stop and punch-through implants (twin-tub V)" in IEDM 86, pp. 256-259, examine the latchup withstand voltage versus n ⁺ -p ⁺ distance, with different epitaxial layer thicknesses as parameters.

M. Yoshimoto et al. use in "A latchup-free CMOS RAM cell with well-source structure" in J.S.S., SC-22, No.4, Aug.87,

Pp. 538-542, the η-well as a supply line for UDD and thus ensure that the η-well is biased always positive than the present in the η-well p ⁺ source-drain regions. A disadvantage of this arrangement, the high resistance of the η-tub, so that this variant is not überali used. H.Shinohara et al. See "A nearly 8Kx8 mixed CMOS static RAM" in ED-32, No.9, Sept. 85, pp. 1792-1796, highly doped rings within the wells and thus achieve a reduction in the current gain values of the lateral transistors u.id a reduction in the resistances in the individual wells.This arrangement, the trigger-on voltage could be postponed to about 13 volts.

D.Takacs et al., In "Surface Induced Latchup in VLSI CMOS circuits" in ED-31, No.3, p.279-286, investigates the influence of a polysilicon conductive line that passes over a thick field oxide with underlying active areas If too little n ⁺ -p ⁺ -areas (<24μιπ) occur on this polysilicon gate voltage peaks of about 10 volts, it may already come to turn on the parasitic thyristor.These voltage spikes can be capacitively coupled from the outside and then lead at appropriate points of the circuit for switching on the parasitic thyristor and thus to the failure of the function of the relevant circuit part.

It is stated that a reduction of the latch-up effect by sufficiently large n ⁺ -p ⁺ spacings and high Feldschwellspannungen can be reached.

All this work shows that the latchup sensitivity can be reduced by the measures mentioned, but can not be eliminated.

In Fig. 1, the known arrangement of n- and p-channel transistor in a p-well CMOS technology is shown again and will be explained in more detail in connection with the equivalent circuit diagram in Fig. 2.

1, a highly doped substrate 1 (η-type) having a concentration of 10 ¹⁸ ... 10 ¹⁹ cm ^{-3 is} used. Then, an epitaxial layer 2 (η-type) of appropriate thickness is deposited. In the case shown, the p-well 6 is then generated with the corresponding channel stoppers. In the known manner, the n-channel transistor with drain 7, source 8 and p ^{+ well} terminal 9 and the p-channel transistor with drain 5, source 3 and n ⁺ substrate terminal 4 are then realized. The two drain areas 7 and 5 are not connected together and are routed to the exit 12. The gates of the two transistors are also connected together and led to the input 11. The two areas 8 and 9 are connected to ground 10 and the two areas 3 and 4 to the operating voltage 13.

In this arrangement of n- and p-MOS channel transistor now also a parasitic thyristor in the form of a vertical npn and a lateral pnp transistor is effective. FIG. 2 shows the simplified equivalent circuit diagram with these parasitic components. The npn vertical transistor 15 is formed of the regions 7 and 8 as the emitter, the p-well region 6 as the base, and the n-epitaxial layer 2 nvt as the n ⁺ substrate 1 as a collector. Between the base and emitter of this transistor, the resistor 17 is effective, resulting from the relatively high-impedance p-well region 6. The lateral pnp transistor 14 is formed of the regions 3 and 5 as emitter, of the n-epitaxial layer 2 as a base and of the p-well region 6 as a collector. Again, a resistor 16 between base and emitter formed of the n epitaxial layer 2 and the n ⁺ substrate 1 is effective. By means of the n.sup. ⁺ -Substrate 1, this resistance value can be greatly reduced, in particular if contacting near the component is not always possible. The coupling of these two transistors to the parasitic thyristor is shown in FIG.

If a "high" level is present at the input 11 of the CMOS inverter, the output 12 has the "low" level. The n-channel MOS transistor is conductive, the p-channel MOS transistor is blocked accordingly. If, for example, a negative overshoot occurs at the output 12, the n ^{+ region} 7 can inject and the parasitic thyristor switches on. ils flows a large current from the operating voltage terminal UDD13 to ground 10. do positive overshoot is reduced in this switching state by the n-channel conductive MOS transistor.

When the input has a "low" level, the "high" level will appear at the output. Thus, the n-channel MOS-Trans are blocked noise and the p-channel MOS transistor conductive. By a negative overshoot at the output 12 can again inject the n ^{+ region} 7 and turn on the parasitic thyristor, the amplitude but be relatively large

got to. In the positive overshoot of the signal amplitude can inject in this switching state, the p ^{+ region} 5, and the parasitic thyristor can also be turned on.

Also due to disturbances on the operating voltage line 13 can be caused by the parasitic capacitances an injection, which turns on the parasitic thyristor.

The conditions for turning on a thyristor are well known in the literature. Decisive are the current gain values of the npn and pnp transistors and the values of the resistors 16 and 17.

As a geometric measure for the switching on of the parasitic thyristor is often the n ⁺ -p ⁺ distance between the n ^{+ region} 7 and the ρ ^f - '. <ibiet 5 indicated.

From this he statements can be seen that in these illustrated CMOS circuitry, the switch-on of the parasit? f.ii Thyristors can only be shifted to higher voltages. The effect of a parasitic thyristor (Latchup E'tekt) generally to prevent is only possible by an oxide isolation of one of the two MOS transistors.

All of the measures listed in the prior art result in reducing the current gain values of the parasitic transistors and minimizing the track resistances. However, for large scale integrated circuits, the n ⁺ p ⁺ distance would be reduced, which contradicts the requirement for small current gain values. If the tubs pretensioned accordingly, so z. B. the p-well 6 with - (3 ... 5) volts, so the pn-junctions drain well has been charged too much, which can lead to small pan penetration depths to touch the space charge zones and thus undesirable space charge limited currents.

Object of the invention

The object of the invention is to provide an arrangement for reducing the latch-up effect (thyristor effect) in integrated CMOS circuits, so that it is possible to realize such circuits which achieve optimum electrical parameters which allow a high packing density even in these CMOS circuits and thus allow an economical production.

Explanation of the essence of the invention

The invention has for its object to provide an arrangement for reducing the latch-up effect in integrated CMOS circuits, which allows to minimize the η ^y -p ⁺ distance, without increasing the current gain values of the parasitic bipolar transistors, so that Even with Submicrommeterstrukturen the small distances for a high packing density can be fully exploited.

According to the invention, the charge for integrated CMOS circuits with pn isolation is achieved in that an additional guard ring is arranged at a corresponding distance around the respective well region and has the opposite conductivity type as the substrate or as the epitaxial layer. This additional protection ring can z. B. with the well diffusion and / or source-drain diffusion can be realized and thus have the corresponding penetration depths as these areas. For small structure widths it is z. B. advantageous to realize the additional guard ring in the form of a doped trench around the respective well area. The depth of this trench can z. B. smaller or larger than the corresponding Wanneneindringtiefe and depends on the required Latchup security. This additional guard ring is connected to ground or to an additional negative bias in a p-well technology. In an n-well technology, however, this protection ring is connected to the operating voltage or to an additional positive bias.

embodiment

The invention will be explained below cn an embodiment. In the accompanying drawings show

Figures 1 and 2: the prior art

3 shows the arrangement according to the invention with a p-well technology. FIG. 4 shows the equivalent circuit diagram according to FIG

5 shows the arrangement according to the invention with a doped trench

6 shows the arrangement according to the invention in an n-well technology for CMOS or BICMCS

According to FIG. 3, the p-well CMOS technology is based on an n ⁺ substrate 1. An epitaxial layer 2 (n "-type) is deposited on the n ⁺ -substrate 1. In this n.sup.- epitaxial layer, the p-well 6 and the additional p-type guard ring 18 are realized ⁺ -. generated and p ⁺ source and drain terminal regions 3,4,5,6,7,8,9 with the p ⁺ diffusion of the guard ring 18 may be doped up simultaneously so that the smallest possible path resistance is achieved The pVp guard ring 18 is arranged at a corresponding distance around the p-well 6 and in the simplest case is connected to ground 10. However, it is more favorable to connect this guard ring 18 to a negative bias.

The valid for this circuit arrangement equivalent circuit diagram is given in Figure 4. By inserting the guard ring 18 in addition, the transistors 21,22 and 23 are effective. The npn parasitic transistor is again effective with n ⁺ gobietone 7.8 (emitter), p-well 6 (base), and η-epitaxial layer 2 / n ⁺ substrate 1 (collector). The parasitic lateral pnp transistors are active as follows:

the pnp transistor 14 with the p ⁺ -regions 3 and 5 (emitter), n-epitaxial layer 2 (base) and p ⁺ / p-protection ring 18 (collector),

the pnp transistor 22 connected in series with the pnp transistor 14 with p'Vp protection ring 18 (emitter), n epitaxial layer 2 (base) and p-well 6 (collector)

and the pnp transistor 21 connected in parallel with transistors 14 and 22, with the p ⁺ -regions 3 and 5 (emitter), n · epitaxial layer 2 (base) and p-well 6 (collector).

In addition, a restricted junction field effect transistor 23 with guard ring 1U acts as a gate. The gate (p ⁺ / p guard ring 18) is reverse biased to the n epitaxial layer 2. The forming Raumladungszonan below the guard ring 18 lace the conductive channel in the n-epitaxial layer accordingly, so that the charge carriers must take the path on the low-resistance n ⁺ substrate 1. The injected minority carriers recombine more or less strongly. The indicated connection from the SFET 23 to the PNP transistor 21 is intended to characterize this described effect. The current amplification value of the pnp transistor 21 is thus influenced by the electrical properties of the SFET. The majority charge carriers, which can flow via the low-resistance n.sup. ⁺ Substrate 1, are symbolized by the resistor 20 in the equivalent circuit diagram.

The resistors 16 and 17 act as described. The resistor 16 is formed from the n-epitaxial layer 2 and the n ⁺ substrate 1, while the resistor 17 from the high-impedance p-well 6 results. In normal Betriebsfail is the operating voltage terminal 13, a positive operating voltage of z. B. +5 volts. The terminal 19 of the pVp guard ring 18 is also connected to ground 10 as well as source 8 and p-well 6 / well terminal 9. Between dome p ⁺ / p-protection 18 and the n-epitaxial layer 2, a space-charge zone is formed which is to reach into the n ⁺ -substrate 1. If, for example, holes from the p ^{+ region} 5 are injected into the n-epitaxial layer 2 due to an overshoot at the output 12, they are trapped by the protective ring 18 and grounded (19, 18 according to FIG. 4). On the other hand, a portion of the charge carriers passes through the n-epitaxial layer 2 in the n ⁺ substrate 1 and from there to the p-well 6 as a collector. Since, however, the n.sup. ⁺ Substrate 1 has a high concentration of charge carriers, the inflowing holes recombine there very quickly and only a very small fraction can reach the collector. The current gain of this pnp transistor 21 is thus very small and can be almost neglected in the case of an n-epitaxial layer on an n ⁺ substrate. Thus, the ignition condition (ß _npn · ß _pnp s 1) of the parasitic thyristor is reached in any case. Such an arrangement can thus be called latchup-safe.

The situation is somewhat different when only one n ~ substrate is used. The space charge zone between the guard ring 18 and the n ~ substrate is also effective here and extends some pm into the substrate. The injected holes from the p.sup. ⁺ Region 5, however, now pass in a larger number around this space charge zone to the p-well 6. The current amplification of this now acting pnp transistor 21 can no longer be neglected. Latchup security is only slightly increased in this case.

The advantage of the guard ring 18 but right comes locally right to the effect when working with an operating voltage of 3 volts. In this case, it is advantageous to connect the guard ring to a negative bias of 2 ... 3VoK. The trough penetration depth can be chosen to be relatively small because the trough is less loaded by the smaller operating voltage. But between the guard ring 18 and the n-epitaxial layer 2 is opposite to a nearly twice as high reverse voltage

Pan epitaxial layer, so that the space charge zone can expand into the n ⁺ substrate 1 and almost completely suppresses the transistor effect of the pnp transistor 21. Thus, small n ⁺ -p ⁺ distances and small pan penetration depths are permissible, and a high packing density is ensured.

The advantages of this circuit are only really for bar work Sibmicrometerbereich appreciated when the space requirement of the protective ring is crucial hardly because the n ⁺ -p ⁺ -Abst8nde would have to be made very large in order to secure the specified latch-up holding voltage.

Fig. 5 shows an arrangement with a doped trench 24 as a guard ring. An appropriate place of technological processes.-; is etched into the n-epitaxial layer 2 a trench (if possible RIE). Depending on the technology used, this trench has a depth of 2 ... 5mm. Subsequently, the trench is filled with p ⁺ -doped polysilicon and annealed, so that impurities from the p ⁺ polysilicon diffuse into the n-epitaxial layer 2. There, a p-doped region is then generated which, together with the p ⁺ -type polysilicon, takes over the function of the protective ring 18. The doped trench 24 may have a depth that is greater or less than the well penetration depth. Deeper trenches have the advantage that a smaller bias voltage can be selected in order to achieve that the space charge zone reaches into the n ⁺ substrate 1. For a high packing density, narrow and deep trenches are advantageous. This is especially true when only one n ~ substrate is used. Fig. 6 shows the Ar order of n ⁺ guard rings 27 for n-well CMOS and BICMOS Teclinology, respectively. According to FIG. 6, the starting material is a substate 1 (p-type) with an average doping. Below the p-channel MOS transistors and the bipolar transistors, a highly doped n-gobiet 26 is arranged. Above this is the epitaxial layer 2 (p ~ type). In this p ~ epitaxial layer, the n-well 25, the n ⁺ protection ring 27, the n ⁺ -source-drain regions 7, 8 and the p ⁺ -connection region 9 are realized. In the n-well 25, which projects into the n ^{+ region} 26, the p ⁺ source-drain regions 3, 5 and the n ⁺ -connection region 4 are arranged. The n ^{+ region} 26 also expands below the n ⁺ protection rings 27 in terms of area. When operating as a CMOS inverter, the operating voltage terminal 13 again has a positive operating voltage of +5 volts. Also on the n ⁺ protection ring 27 is located on the terminal 28 to this positive voltage. The substrate 1 with the epitaxial layer 2 are interconnected via the p ^{+ region} 9 with the mass 10. The n ⁺ source region 8 is also connected to ground 10. Between the guard ring 27 and the epitaxial layer 2 and between the n ^{+ region} 26 and the epitaxial layer 2, space charge zones are formed, which constrict the epitaxial layer in the adjacent region. If, for example, electrons are now injected from the n ^{+ region} 7, they are captured by the n ⁺ protective ring 27. The holes that could be injected from the p ⁺ regions 3 or 5 also do not work through the lateral pnp transistor effect because the p "epitaxial layer is pinched off. The pnp transistor, which crosses the n ^{+ region} 26 to substrate 1, but has such a small current gain that is incapable of firing the parasitic thyristor with the npn transistor current gain together., In highly doped rv region 26, most of the injected holes recombine.

In the case of a BICMOS circuit arrangement, it is furthermore advantageous to realize the supply of the operating voltage via the n ^{+ region} 26 and to short-circuit the p ⁺ and n * regions 3 and 4 only. In this case, the n-well 25 and the n ⁺ -region 26 are always biased more positively to the p ⁺ -regions 3 and 5 biased.

The n ⁺ protection ring 27 can be realized in this technology variant to realize its operation with the flat η ^ diffusion for the other n ⁺ areas, as the Breiton of the space charge zones, which form at the present voltages and concentration ratios, about 2 to 3pm. That is, with an epitaxial layer thickness of 3... 4 μm, the partial region of the epitaxial layer under the n ⁺ protective ring 27 is completely pinched off, if penetration depth of the η "'protective ring 27 and outdiffusion from the n ^{+ region} 26 are taken into account.

This means that in an n-well Techiiologie with n ⁺ -Schutzring and buried n ⁺ regions without trench small n ⁺ -p ⁺ spacings and high packing densities with a high latch-up security realized.

Claims (8)

1. An arrangement for reducing the latch-up effect in integrated CMOS circuits with pn insulation and well areas, characterized in that an additional guard ring (18; 27) is arranged at a distance around the respective pan and the opposite l.eitungstyp as that Substrate or as the epitaxial layer has. 2. Arrangement according to claim 1, characterized in that the additional guard ring (18; 27) has the same penetration depth as the corresponding WannengebieL. 3. Arrangement according to claim 1, characterized in that the additional guard ring (Ib; 27) has the same depth of penetration as the source and drain areas. 4. Arrangement according to claim 1, characterized in that the additional guard ring in the form of a doped! ι trench (24) is arranged around the respective tub area. 5. Arrangement according to claim 4, characterized in that the doped trench (24) has a depth which is greater than the Wanneneindringtiefe. 6. Arrangement according to claim 4, characterized in that the doped trench (24) has a depth which is smaller than the Wanneneindringtiefe. 7. Arrangement according to claims 1 to 6, characterized in that b.ii a p-well technology, the additional p-doped guard ring (18) is connected to ground (10) or to the most negative potential of the circuit arrangement. 8. Arrangement according to claims 1 to 6, characterized in that in an n-well technology, the additional n-doped guard ring (27) to the operating voltage UDD (13) or to the highest positive potential of the circuit is connected.