DD272945A1 - MULTICHIP MODULE FOR HIGH SWITCHING SPEEDS - Google Patents

MULTICHIP MODULE FOR HIGH SWITCHING SPEEDS Download PDF

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Publication number
DD272945A1
DD272945A1 DD88316621A DD31662188A DD272945A1 DD 272945 A1 DD272945 A1 DD 272945A1 DD 88316621 A DD88316621 A DD 88316621A DD 31662188 A DD31662188 A DD 31662188A DD 272945 A1 DD272945 A1 DD 272945A1
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DD
German Democratic Republic
Prior art keywords
bonding
conductor
signal
potential
chip
Prior art date
Application number
DD88316621A
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German (de)
Inventor
Guenter Turinsky
Original Assignee
Robotron Elektronik
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Publication date
Application filed by Robotron Elektronik filed Critical Robotron Elektronik
Priority to DD88316621A priority Critical patent/DD272945A1/en
Publication of DD272945A1 publication Critical patent/DD272945A1/en

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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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Abstract

Die Erfindung betrifft einen Multichipmodul fuer hohe Schaltgeschwindigkeiten, bei dem die elektrische Verbindung der Halbleiterchips durch Bondbruecken und vorbereitete Kontaktinseln erfolgt. Hierfuer sieht die Erfindung vor, dass die Traegerbondflaechen und die Chipbondflaechen an der Peripherie der Chips in einer solchen Reihenanordnung vorgesehen sind, dass jeder Signalleiterbondflaeche mindestens zu beiden Seiten benachbart eine Potentialleiterbondflaeche angeordnet ist, dass die Bonddraehte von den Chipbondflaechen zu den Traegerbondflaechen in jeder Reihe mit gleicher Loopform, gleicher Loophoehe ausgebildet und parallel gefuehrt sind, dass die Ankontaktierungspunkte der Bonddraehte auf den Chipbondflaechen und Traegerbondflaechen auf gleicher Linie angeordnet sind und dass die Traegerbondflaechen mit zum Rand der Traegerplatte fuehrenden Leiterzuegen in paralleler Anordnung verbunden sind. Fig. 2The invention relates to a multi-chip module for high switching speeds, in which the electrical connection of the semiconductor chips is carried out by bonding bridges and prepared contact islands. For this purpose, the invention provides that the Traegerbondflaechen and the Chipbondflaechen are provided on the periphery of the chips in such a series arrangement that each Signalleiterbondflaeche at least on both sides adjacent a Potentialleiterbondflaeche is arranged, that the Bonddraehte of the Chipbondflaechen to the Traegerbondflaechen in each row are formed the same loop shape, same Loophoehe and performed in parallel, that the Ankontaktierungspunkte the bond wires are arranged on the Chipbondflaechen and Traegerbondflaechen on the same line and that the Traegerbondflaechen are connected to leading to the edge of Traegerplatte Leiterzuegen in parallel arrangement. Fig. 2

Description

Hierzu 2 Seiten ZeichnungenFor this 2 pages drawings

Anwendungsgebiet der ErfindungField of application of the invention

Die Erfindung betrifft einen Verdrahtungsträger für die elektrische Verbindung von Halbleiterchips hoher Schaltgeschwindigkeit über Bonddrahtbrücken und vorbereitete Kontaktinseln. Solche Verdrdhtungsträger werden beispielsweise zur Aufnahme und Verdrahtung von hochintegrierten Logik- und Speicherschaltungen in Form von gehäuselosen Nacktchips benötigt, um die Packungsdichte, Verdrahtungsdichte und Zuverlässigkeit von elektronischen Geräten der Datenverarbeitung, Nachrichtentechnik und Mikrorechentechnik weiter zu erhöhen.The invention relates to a wiring support for the electrical connection of semiconductor chips of high switching speed via bonding wire bridges and prepared contact pads. Such amplification carriers are required, for example, for accommodating and wiring highly integrated logic and memory circuits in the form of caseless nude chips, in order to further increase the packing density, wiring density and reliability of electronic devices for data processing, telecommunications and microcomputer technology.

Charakteristik der bekannten technischen LotungenCharacteristic of the known technical soundings

Von der Herstellung kompakter Raugruppen mit hochintegrierten Halbleiterchips (HL-Chips) ist es bekannt, die Kontaktierung der HL-Chips mit dem Verdrahtungsträger über Bonddrähte von automatischen Drahtbondern ausführen zu lassen. Diese Art dor Kontaktierung ist wirtschaftlich und in gewissen Grenzen frei wählbar. Außerdem ist sie für alle bekannten Verdrahtungsträger in Leiterplattentechnik, Dick- und Dünnschichttechnik einsetzbar. Ein solcher Verdrahtungsträger mit hochpoligen Halbleiter hip& ist aus dem DD-WP 243144 bekannt. Bei dieser Lösung wiiü jedes Bordfenster des Haibleherchips mit dem dazugehörigen Bondfenster auf dem Verdrahtungsträger über einen Bonddraht elektrisch verbunden. Mit der Zunahme des Integrationsgrades steigt die Anzahl der anzuschließenden Bondinseln. Dieser Trend zwingt zum Einsatz von immer kleinor werdenden Bondflächen und dünnen Bonddrähten. So kommt es, daß heute Bonddrähte von 15pm bis 500pm Dicke verarbeitet werden müssen. Deshalb wird das Dickdrahtbonden (100pm...500pm) meistens mit Aluminiumdrähten ausgeführt. Dünndrahtbonder verarbeiten aufgrund der höheren Präzision und des notwendigen Drahthandlings fast ausschließlich Golddraht. Ein Hyoridbonder ist von seiner mechanischen Konstruktion sowie seiner elektronischen Auslegung, einschließlichFrom the production of compact Raugruppen with highly integrated semiconductor chips (HL chips), it is known to make the contacting of the HL chips to the wiring carrier via bonding wires of automatic wire bonders. This type of contacting is economical and within certain limits freely selectable. In addition, it can be used for all known wiring substrates in printed circuit board technology, thick and thin film technology. Such a wiring carrier with high-pole semiconductor hip & is known from DD-WP 243144. In this solution, each on-board window of the semiconductor chip is electrically connected to the associated bonding window on the wiring carrier via a bonding wire. As the degree of integration increases, the number of bond pads to be connected increases. This trend forces the use of ever smaller bonding surfaces and thin bonding wires. So it happens that today bond wires from 15pm to 500pm thickness must be processed. Therefore, thick wire bonding (100pm ... 500pm) is mostly done with aluminum wires. Thin wire bonder processes almost exclusively gold wire due to the higher precision and the necessary wire handling. A Hyoridbonder is inclusive of its mechanical design as well as its electronic design

Softwarteunterstützung, in der Lage, unterschiedliche Bondparameter zu akzeptieren. Die Software in Verbindung mit einem modernen Bilderkennungssystem erlaubt es, Bondparameter, wie Bondgewicht, Ultraschallenergie, Ultraschallzeit, Loophöhe, Loopform, au omatische Fokussierung bei unterschiedlichen Chipdicken und unterschiedlichen Oberflächenkontrasten, zu programmieren. Die Sondnadel kann in drei Dimensionen im Selbst-Lernverfahren frei programmiert werden. Aufgrund der Länge des Bonddrahtes, der Führung des Bonddrahtes im freien Raumund der willkürlichen Führung der Loiterzüge in den Verdrahtungsebenen des Verdrahtungsträgers ist diese Art der Herstellung einer Hybridschaltung für hochfrequente Schaltsignale nicht ausreichend. In allen bekannt gewordenen Schriften wurden HF-technische Gesichtspunkte bei der Realisierung d'-r Verdrahtung nicht beachtet. Einer Weiterverwendung der bekannten Herstellungstechnologie von Hybrid-IS bsi hochfrequenten Schaltungen stehen die Serieninduktivität, die Koppelkapazität und der unkontrollierte Wellenwiderstand entgegen. Moderne Schaltungen erfordern deshalb zur vollen Nutzung ihrer progressiven elektrischen Konnwerte eine verbesserte Bondtechnologie, die auch HF-Gesichtspunkte beachtet.Software support, able to accept different bond parameters. The software combined with a modern image recognition system allows to program bond parameters such as bond weight, ultrasound energy, ultrasound time, loop height, loop shape, automatic focusing with different chip thicknesses and different surface contrasts. The stylus can be freely programmed in three dimensions in the self-learning procedure. Due to the length of the bonding wire, the free wire routing of the bonding wire, and the arbitrary routing of the Loiter trains in the wiring planes of the wiring harness, this way of manufacturing a hybrid circuit for high frequency switching signals is not sufficient. In all known fonts RF-technical aspects were not considered in the realization d'r wiring. Further use of the known production technology of hybrid IS bsi high-frequency circuits are opposed by the series inductance, the coupling capacity and the uncontrolled characteristic impedance. Modern circuits, therefore, require an improved bonding technology, which also takes into account RF considerations, to the fullest use of their progressive electrical properties.

Aus der DE-OS 2104 057 ist eins elektrische Verbinderanordnung bekannt, bei der jeder Signalkontakt von Erdkontakten umgeben ist. Da in dieser Veröffentlichung lediglich auf eine Trennstelle eingegangen wird, ist eine Anleitung für die Bonddraht- und Leitungsführung und Bondstellenausbildung bei Multichipmodulen hoher Schaltgeschwindigkeit nicht zu entnehmen.From DE-OS 2104 057 an electrical connector assembly is known in which each signal contact is surrounded by earth contacts. Since only a separation point is dealt with in this publication, a guideline for the bonding wire and cable routing and bond formation in multi-chip modules with high switching speed can not be found.

Ziel dor ErfindungAim of the invention

Die Erfindung hat das Ziel, die HF-Eigenschaften der Leiterverbindungen bei einem Multichipmodul zu verbessern und eine kostengünstige Herstellung bei hoher Packungsdichte zu ermöglichen.The invention has the goal to improve the RF characteristics of the conductor connections in a multi-chip module and to enable cost-effective production with high packing density.

Darlegung des Wesens der ErfindungExplanation of the essence of the invention

Der Erfindung liegt die Aufgabe zugrunde, Störimpulse durch Übersprechen zu vermindern, den Wellenwiderstand bei den Verbindungsleitungen kontrollierbar zu gestalten und eine berechenbare Signalausbreitungsgeschwindigkeit zu schaffen. Erfindurigsgemäß wird die Aufgabe durch die im kennzeichnenden Teil der Patentansprüche angegebenen Merkmale gelöst. Das Wesen der Erfindung besteht in einer strengen Parallelführung aller Leitung&verbindungen und in der Abstimmung der elektrischen Kennwerte durch die gemischte Anwendung von Dünn- und Dickdrahtbonddrähten und Führung der Leiterzüge in vorbestimmten Verdrahtungskanälen.The invention has for its object to reduce glitches by crosstalk, to make the characteristic impedance controllable in the connecting lines and to provide a predictable signal propagation speed. According to the invention, the object is achieved by the features specified in the characterizing part of the patent claims. The essence of the invention consists in a strict parallel guidance of all line connections and in the coordination of the electrical characteristics by the mixed use of thin and thick wire bonding wires and guidance of the conductor tracks in predetermined wiring channels.

Ausführungsbeispielembodiment

Die Erfindung soll an einem Ausführungsbeispiel näher erläutert werden. In der Zeichnung zeigen:The invention will be explained in more detail using an exemplary embodiment. In the drawing show:

Fig. 1: einen Randabschnitt eines Multichipmoduls,1: an edge portion of a multi-chip module,

Fig. 2: eine Seitenansicht des Randabschnittes gemäß Fig. 1,2 is a side view of the edge portion of FIG. 1,

Fig. 3: einen Bereich zwischen zwei Halbleiterchips.3 shows a region between two semiconductor chips.

Der Randabschnitt in Fig. 1 zeigt eine Trägerplatte 1, auf der ein Chip 2 durch die Klebefläche 3 positioniert ist. Die Trägerplatte ist beispielsweise is Keramikträger mit mehrlagiger Dünnschichtverdrahtung ausgebildet. Das Chip 2 ist auf der Oberseite an der Peripherie mit einer Reihenanordnung von Chipbondflächen 4 versehen, auf denen in bekannter Weise ein Ende von Bonddrähten 5 befestigt werden kann. (Es sind zur Erhaltung der Übersichtlichkeit nur die äußeren Bonddrähte 5 gezeigt.) Zur Anordnung der anderen Enden der Bonddrähte 5 und zur elektrischen Verbindung des Chips 2 mit den Signal- und Stromversorgungsleitbahnen und/oder den Außenanschlüssen sind auf der Trägerplatte 1 gleichviel Trägerbondflächen 6 unmittelbar an der Chipkante ausgebildet. Die Trägerbondflächen 6 werden in üblicher Verbindungstechnik mit den Verdrahtungsebenen des Keramikträgers verbunden, so daß auf eine nähere Beschreibung verzichtet werden kann. Die Trägerbondflächen 6 können durch Leiterzüge 7 auch an Anschlüsse 8 geführt werden, die sich am Rand dor Trägerplatte 1 befinden. Für die Ausführung der Anschlüsse 8 gibt es mehrere Ausbildungsformen, vom der lediglich, da die Gestaltung nicht erfindungswesentlich ist, eine auf die Trägerplattenunterseite führende Anschlußklemme dargestellt ist. In der Seitenansicht gemäß Fig. 2 sind die Anschlüsse 8 deutlicher zu sehen. Die Anordnung für die Chipbondflächen 4 und Trägerbondflächen 6 kann ein-, zwei- oder mehrreihig sein. In der Zeichnung sind drei Reihen A, B, C dargestellt. Die Verdrahtung der Reihen A, B, C stellt das Wesen der Erfindung dar.The edge section in FIG. 1 shows a carrier plate 1, on which a chip 2 is positioned through the adhesive surface 3. The carrier plate is formed, for example, ceramic carrier with multilayer thin-film wiring. The chip 2 is provided on the upper side at the periphery with a series arrangement of chip bonding surfaces 4, on which one end of bonding wires 5 can be fixed in a known manner. (For the sake of clarity, only the outer bonding wires 5 are shown.) For the arrangement of the other ends of the bonding wires 5 and for the electrical connection of the chip 2 to the signal and power supply conductors and / or the outer terminals, the same number of carrier bonding surfaces 6 are directly on the carrier plate 1 formed on the chip edge. The carrier bonding surfaces 6 are connected in conventional connection technology with the wiring levels of the ceramic carrier, so that can be dispensed with a more detailed description. The carrier bonding surfaces 6 can also be guided by leads 7 to terminals 8, which are located on the edge dor carrier plate 1. For the execution of the terminals 8, there are several forms of training, of which only, since the design is not essential to the invention, a leading to the support plate bottom terminal is shown. In the side view of FIG. 2, the terminals 8 can be seen more clearly. The arrangement for the chip bonding surfaces 4 and carrier bonding surfaces 6 may be one, two or more rows. In the drawing, three rows A, B, C are shown. The wiring of the rows A, B, C represents the essence of the invention.

Zur Sicherung der gewünschten guten elektrischen Eigenschaften von Signalleitern sind diese links und rechts bei Vorwendung nur einer Reihe A benachbart von Potentialleitern umgeben.In order to secure the desired good electrical properties of signal conductors, these are surrounded on the left and on the right by only one row A adjacent to potential conductors.

Unter dem Begriff Potentialleiter sollen Masse- und alle anderen Spannungsversorgungsleitor vorstanden werden. Um Störstellen weitgehend auszuschließen, wird die strenge Parallelanordnung von Signal- und Potentialleitorn vom Halbleiterchip beginnend bis zu den Anschlüssen 8 bzw. bis zum nächsten Halbleiterchip beibehalten. Da sich die Loopform und Loophöhe beim automatischen Drahtbonden programmieren läßt, ist die gleichförmige räumliche Zuordnung von Signal- und Potentialleitern mit engen Toleranzen möglich. Unterstützt wird dieses Verfahren durch eine standardisierte Bondstellenanordnung auf dem Chip 2 und auf der Trägerplatte 1. Die Bondstellen sind somit abwechselnd mit statischem Potential (Masse, Spannung) bzw. mit den Potential des Signalleiters belegt.Under the term potential conductor mass and all other voltage supply to be overseer. In order largely to exclude impurities, the strict parallel arrangement of signal and Potentialleitorn from the semiconductor chip beginning to the terminals 8 and to the next semiconductor chip is maintained. Since the loop shape and loop height can be programmed in automatic wire bonding, the uniform spatial allocation of signal and potential conductors with narrow tolerances is possible. This method is supported by a standardized bonding point arrangement on the chip 2 and on the carrier plate 1. The bonding points are thus alternately occupied with static potential (ground, voltage) or with the potential of the signal conductor.

Bei ECL-Halbleiterchips kann es notwendig werden, daß zwischen zwei Potentialbonddrähten iwei Signalbonddrähte eingebettet sind. Die Fläche der Bondinseln ist der verwendeten Bonddrahtstärke angepaßt.For ECL semiconductor chips, it may be necessary for two signal bonding wires to be embedded between two potential bonding wires. The area of the bonding islands is adapted to the bond wire thickness used.

In qjnerWeiterentw.cklung ist vorgesehen, dnß für die Signalleiter dünne und für die Potentialleiter dicke Bonddrähte verwendet werden.In qjnerWeiterentw.cklung is provided thn the signal conductors thin and for the potential conductor thick bonding wires are used.

Bei einer hohen Packungsdichte und kleinem Ras'erabsland der Bondinseln ist zum Vermeiden von Kurzschlüssen zwischen benachbarten Bonddrähten eine Beabstandung dnrch einen Harzklebertropfen 9 vorgesehen. Die Bonddrähte können auch mit Isolation versehen sein.At a high packing density and small fringe erosion of the bonding pads, a spacing of a resin adhesive drop 9 is provided to avoid short circuits between adjacent bonding wires. The bonding wires can also be provided with insulation.

Da die Zeichnung die Reihen A, B, C zeigt, sind auch drei Harzklebertropfen 9 dargestellt, die auch raupenförmig ausgebildet werden können. Die Bonddrähte 5 werden in jeder Reihe A, B, C mit gleicher Loopform, gleicher Loophöhe ausgebildet und parallel geführt. Die Ankontaktierungspunkte der Bonddrähte 5 auf den Chipbondflächen 4 und Trägerbondflächen 6 werden auf gleicher Linie angeordnet, z. B. genau im Zentrum der Bondflächen. Auch die Leiterzüge 7, die von den Trägerbondflächc<i 5zu den Anschlüssen 8 verlaufen, werden konsequent in paralleler Anordnung geführt. Werden die Chipbondflächen 4 und die Trägerbondflächen 6 in drei Reihen A, B, C angeordnet, dann lassen sich Signalleiter mit hohen Frequenzen mit einem Kreis von Potentialbondflächen umgeben. So wurden in Fig. 1 in den Reihen B beispielsweise die vierten und sechsten Chipbondflächen 4 und Trägorbondflächen 6 von links voll schwarz gezeichnet, während alle anderen Flächen hell dargestellt sind. Das heißt, die vierten Bondflächen und die sechsten Bondflächen gehören zu einer Signalleiter-, die anderen Bondstellen zu einer Potentialleiterverbindung. Die in der Reihe B zwischen den Bondflächen der Signalleiter befindliche Bondfläche für einen Potentialleiter (helle Bondfläche) ist also quasi beiden Signalleiterflächen gemeinsam zugeordnet. , Wie bereits dargelegt wurde, können die Bonddrähte 5 für die Chipbondflächen 4 und Trägerbondflächen 6 mit unterschiedlichem Durchmesser ausgebildet werden. Deshalb ist es zweckmäßig, für die dickeren Bonddrähte 5 der Potentialleiter euch großflächigere Bondflächen vorzusehen. Die Geometrie dieser Bondflächen kann quadratisch, rechteckig oder auch U-förmig sein, wie es in Fig. 3 dargestellt ist. Fig. 3 zeigt einen Bereich zwischen den Chips 2, die sich an den Enden der Leiterzüge 7 befinden. In der Mitte des Bereiches befindet sich ein Redundanzleitersystem 10, das keine Verbindung zu den bisher genannten Leitungsverbindungen hat aber zur Verbindung zweier Chips 2 überbrückt werden muß. Dazu befinden sich zu beiden Seiten des Redundanzleitersystems 10 Verbindungsflächen 11 für Signalleiter und Verbindungsflächen 12 für Potentialleiter. Die Verbindungsflächen 12 sind U-förmig ausgebildet und umgeben die Verbindungsflächen 11 klammerartig. Fig. 3 macht deutlich, daß auch das Redundanzleitersystem durch parallel angeordnete Bonddrähte überbrückt wird. Die mit den Verbindungsflächen 11 über Vias verbundenen Signalleiter werden in den anderen Leiterzugebenen nahe von Potentialleitern angeordnet.Since the drawing shows the rows A, B, C, three resin adhesive drops 9 are shown, which can also be formed caterpillar. The bonding wires 5 are formed in each row A, B, C with the same loop shape, the same loop height and performed in parallel. The Ankontaktierungspunkte the bonding wires 5 on the chip bonding surfaces 4 and carrier bonding surfaces 6 are arranged on the same line, z. B. exactly in the center of the bonding surfaces. The conductor tracks 7, which extend from the carrier bonding surface to the terminals 8, are also consistently guided in a parallel arrangement. If the chip bonding surfaces 4 and the carrier bonding surfaces 6 are arranged in three rows A, B, C, then signal conductors with high frequencies can be surrounded by a circle of potential bonding surfaces. For example, in FIG. 1, in rows B, for example, the fourth and sixth die bonding surfaces 4 and support bonding surfaces 6 are drawn from the left fully black, while all other faces are bright. That is, the fourth bonding pads and the sixth bonding pads belong to one signal conductor, the other bonding pads to a potential conductor connection. The bonding surface for a potential conductor (light bonding surface) located in the row B between the bonding surfaces of the signal conductors is thus assigned to both signal conductor surfaces together. As has already been stated, the bonding wires 5 can be formed for the chip bonding surfaces 4 and support bonding surfaces 6 with different diameters. Therefore, it is expedient to provide you for the thicker bonding wires 5 of the potential conductor you larger area bonding surfaces. The geometry of these bonding surfaces may be square, rectangular or even U-shaped, as shown in Fig. 3. Fig. 3 shows a region between the chips 2, which are located at the ends of the conductor tracks 7. In the middle of the area is a redundancy ladder system 10, which has no connection to the previously mentioned line connections but must be bridged to connect two chips 2. For this purpose there are 10 connection surfaces 11 for signal conductors and connection surfaces 12 for potential conductors on both sides of the redundancy conductor system. The connecting surfaces 12 are U-shaped and surround the connecting surfaces 11 like a clamp. Fig. 3 makes it clear that the redundant conductor system is bridged by parallel bonding wires. The signal conductors connected to the connection surfaces 11 via vias are arranged in the other conductor allocations near potential conductors.

Claims (10)

1. Multichipmodul mit hochdichter Mehrebenenverdrahtungsstruktur, bei dem auf dor oberen Schichtebene Chipbondflächen aufweisende Halbleiterchips befestigt und Trägerbondflächen zur elektrischen Verbindung zwischen den Chipbondfiächen der Halbleiterchips und den an den Trägerbondflächen angeschlossenen Leitungsverbindungen für Signal- und Stromversorgungsleitbahnen und/oder Außenanschlüssen mittels Bonddrahtbrücken vorgesehen sind, dadurch gekennzeichnet, daß die Trägerbondflächen (6) und die Chipbondfiächen (4) an der Peripherie derChips (2) in einer solchen Reihenanordnung vorgesehen sind, daß jeder Signalleiterbondfläche mindestens zu beiden Seiten benachbart eine Potentialleiterbondfläche angeordnet ist, daß die Bonddrähte (5) von den Chipbondfiächen (4) zu den Trägerbondflächen (6) in jeder Reihe (A, B, C) mit gleicher Loopform, gleicher Loophöhe ausgebildet und parallel geführt sind, daß die Ankontaktierungspunkte der Bonddrähte (5) auf den Chipbondfiächen (4) und Trägerbondflächen (6) auf gleicher Linie angeordnet sind und daß die Trägerbondflächen (6) mit zum Rand der Trägerplatte (1) führenden Leiterzügen (7) in paralleler Anordnung verbunden sind.1. Multi-chip module with high-density multi-level wiring structure, in which on the upper layer layer chip bonding surfaces mounted semiconductor chips attached and carrier bonding surfaces for electrical connection between the Chipbondfiächen the semiconductor chips and connected to the Trägerbondflächen line connections for signal and Stromversorgungsleitbahnen and / or external connections are provided by bonding wire bridges, characterized in that the carrier bonding surfaces (6) and the chip bonding surfaces (4) are provided on the periphery of the chips (2) in such a series arrangement that each signal conductor bonding surface is arranged adjacent at least on both sides an potential conductor bonding surface such that the bonding wires (5) are separated from the chip bonding surfaces (5). 4) to the carrier bonding surfaces (6) in each row (A, B, C) are formed with the same loop shape, same loop height and are guided in parallel, that the Ankontaktierungspunkte the bonding wires (5) on the Chipbondfiäc hen (4) and Trägerbondflächen (6) are arranged on the same line and that the Trägerbondflächen (6) with the edge of the support plate (1) leading conductor tracks (7) are connected in a parallel arrangement. 2. Muitichipmodul nach Anspruch 1, dadurch gekennzeichnet, daß die Bonddrähte (5) der Potentialleiter dicker als die Bonddrähte (5) der Signalleiter sind.2. Muitichipmodul according to claim 1, characterized in that the bonding wires (5) of the potential conductor are thicker than the bonding wires (5) of the signal conductors. 3. Multichipmodul nach Anspruch 1, dadurch gekennzeichnet, daß die Chipbondfiächen (4) und/oder Trägerbondflächen (6) des Potentials großflächiger als die der Signalleiter ausgebildet sind.3. multi-chip module according to claim 1, characterized in that the Chipbondfiächen (4) and / or Trägerbondflächen (6) of the potential over a larger area than the signal conductors are formed. 4. Multichipmodul nach Anspruch 1 und 3, dadurch gekennzeichnet, daß die Verbindungsflächen (11) der Signalleiter mit U-förmigen Veroindungsflächen (12) der Potentialleiiar umgeben sind.4. Multichipmodul according to claim 1 and 3, characterized in that the connecting surfaces (11) of the signal conductor with U-shaped Veroindungsflächen (12) are surrounded by the Potentialleiiar. 5. Multichipmodul nach Anspruch 1, dadurch gekennzeichnet, daß zur Sicherung der Parallelführung die benachbarten Bonddrähte (5) mit einem Halterungsmittel beabstandet sind.5. multi-chip module according to claim 1, characterized in that for securing the parallel guide, the adjacent bonding wires (5) are spaced with a holding means. 6. Multichipmodul nach Anspruch 1 und 5, dadurch gekennzeichnet, daß als Halterungsmittel ein Harzklober vorgesehen ist.6. multi-chip module according to claim 1 and 5, characterized in that a Harzklober is provided as a holding means. 7. Multichipmodul nach Anspruch 1, dadurch gekennzeichnet, daß ein zwischen den Chips (2) befindliches Redundanzleitersystem (10) durch konsequente Parallelführung von Bonddrähten (5) überbrückt ist.7. Multichipmodul according to claim 1, characterized in that between the chips (2) located redundant conductor system (10) is bridged by consistent parallel guidance of bonding wires (5). 8. Multichipmodul nach Anspruch 1, dadurch gekennzeichnet, daß die Reihenanordnung aus drei Reihen (A, B, C) besteht.8. Multichipmodul according to claim 1, characterized in that the series arrangement consists of three rows (A, B, C). 9. Multichipmodul nach Anspruch 1 und 8, dadurch gekennzeichnet, daß jede Signalbondfläche von einem Kreis von Potentialbondflächen umgeben ist.9. multi-chip module according to claim 1 and 8, characterized in that each signal bonding surface is surrounded by a circle of potential bonding surfaces. 10. Multichipmodul nach Anspruch 1 bis 9, dadurch gekennzeichnet, daß die mit den Verbindungsflächen (11) über Vias verbundenen Signalleiterin den anderen Leiterzugebenen nahe von Potentialleitern angeordnet sind.10. Multichipmodul according to claim 1 to 9, characterized in that the connection with the surfaces (11) connected via vias signal conductor are arranged in the other Leiterzugebenen near potential conductors.
DD88316621A 1988-06-10 1988-06-10 MULTICHIP MODULE FOR HIGH SWITCHING SPEEDS DD272945A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004053987A1 (en) * 2002-12-10 2004-06-24 Koninklijke Philips Electronics N.V. High density package interconnect wire bond strip line and method therefor
EP1683196A2 (en) * 2003-10-27 2006-07-26 Freescale Semiconductor, Inc. Electromagnetic noise shielding in semiconductor packages using caged interconnect structures
EP1818984A2 (en) * 2001-09-28 2007-08-15 Freescale Semiconductors, Inc. Semiconductor chip with multiple rows of bond pads

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1818984A2 (en) * 2001-09-28 2007-08-15 Freescale Semiconductors, Inc. Semiconductor chip with multiple rows of bond pads
EP1818984A3 (en) * 2001-09-28 2007-10-03 Freescale Semiconductors, Inc. Semiconductor chip with multiple rows of bond pads
WO2004053987A1 (en) * 2002-12-10 2004-06-24 Koninklijke Philips Electronics N.V. High density package interconnect wire bond strip line and method therefor
EP1683196A2 (en) * 2003-10-27 2006-07-26 Freescale Semiconductor, Inc. Electromagnetic noise shielding in semiconductor packages using caged interconnect structures
EP1683196A4 (en) * 2003-10-27 2007-03-21 Freescale Semiconductor Inc Electromagnetic noise shielding in semiconductor packages using caged interconnect structures

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