DD269244A1

DD269244A1 - SECONDARY MEMORY ARRANGEMENT FOR INTELLIGENT CONTROLLER

Info

Publication number: DD269244A1
Application number: DD30977787A
Authority: DD
Inventors: Herbert Wagner; Peter Kindler
Original assignee: Zeiss Jena Veb Carl
Priority date: 1987-12-02
Filing date: 1987-12-02
Publication date: 1989-06-21

Abstract

Zweitorspeicheranordnung fuer intelligente Controller fuer Mehrprozessor- oder Mehrrechnersysteme mit Zweitorspeichern. Durch erfindungsgemaesse Verschaltung der in einem Rechner ohnehin vorhandenen Baugruppen wird eine Zweitorspeicheranordnung fuer intelligente Controller geschaffen, die ohne Arbiter arbeitet. Genutzt wird die Eigenschaft der Mikrorechner, dass sie waehrend der Programmbearbeitung in einen inaktiven Zustand gebracht werden koennen. Der Prozessor, bei dem diese Eigenschaft genutzt wird, arbeitet gleichzeitig als Arbiter. FigurTwo-port memory arrangement for intelligent controllers for multiprocessor or multi-computer systems with two-port memories. By interconnecting the present in a computer anyway assemblies a zweitorspeicheranordnung for intelligent controller is created, which works without arbiter. The property of the microcomputer is that they can be brought into an inactive state during program processing. The processor that uses this feature also works as an arbiter. figure

Description

It is advantageous if the signal INACTIVE is formed directly by the first processor by the control stage. According to the invention, this is done by the address signals (ADDRESS) and the control signals (CONTROL SIGNAL) from the input of the Zweitorspeichers (2) additionally lead to each another input of the control stage (3). This eliminates the wait for bus 2 to the status signal, the second bus is thus prioritized higher. The characteristic of the microcomputer is that it is used during program execution in an inactive state. Waiting state, DMA state can be brought. The processor using this feature is also the arbit ir for the dual port memory. The fact that the bus signals of the inactive processor can be switched high impedance eliminates the additional expense of Multiplexer for the address, data and control bus. Only the second processor only needs to have bus drivers running themselves

hochohmig schalten lassen, solange der Prozessor nicht zum Zweitorspeicher zugreift.can be switched to high impedance as long as the processor does not access the second-port memory.

embodiment

Die Erfindung soll anhand eines in der Zeichnung dargestellten Ausführungsbeispiels näher erläutert werden. Ein erster Prozessor (CPU) 1 ist über seine Daten-, Adressen- und Steuerbusleitung mit den Eingängen eines Zweitorspeichers 2 verbunden.The invention will be explained in more detail with reference to an embodiment shown in the drawing. A first processor (CPU) 1 is connected to the inputs of a two-port memory 2 via its data, address and control bus.

Die Daten-, Adreß- ur.d Steuerbelastung eines zweiten Prozessors (nicht dargestellt) führen über Bustreiber 4,5,6 ebenfalls an die Eingänge des Zweitorspeichers 2. Das Adressen- und das Steuersignal des Busses 2 führt an Eingänge einer Steuerstufe 3, ein Ausgangssignal der Steuerstufe 3 bildet das Signal INAKTIV, das an einen Eingang des ersten Prozessors 1 führt. An einem Ausgang des ersten Prozessors liegt ein Signal STATUS an, das mit einem Eingang der Steuerstufe 3 in Verbindung steht. Ein Ausgangssignal der Steuerstufe 3 ist mit je einem Eingang der Bustreiber 4, B, 6 verbunden.The data, address ur duty tax burden of a second processor (not shown) via bus driver 4,5,6 also to the inputs of the two-port memory 2. The address and the control signal of the bus 2 leads to inputs of a control stage 3, a Output signal of the control stage 3 forms the signal INACTIVE, which leads to an input of the first processor 1. At an output of the first processor is a signal STATUS, which is in communication with an input of the control stage 3. An output signal of the control stage 3 is connected to one input of the bus drivers 4, B, 6.

Solange kein Speicherzugriff über Bus 2 angefordert wird, kann die CPU 1 über Adreß-, Daten-und Steuerbus mit dem Speicher 2 zusammenarbeiten. Die Steuerstufe 3 empfängt das oder die Statussignale der CPU 1 und die Adreß- und Steuersignale von Bus 2. Sie schaltet die Bustreiber 4,5,6 von Bus 2 inaktiv, so daß dieser Bus die Speichersignale nicht beeinflussen kann. Kommt am Bus 2 eine Anforderung zum Zugriff zum Speicher 2, so erzeugt die Steuerstufe 3 ein Signal INAKTIV, das die CPU 1 in den inaktiven Zustand bringt. Das Statussignal der CPU 1 wird in der Steuerstufe 3 ausgewertet. Sobald die CPU den inaktiven Zustand über das Statussignal signalisiert, erzeugt die Steuerstufe 3 ein Signal 7, das die Bustreiber 4,6,6 für Adreß·, Daten- und Steuerbus von Bus 2 aktiv schaltet und der Speicherzugriff von Bus 2 zum Speicher 2 erfolgen kann. Nach Beendigung dieses Zugriffes schaltet die Steuerstufe 3 das Signal „inaktiv" wieder ab und die CPU 1 kann wieder zum Speicher 2 zugreifen. Da bei intelligenten Controllern die CPU des Controllers ihre Verarbeltungsaufträgo von einer übergeordneten zentralen Verarbeitungseinheit erhält, ist es oft möglich, daß sie auf Verarbeitungsaufträge wartet. Dann ist es sinnvoll, daß die CPU nur zum Speicher zugreift, wenn sie tatsächlich Verarbeitungsaufträge abzuarbeiten hat. Für diesen Fall wird die oben angegebe. ie Schaltung so modifiziert, daß die CPU 1 über ihren Adreß·, Steuer- und Datenbus die Steuerstufe 3 so beeinflussen kann, daß diese das Signal „INAKTIV bildet, wenn die CPU 1 keine Verarbeitungsaufträge mehr hat (gestrichelt dargestellt). Damit wird gesichert, daß der Zugriff über Bus 2 schneller erfolgen kann. Hierbei ist der Bus 2 höherpriorisiert.As long as no memory access via bus 2 is requested, the CPU 1 via address, data and control bus with the memory 2 can work together. The control stage 3 receives the status signal (s) of the CPU 1 and the address and control signals of bus 2. It turns the bus drivers 4, 5, 6 of bus 2 inactive, so that this bus can not influence the memory signals. If a request for access to the memory 2 occurs at the bus 2, the control stage 3 generates a signal INACTIVE, which brings the CPU 1 into the inactive state. The status signal of the CPU 1 is evaluated in the control stage 3. As soon as the CPU signals the inactive state via the status signal, the control stage 3 generates a signal 7 which activates bus drivers 4, 6, 6 for address, data and control bus of bus 2 and memory access from bus 2 to memory 2 can. Upon completion of this access, the control stage 3 deactivates the signal "inactive" again and the CPU 1 can again access the memory 2. Since in intelligent controllers the CPU of the controller receives its processing task from a higher-level central processing unit, it is often possible that it Then, it makes sense that the CPU only accesses the memory when it actually has to process processing jobs, in which case the above-mentioned circuit is modified so that the CPU 1 passes over its address, control and data bus the control stage 3 can influence it to make the signal "INACTIVE" if the CPU 1 no longer has any processing jobs (dashed line), thus ensuring that the access via bus 2 can take place more quickly.

Claims

1. A dual-port memory arrangement for intelligent controllers, consisting of two via separate bus systems connected to the two-port memory processors (CPU), existing in the bus lines of a bus system bus drivers and a Steuerkufe, characterized in that the address signals (ADDRESS) and did control signals (STEUE RSIGNALE ) of the bus (BUS 2), which is connected via driver stages (4,5,6) to the Zweitorspeicher (2), in addition to each lead an input of the control stage (3) and to a third input of the control stage (3) an output signal (STATUS) of the directly to the Zweitorspeicher (2) connected processor (1) is applied, an output signal (7) of the control stage (3) leads to all bus drivers (4,5,6) and a second output signal (INACTIVE) at an input of Processor (1) is present.

2. A dual-port memory arrangement for intelligent controllers, characterized in that the address signals (ADDRESS) and the control signals (CONTROL SIGNAL) from the input of the two-port memory (2) additionally lead to a respective further input of the control stage (3).

For this 1 page drawing

Field of application of the invention

Field of application of the invention are multiprocessor or multi-computer systems with two-port memories.

Characteristic of the known state of the art

In multiprocessor or multi-computer systems, two-port memories are increasingly being used. As a result, the data exchange between the processors or computers via a common memory area can be realized very quickly and without additional interface circuits. In particular, the Zweitorspekher is also used for intelligent peripheral controller (Operating Documentation workstation computer A71OC by VEB Robotron electronics Dresden in part operating documentation two-port memory robotron k2071 p. 1 to 22).

In the case of two-port memories, access to the memory is made by two different processors via two separate bus systems. A functional unit of the two-port memory, the arbiter, has the task of controlling the accesses of the processors to the memory so that there are no conflicts. The arbiter guarantees that even if the processors access the memory simultaneously, the accesses will be executed one after the other. In addition, the arbiter controls the drivers or multiplexers for the address, data and control bus of the memory so that only the address, data and control signals of the processor, which currently has the access right for the memory, are applied to the memory (EP 180467IPC G11C 8/00, US 4604683IPC G06F13 /

The circuit complexity for the arbiter and the required driver and multiplexer stages is for many applications in the. Ratio to the memory itself too high. This is especially true for intelligent controllers that are essential to realize on a printed circuit board. The cost of the memory control exceeds the cost of the actual memory significantly.

Object of the invention

The aim of the invention is to provide a circuit arrangement for a two-port memory, which can be realized with significantly less effort on components and thus on a smaller board area. This makes it possible to realize intelligent controllers with a larger range of functions on a printed circuit board.

Explanation of the essence of the invention

The invention has for its object to provide a Zweitorspeicheranordnung for intelligent controllers, which is realized without arbiter and essentially by exploiting already existing modules. The object is achieved by a two-port memory arrangement for intelligent controllers comprising two processors (CPU) connected to the two-port memory via separate bus systems, from bus drivers present in the bus lines of a bus system and from a control stage according to the invention in that the address signals (ADDRESS) and the control signals (CONTROL SIGNALS) of the bus (BUS 2), which is connected via driver stages (4,5,6) to the Zweitorspeicher (2), in addition to each lead an input of the control stage (3) and at a third input of the control stage (3) an output signal ( STATUS) of the directly to the Zweitorspeicher (2) connected processor (1) is applied, an output signal (7) of the control stage (3) leads to all bus drivers (4,5,6) and a second output signal (INACTIVE) at an input of the processor (1) is present. If no request is made via the bus provided with driver stages, the first processor can work directly with the two-port memory. When requested via bus 2, a signal INACTIVE is formed at the output of the control stage, which puts the first processor into the waiting state. The signal STATUS present at the output of this processor leads to the control stage, which then generates a signal which activates the bus drivers so that the second processor can cooperate with the two-port memory.