DD258885A1 - STORE-SAFE IMAGE SYNCHRONIZER SWITCHING - Google Patents

Abstract

With the circuit according to the invention, the frame sync pulse is separated from a sync signal mixture subject to errors and an exact, variable temporal position or length of the frame sync pulse in the line screen is enabled. According to the invention, an AND gate and an edge-controlled 2: 1 frequency divider are connected to the input, the output of which is connected to an edge-triggered circuit for generating signals of a variable length and position. The center of the generated signals is approximately half the time from the input signal edge in time. The output of this circuit is connected to the second input of the AND gate. To select the duration and the position of the frame synchronizing pulse, a pulse counter and a monoflop are connected to the AND gate whose output is connected to the reverse edge-controlled reset input of the pulse counter and the clock input of a flip-flop. The counter outputs are connected via a switch to the reset input of the flip-flop. Fig. 3

Description

For this 4 pages drawings

Field of application of the invention

The invention relates to a circuit arrangement for detecting and generating the image sync pulse from the composite sync signal with a possible change in its temporal position within the Bildauschastlücke. for the synchronization of the video signal for measurement purposes.

Characteristic of the known state of the art

A common method to recover the frame sync pulse from the sync signal, such as. The use of an RC low-pass filter as a pulse width discriminator is used, in order to achieve a voltage increase at the time of the frame synchronizing pulse (FIG The advantage of this circuit is that the image change pulse is not exactly in the line raster, another variant is to separate the image sync pulse from the sync sound signal area, the pre-neighbors ensure that the capacitor voltage always approximates the same initial value Ua and the picture change occurs at the same time. 2 is the application of a high pass whose time constant is chosen so that its output changes as the duty cycle changes as shown in Fig. 2. The advantage of this circuit over the low pass pulse width discriminator is that the image change pulse occurs exactly at the trailing edge of the first main pulse dt. A disadvantage is the low immunity to interference of this circuit over short glitches by their high-pass character. (Schröder: "Electrical Communications Engineering" B. Ill, p. 721 ff.)

Other circuits evaluate the sync signal on delay times between the line sync pulses or derive in different ways from the changed pulse intervals (DE-OS 3343455) or the changed duty cycle from the frame sync pulse (DE-OS 2903488). Disadvantage of these circuits is the high cost or in that the vertical sync pulse is not in the line grid.

Object of the invention

The aim of the invention is to separate the frame sync pulse from a faulty sync signal region and to allow an exact, variable temporal position or length of the frame sync pulse in the line screen.

Explanation of the essence of the invention

The object of the invention is to obtain a temporally variable frame pulse from a faulty synchronous signal mixture at a defined time during the blanking interval. According to the invention the object is achieved in that the input to an AND gate and an edge-controlled 2: 1 frequency divider is connected, the output of which is connected to a circuit for generating signals of selectable length and position upon arrival of a signal edge.

The center of the generated signals is approximately half the line time away from the input signal edge in time.

The output of the circuit for generating pulses of selectable length and location is at the second input of the AND gate

connected. ·

By applying a schmal time window as possible - signal of selectable length and position - during the time interval in which the Vortrabanten, the frame sync pulses or Nachtrabanten are expected, the insensitivity of the circuit to glitches is achieved.

To select the duration and the position of the frame sync pulse within the picture blanking interval, the count input of a pulse counter and an edge-triggered monoflop are connected to the output of the AND gate, the output of which is connected to the trailing edge-controlled reset input of the pulse counter and to the clock input of a flip-flop. To the outputs of the counter a switch is connected, which connects one of the counter inputs optionally with the reset input of the flip-flop. At the output of the Flipf lops then the frame sync pulses with an adjustable period of time. At a second input of the switch image sync pulses can be removed with a line duration and variable timing.

The circuit for generating signals of selectable length and position can be realized by two successive edge-triggered monoflops, wherein the first monoflop determines the beginning of the signal and the second one controlled by the trailing edge of the first monoflop monoflop the length of the signal. In a further variant, the output of a first monoflop whose holding time 2 is greater than half the time duration and the negated output of a second monoflop whose holding time is less than half the line duration with a leading at its output the desired signal length and position capable AND Link connected. Both monoflops are connected to each other on the input side.

embodiments

The invention will be further explained with reference to an embodiment. Show

3 shows a block diagram of a circuit arrangement according to the invention with parallel monoflops for time window formation; FIG. 4 shows an associated pulse diagram

5 shows a block diagram with successive monoflops for time-slot formation

For different applications, it is necessary to obtain an exact image change impulse from a disturbed synchronous signal mixture. The present circuit makes it possible to separate the frame sync pulse by setting a time window after the line sync pulses, from a sync pulse mixture subject to glitches, and to select its time duration within the frame blanking interval.

In the diagram (Figure 3) and in the timing diagram (Figure 4), the function of the circuit is shown, wherein the components are designed in positive logic.

The output state of the flip-flop 1, which is connected as a 2: 1 frequency divider, is changed by the synchronizing pulse mixture present in the input for each incoming line synchronizing pulse. Each HL jump of the negated output sets the two monoflops 2 and 3. The first monoflop 2 is set to a hold time 11 which is slightly greater than half the line duration> Th / 2.

The hold time 12 of the second monoflop 3 is smaller by a small amount than half the line duration, the output signal is applied to the negated output. The output signals of the flip-flop 1 and the two monoflops 2 and 3 are linked via an AND gate 4. This ensures that only an output signal appears when in the time range Tf = ti - t «2 within a line, the synchronous level is present. All glitches that are outside this time window do not produce an output signal.

In order to be able to select the time of the frame sync pulse within the picture blanking interval at intervals of one line duration in each case, a pulse counter 5 connected to the AND gate 4 was used. As a result, the position and the length of the image change pulse can be varied over six line spacings. These possibilities of change are limited by the number of pre-and post-alarms and the half-time pulses during the frame sync pulse. With a likewise connected to the AND gate third monoflop 6 ensures that the pulse counter 5 is reset only and prepared for a new counting cycle when the Haltezert Monoflops 6 has expired. Therefore, the frame sync pulse begins only after the time interval 13. The noise immunity of the circuit depends on how short the time window Tf can be selected. This depends on the time stability of the monoflops 2 and 3. The same function fulfills the circuit of FIG. 5. Here the position of the time window is determined by the hold time of the first monoflop 2 (ti <Th / 2) and its length is determined by the Hold time of the second monoflop 312 = tf determined. The advantage of this circuit is that the hold time of the monoflop 3 for the time window f starts only after the holding time of the first monoflop 2 has elapsed, and thereby becomes less sensitive to tolerances of the hold times.

Claims (3)

claims: 1. Störsichere Bildsynchronisierschaltung, characterized in that the input to an AND gate (4) and an edge-controlled 2: 1 frequency divider (1) is connected, the output of which is connected to a circuit for generating signals of selectable length and location upon arrival of a signal edge , wherein the center of the generated signals is approximately one half line time away from the input signal edge in time and that the output of the circuit is for. Generation of pulses of selectable length and position to the second input of the AND gate (4) is connected. 2. Störsichere Bildsynchronisierschaltung according to claim 1, characterized in that connected to the output of the AND gate (4), the count input of a pulse counter (5) and an edge-triggered monoflop (6) whose output with the trailing edge-controlled reset input of the pulse counter (5) and connected to the clock input of a flip-flop (7), that to the outputs of the counter (5) a changeover switch (8) is connected, each one of the counting outputs selectively connected to the reset input of the flip-flop (7), at its output (9 ) an image sync pulse with adjustable time is applied. 3. Störsichere Bildsynchronisierschaltung according to claim 1 and 2, characterized in that the changeover switch (8) has a second output (10), the image sync pulses with a time duration , and variable timing position.