DD250403A1 - SOS TYPE SEMICONDUCTOR ARRANGEMENT - Google Patents

Abstract

The invention relates to a semiconductor device of the SOS type and is intended for use in the field of semiconductor device fabrication. The object of the invention is to provide an SOS-type semiconductor device which has improved electrical and thermal conductivities, the production of which involves reduced costs for mechanical substrate preparation, and which offers good opportunities for the epitaxial arrangement of different semiconductors, even on the same substrate. The essence of the invention consists in an arrangement in which on a monocrystalline MgO carrier a thin, single-crystalline oxide intermediate layer with spinel or spinel-like structure and on this the epitaxial semiconductor layer is arranged. Possible fields of application of the invention are the integrated microelectronics, optoelectronics and acoustoelectronics.

Description

For this 1 page drawings

Field of application of the invention

The invention relates to a semiconductor device consisting of an insulating substrate and an epitaxial semiconductor layer. It is intended for use in the field of semiconductor device and electronic circuit fabrication. Such components and circuits can be used especially in integrated micro, acousto and optoelectronics.

Characteristic of the known technical solutions

It is known that integrated circuits of microelectronics arranged on an electrically insulating substrate theoretically have significant advantages over those arranged on a semiconducting substrate. Among these advantages are known: reduced parasitic capacitances, higher cut-off frequencies, higher switching speeds, lower energy consumption, the possibility of higher integration density, increased radiation resistance, the possibility of accommodating active and passive components on the same substrate. For the production of integrated circuits on insulating substrate so far semiconductor devices are used which consist of a monocrystalline substrate and an epitaxial Haibleiterschicht located thereon, z. A silicon layer, wherein the monocrystalline substrate consists of either a sapphire (Al ₂ O ₃ ) or a magnesium aluminate spinel (eg MgAl ₂ O ₄ or MgO · nAl ₂ O ₃ ). These arrangements are collectively referred to as silicon-on-sapphire (semiconductor-on-sapphire) arrangements.

The conventional SOS devices are characterized by a number of disadvantages, which have resulted in the fact that integrated circuit isolating circuits have so far found only very limited distribution. First, these disadvantages are that the electrical properties of the semiconductor layers are impaired by a high number of crystal lattice defects in the semiconductor layer and at the interface between the semiconductor layer and the substrate. In the case of SOS arrays, these defects are mainly due to the fact that the sapphire has a rhombohedral crystal lattice, while most of the materials used for the semiconductor layer have a cubic crystal lattice so that there is poor lattice matching at the interface. Another cause is reactions between the Al ₂ O ₃ and the semiconductor layer ("autodoping"). In the case of SOS arrangements on magnesium aluminate spinel, these defects are mainly due to the difficulty of mass producing large single crystals which have a sufficiently good homogeneity of the required chemical composition.

Secondly, there are disadvantages of the conventional SOS arrangements in the limited thermal conductivity of sapphire and magnesium aluminate spinel, which in itself is comparatively high in both cases, but for certain purposes, such as. B. for microwave components very high power, not sufficient.

Thirdly, because sapphire and magnesium-aluminate spinel are very hard materials that are currently used, the cost of mechanical machining necessary to prepare the substrates is very high. can only be worked with diamond tools. Fourth, the fact that the crystal lattice of the sapphire is of rhombohedral symmetry is unfavorable in that it is more difficult to arrange different semiconductor materials epitaxially on the same substrate with good layer quality than on a substrate with cubic symmetry of the crystal lattice. However, such arrangements of different semiconductor layers on the same substrate are likely to become very important in the future because they allow the fabrication of integrated circuits consisting of devices having electronic, optoelectronic and acoustoelectronic functions.

To eliminate the first-mentioned disadvantage, a semiconductor device has been proposed in which instead of magnesium aluminate spinel, a mixed crystal consisting of a proportion of magnesium aluminate spinel and a proportion

Magnesium titanate spinel or instead of sapphire a sapphire-like mixed crystal is used (J.Nishizawa and M. Kimura, DE-OS 2547931 and DE-OS 2534187). It is doubtful whether this proposal is feasible because it would be technically even more difficult to produce solid mixed crystals of the stated composition with sufficiently good homogeneity than in the case of magnesium aluminate spinel. In addition, the other disadvantages mentioned are not eliminated. A practical use of this proposal has not become known. Finally, there has been proposed an SOS type semiconductor device using a single crystal of beryllium oxide (BeO) as a substrate. Although this arrangement eliminates at least the second of the enumerated disadvantages, but is associated with the serious drawback of high toxicity of the BeO, in particular the dusts resulting from its processing. Furthermore, the production costs for BeO monocrystals should be very high.

Object of the invention

The aim of the invention is to provide an SOS-type semiconductor device having the following advantageous properties:

1. Improved electrical properties, eg. B. higher charge carrier mobilities, the semiconductor layer,

2. higher thermal conductivity of the substrate,

3. reduced costs for the mechanical processing necessary for substrate preparation,

4. the possibility of arranging different semiconductor materials (eg Si, GaAs, AIN) epitaxially with good layer quality on the same substrate.

Essence of the invention

The invention is based on the object

(1) to improve the density of crystal defects in the semiconductor layer and at the interface with the insulating substrate by improving the electrical characteristics of the semiconductor layer by using, in the semiconductor device, a substrate which is monocrystalline in the region adjacent to the interface with the semiconductor layer; thirdly, has a cubic crystal lattice, third, has sufficient chemical composition homogeneity, fourth, is less chemically reactive than sapphire,

2. to find a more thermally conductive starting material than sapphire or magnesium aluminate spinel,

3. find a softer starting material than sapphire or magnesium aluminate spinel and

4. indicate a substrate that provides good conditions for the epitaxial arrangement of different semiconductor materials with good layer quality by its cubic structure.

This object is achieved according to the invention by providing the following semiconductor arrangement: A thin, single-crystalline, oxidic intermediate layer with spinel structure or spinel-type structure is arranged on a monocrystalline magnesium oxide support and the epitaxial semiconductor layer is arranged thereon. The term spinel structure is known to denote a crystal lattice of space group Fd3m consisting of an approximately cubic face-centered anion sublattice and two cation sublattices formed by distinct, crystallographically uneven lattice sites, the number of lattice sites of a cation sublattice being twice as large .the grating patches of the other cations sublattice.

The arrangement according to the invention ensures a lower density of the crystal defects in the semiconductor layer and at the interface and thus improved electrical properties of the semiconductor layer, since carrier and intermediate layer are each monocrystalline first and secondly have a cubic crystal lattice, thirdly, the intermediate layer with adequate production sufficient homogeneity of the chemical Composition, in particular, if it is prepared by the method specified in DD-WP 0151771 and fourthly, the intermediate layer according to the invention eliminates the disadvantage of the relatively large chemical reactivity of the support material MgO occurring in the absence thereof, since materials with spinel structure are generally chemically less reactive in general.

Further, the support and intermediate layer substrate has a higher thermal conductivity than sapphire and magnesium aluminate spinel, and the thermal conductivity of the substrate is determined by that of the MgO support because the intermediate layer is thin. For the thermal conductivity λ, measured in W cm " ¹ K" ¹ applies, for example, at a temperature of 100 ⁰ C:

A (MgO) = 0.39; A (Al ₂ O ₃ ) = 0.28; A (MgAl ₂ O ₄ ) = 0.11.

Furthermore, due to its lower hardness, the MgO support is much easier to process mechanically than the conventional materials. Thus, for the Mohs hardness: H (MgO) = 5.5; H (Al ₂ O ₃ ) = 9; H (MgAl ₂ O ₄ ) = 8.

Moreover, owing to the cubic crystal symmetry of the intermediate layer and the carrier, improved possibilities for applying different epitaxial semiconductor layers on the same substrate are of particular importance, the additional possibility being the lattice mismatch between the semiconductor layer and the intermediate layer, and optionally also between the intermediate layer and the MgO support, determine by suitable choice of the chemical composition of the intermediate layer, which may be a chemical compound or a mixed crystal.

The intermediate layer may in particular contain the element magnesium; its thickness is typically less than about 1 μηι to choose.

In addition, the arrangement according to the invention satisfies the basic requirements imposed on SOS-type assemblies.

In particular, the condition required for the ratio of the thermal expansion coefficients a (MgO)> (intermediate layer)> a (semiconductor) can be satisfied. For example, ₂ Ti0 ₄ and intermediate layer, an epitaxial silicon layer is for a quantity of Mg at a temperature of 200 ⁰ C:

a (MgO) = 12.5 x 10 ^"6 K- ^ a (Mg ₂ TiO ₄₎ = 8.5 x 10" ⁶ K- ¹ Yes (Si) = 3.5 x 10 ^"6 K- ^1., see also the other requirements, such as the isojatory character of the substrate, thermal stability and optical transparency, are fulfilled.

1st embodiment

The following schematic arrangement shown schematically in FIG. 1 is given. On a single-crystalline MgO support whose surface is parallel to the (001) -crystal lattice plane, a 0.4 / jm thick single crystal Mg ₂ Ti0 ₄ layer and on this a 0.6 / xm thick epitaxial silicon layer is arranged so that the following crystallographic orientation relationships are fulfilled:

[100] _Mg

2nd embodiment

The following arrangement is given. On a monocrystalline MgO support whose surface is parallel to the (111) -crystal lattice plane, a Ο, δμ, ιη thick, single crystal Mg ₂ VO ₄ layer and on this a 1 micron thick epitaxial silicon layer is arranged so that the following kristaiiographic Orientation relationships are fulfilled:

(111) _Mg o! | (111) m _9i voJI (111) si

Iiji

3rd embodiment

The following arrangement, shown schematically in FIG. 2, is given. On a monocrystalline MgO support whose surface is parallel to the (001) -crystal lattice plane, is a 0.5μΓΠ thick, monocrystalline spinel layer of the mixed crystal Mg (Mg ₀ , 66Tio, 66Alo, 68) 04 and on this a 0,8μιτι thick semiconductor layer , partially made of Si or GaAs, arranged so that the following crystallographic orientation relationships are satisfied:

for the Si ranges (100) _MgO || (100) _z || (100) si

[ioo] _Mg0 || [ioo] ₂ || [ioo] _Si

undfürdie

GaAs areas (100) _Mg ol | (100) _z |] (100) _GaAs

Z here denotes the specified mixed crystal. The composition of the mixed crystal has been chosen so that the lattice mismatches Si / Z and GaAs / Z are equal in magnitude. The mixed crystal Mg (Mg _0i66 Ti ₀ , 66Alo, 68) 04 consists of 66 mol% of Mg ₂ TiO ₄ and 34 mol% of MgAl ₂ O ₄ . This composition corresponds to a lattice parameter of a _z = 0.3811 nm. Following the usual convention in the case of SOS arrangements of the above orientation relationship results.

a _S i = 0.5431 nm

aGaAs = 0.56531 nm a _z = 0.8311 nm

aMgO = 0.4213 nm the lattice mismatches too

3a _S i-2a ₂

Tsi / z = 2 · - = -0.02

3a _si + 2a _z

f - O ^Ga GaAs ^ia Z. _{n no}

TGaAs / Z = 2 * = + 0.02

f O az ~ ^ - aMgO r \ γ \ λ A

'Z / MgO - 2' - = -0.014

a _z + 2a _Mg o

Claims (5)

1. A semiconductor device of the SOS type, characterized in that on a single-crystal magnesium oxide support, a thin, single-crystal oxide layer with spinel or spinel-like structure and on this, the epitaxial semiconductor layer is arranged. 2. Arrangement according to item 1, characterized in that the oxidic layer consists of a chemical compound. 3. Arrangement according to item 1, characterized in that the oxidic layer consists of a mixed crystal. · 4. Arrangement according to item 1, characterized in that the oxidic layer contains the element magnesium. 5. Arrangement according to item 1, characterized in that the oxide layer has a thickness of at most 1 ^ m.