DD246860A1 - MICRORINE ARRANGEMENT WITH PROGRAM CONTROLLED INTERFACE CONNECTION - Google Patents

Abstract

The invention is applicable to microcomputers whose address bus has more lines than the data bus. The object of the invention is to increase the transmission rate in the operation of interfaces comprising relatively many information lines. It is solved the task of the interface connection in such a way that even with a larger number of information lines a direct program control with relatively high transfer rate is possible. The solution is to create a special state that allows certain commands to be interpreted differently from the usual execution. This makes it possible to switch the assignment of the address bus to the outgoing interface or to feed the occupancy of the incoming interface to the data bus. An automatic control unit is developed which acts on the interrupt control of the CPU and the memory access control on the basis of specific commands and controls the exchange of information between the interface and the address and data bus. Fig. 2

Description

For this 9 pages drawings

Field of application of the invention

The invention relates to a microcomputer arrangement with program-controlled interface connection, wherein the interface connection has more information lines in at least one transmission direction than the data bus of the microcomputer. Areas of application arise everywhere where correspondingly wide-ranging interfaces are to be controlled. An example is the connection of a control circuit for television viewing devices to a controlling microcomputer as part of a control and service processor for computer equipment.

Characteristic of the known technical solutions

Interfaces which have at most as many information lines as the data bus of the microcomputer for a transmission direction can be connected downstream of this data bus via coupling stages, via registers or via special E-A circuits. This is described in detail in textbooks (eg Kieser / Meder: Mikroprozessortechnik, Verlag Technik Berlini 982) and in the writings of the relevant manufacturers.

If the interfaces comprise more information lines, several registers or E-A circuits must be provided. In this case, the entire occupancy of the information lines in each case by multiple accesses to build or query, i. in sections according to the width of the data bus, e.g. B. in each case to one byte. Therefore, the transmission rate in the operation of such interfaces with microcomputers is significantly limited, so that they are no longer usable at higher requirements. The alternative switching means (sequential controls, microprogram control units, etc.) are relatively expensive.

Object of the invention

The aim of the invention is to significantly increase the transmission rate in the operation of interfaces which comprise a relatively large number of information lines, without fundamentally departing from the program control by a microcomputer.

Essence of the invention

The object of the invention is to form a microcomputer arrangement with interface connection so that even with a larger number of information lines a direct program control with a relatively high transmission rate is possible.

The deficiency of the known solutions are due to the fact that in conventional microcomputer arrangements, the occupancy of the interface lines can be set or queried only in sections (eg in individual bytes), so that for higher speed requirements the direct program control by special autonomously operating switching means must be replaced.

According to the invention the object is achieved by the cited in the claims circuits.

The effect of the circuit arrangement according to the invention is that, after a special state has been set by the program, some commands using the Funktionszuordners be interpreted differently than in the usual sense. Each command that is supposed to produce a special effect is preceded by a NOP command. During the transition from the NOP instruction to the following, the interrupt inputs of the CPU are disabled. The control line, which is arranged upstream of the permission inputs of the general memory decoding circuits, prevents accesses to the other memory means of the microcomputer during some control states. Further control signals cause the charge of the register with the assignment of the address bus or their provision on the outgoing leading interface lines or the successive connection of the coupling stages on the data bus.

embodiment

In the following embodiment show:

1 shows a conventional microcomputer arrangement with interface connection,

2 shows a microcomputer arrangement designed according to the invention,

3 shows the essential processes,

Figure 4; 5: details of the control circuits,

6: the state transitions,

Figure 7; 8: the command sequences,

Figure 9: the decoder circuit for the memories of the microcomputer.

Fig. 1 shows a conventional microcomputer arrangement of CPU 7, ROM, RAM and E-A circuits (PIO), are connected to the interface lines 5, 8. It is, for example, one of the widely used systems which have an 8-bit data bus 9 and a 16-bit address bus 6. Both outbound and inbound interfaces 5,8 have 16 each. Information lines connected to two 8-bit ports of an E-A circuit. Thus, two accesses are always required for setting or querying the interface assignment, such. For example, to output the command sequence LDA, LOW part OUT PIO 1 PORT B LDA, HI part OUTPIO 1 PORTA and to enter the command sequence IN-PIO 2 PORT B LD LOW part, A In PIO 2 PORT A LD HI part , A.

In this case, the LD instructions stand for transport operations of any desired type in order to retrieve or store the information currently required.

It can be seen that several machine instructions must be executed in the CPU for each interface assignment. Therefore, in the inventive design of the microcomputer assembly gem. 2, the outgoing leading interface lines 5 via an output register 1 the address bus 6 downstream, and the inbound leading interface lines 8 are formed via coupling stages 2,3, depending on the nature of the interface as a controllable driver circuits or registers with separately controllable "tri state" outputs The clock input of the output register 1 and the enable enable inputs of the coupling stages 2, 3 are arranged downstream of control circuits 4. If the concrete time conditions permit the interface, then the output register 1 can be omitted Interface lines are then connected directly to the address bus or via further coupling stages, and the corresponding line of the control circuits 4 serves as a validity line for the interface assignment, but these differences are meaningless for the further description.

The control circuits 4 are arranged downstream of the data bus 9 and access control lines of the CPU. They essentially include decoder circuits for selected machine instructions with downstream control flip-flops to which said turn-on permission and timing lines are connected. Furthermore, outputs of control flip-flops are connected in disjunctive connection to the enable inputs of the general memory access decoder circuits having the access control lines for the memory means of the microcomputer (ROM, RAM) connected in such a manner that all memory accesses will occur upon the onset of control (control flip flop active) be prevented.

The principle now is to use the control circuits 4 to interpret certain instructions differently, so that the register 1 wtrd loaded with the occupation of the address bus or the switching stages 2,3 are successively switched to the data bus.

For the first case, for example, the command LD (HL), A is used (transport of the byte in the register A to the memory cell whose address is contained in the register HL). The command is executed in two consecutive cycles:

1. reading the operation code (77 H in the example),

2. Write access, with the CPU occupying the address bus with the contents of the HL register and the data bus with the contents of the Α register.

The desired effect is achieved when the control circuits 4 trigger a load pulse for the register 1 in the second cycle, so that the address assignment (corresponding to the HL content) is transferred to the register 1. In addition, writing to the other memory means (RAM) of the microcomputer must be prevented.

For the second case, for example, the command LD HL, nm is used (loading the register L with the immediate value m and subsequently the register H with the immediate value n). The command is executed in three consecutive cycles:

1. Reading the operation code (in the example 21 H),.

2. reading the immediate value m from the next address and transport in register L,

3. Read the immediate value η from the next but one address and transport to register H.

The desired effect is achieved when the control circuits 4 switch the coupling stages 3 to the data bus in the second cycle and the coupling stages 2 in the third cycle.

It must be prevented that other memory means (namely the memory containing the command code) occupy the data bus. Thus, instead of the direct value (nm), the assignment of the interface is transported to the CPU.

3 shows the essential processes, combined for the first (a) and the second case (b).

The example CPU are i.a. following control lines downstream:

MREQ: general memory requirement

MI: access to read the opcode

RSFH: Refresh access for dynamic RAMs (always follows immediately on M1)

WR: write pulse

RD: read access

WAIT: Waiting state (line leads to CPU)

INT, NMI: Interrupt triggering (cables lead to the CPU).

Details of the control circuits 4 are shown in Figs. The arrangement generates gem. 4 shows a control pulse (CONTROL PULSE) whose leading edge becomes active before the end of the current cycle (see FIG. 3), so that the evaluation of the data bus occupancy can be controlled thereby. (For refresh cycles, no control pulse is delivered.) The circuit itself requires no particular explanation, since a pulse with the desired position of the leading edge can also be generated in another way (eg with a monostable multivibrator). In smaller microcomputer arrangements with uncritical time ratios u. U. also the trailing edge of MREQ be used directly as a control pulse.

Fig. 5 shows an embodiment of the decoding of the machine instructions together with the downstream Steuerflipflops, the

takes particular account of the practicalities of programming.

In this case, the data bus lines 9 together with the access control line for the instruction read (M 1) to a function allocator 15 (ROM) are connected to the two registers 16,17 are arranged downstream. The reset inputs of both registers 16, 17 are connected to an inverted operating work permit line 14 (SPECIAL ENABLE), which is connected downstream of further programmable means (not shown in detail) of the microcomputer (for example an E-A circuit). At the clock input of the first register 16, the control pulse line (CONTROL PULSE) acc. 4 and connected to the second register 17, the memory access control line (MREQ) of the CPU (the upstream conjunctive link is provided only for technical reasons of the exemplary CPU). Three outputs of the first register 16 are fed back to further inputs of the Fünktionszuordners 15. Another output is inverted to conjunctive junctions 20, 21, which are upstream of the interrupt inputs of the CPU (INT, NMI). The conjunctive links 20,21 are each with the corresponding interrupt trigger line. (INTERRUPT, NMI ACTION)

 The second register 17 are arranged in the following order:

A control line 18 (SPECIAL ACCESS) upstream of the permission inputs of the general memory access decoder circuits 19,

The switch-on authorization line 10 of the coupling stages 3 (ENABLE 3),

- those (11) of the coupling stages.2 (ENABLE 2),

- The clock pulse line 12 of the register 1 (REG 1 CLOCK).

Each of these lines is connected downstream of a conjunctive connection of the respective register output, namely, the first three are associated with the memory access control line MREQ of the CPU and the latter with the write pulse line (WR).

Essentially, the described arrangement is a control computer for analyzing the instruction stream of the CPU, which decodes certain instructions and provides the necessary control signals for these instructions.

Such a command execution sibling command decoding is known per se and z. B. in E-A circuits used to detect the interrupt return. Also, there are so-called coprocessor circuits that can perform certain operations faster than the actual CPU and take effect when their associated commands appear from the data bus. This is z. In the article by Agnew / Kellermann: "Microprocessor Implementation of Mainframe Processors by Means of Architecture Partitioning", IBM Journal of Research & Development / Vol. 26, No. 4, June 1982, pp. 401-411.

A similar control machine is also (for the purpose of expanding the address space) in the contribution sequence "Multimikrorechnersysteme", No. 10, in radio television electronics, Issue 1.1985, p.95 shown.

The function allocator acc. Fig. 5 contains the Coördierung of the subsequent state and the control information in parallel (Mealy-automaton).

In detail contain '

The bits 2-0 the coding of the following state (O... 7, that is to say, the automaton has 8 possible states),

Bit 3 the interruption prevention,

Bit 4 the suppression of other memory accesses during the special accesses to the interface,

The bits 5, 6 the switch-on permission for the coupling stages 3, 2,

- Bit 7 the write permission for the register 1

 Fig. 6 illustrates the state transitions

 The abbreviations not yet explained mean:

For example, a two-byte operation code instruction (both bytes are read one by one with successive M 1 accesses), SP = each of the operation codes used for the special accesses, NOP = NO-OP instruction (operation code OOH).

I -4- 246 880

The control circuits 4 have the following essential properties:

j 1. Disabling the mode permission line (SPECIAL ENABLE) will render it ineffective. This is how all commands work

j in the usual sense, and the interface is not addressed. Thus, the special effects can only be activated,

j if you really need them; Outside of the interface control, the microcomputer can be used in the usual way.

i 2. It is possible to control whether the special commands should have the special effect or not. This is essential because the particular

! appropriate instructions (eg, LD [HL], A, LD HL, nm) are also very useful for common programming and are often used

I will. General restrictions on use were the advantage of the arrangement according to the invention cancel

(longer runtime due to forced, complicated programming).

For this reason, the convention is introduced that every command which is to trigger one of the special effects described should be introduced

I 'command NOP is preceded. This affects the execution time. Not particularly, but allows both the permissive

  Use of all commands as well as the use of any suitable commands for the special functions. So next to! register HL also the other corresponding registers are used, it can direct values in the register 1

j, etc. It would also be possible to read a 16-bit word from the interface and hence the storage means of the

I microcomputer to address.

I 3. During the transition from the NOP instruction to the following instruction, all interrupt inputs of the CPU are disabled, so

I that the instruction sequence can not be interrupted (otherwise the arrangement would not be when interrupts occur

j functional).

j The individual states. Fig.6sind:

j 0: ground state, expecting the instruction to read (M 1), no special effects

j 1: Read the second opcode byte with appropriate commands (these have as first opcode only CP, DD, ED

or FD), no special effects

2: command NOP read, prevention of interruptions

i 3: Writing to register 1 with WR pulse (bit 7 = 1)

η 4r connecting coupling stages 3

j 5: connecting coupling stages 2

j 6: Get first immediate byte, no special effects'

ι 7: Get second direct value byte, no special effects.

  In states 3,4,5, bit 4 is active so that accesses to the other memory centers are prevented. The function allocator realizes the disjunctive linking of the states mentioned.

; For such a trained microcomputer z. B. the following additional commands are defined (such as

'Macro definitions in assembly language):

- OUTW (OUTPUT WORD) from BC, DE or HL (sequences from NOP, LD [BC], A etc.)

; OUTWI (OUTPUT WORD IMMEDIATE) as a result of NOP; LD (nm), A; nm is the direct value to be output

ι - INW (INPUT WORD after BC, DE or HL) (sequences from NOP, LD BC, nm etc.)

• -INWMPdNPUTWORDANDMAP)

i as a sequence NOP; LD A, (nm); with the read interface allocation the memory means of the microcomputer are addressed, and

! the read value is put into the Α register.

FIG. 7 illustrates the sequence of the output commands, FIG. 8 shows that of the input commands.

ι The special effects are to be triggered during the respective state. A state is gem. Fig. 5 before

! set to the end of a cycle. Thus, the allocator 15 is addressed again, so that at the beginning of the next cycle the

Tax information can be transferred to the second register 17. At the function allocator 15 are doing no

! particular time requirements. For faster microcomputers and the acquisition of tax information would be

j possible in parallel with the subsequent state. Since these may only come into effect in the following cycle, one would be

! Provide intermediate register for the bits 7-4 (wiring as the first register). Also, the generation of the

i control pulse gem. Fig.4 slightly modify so that the rising edge only effective immediately before the MREQ trailing edge

  becomes. Thus, the function allocator 15 can be constructed of conventional ROM or PLA circuits.

As can be seen from the state graph (FIG. 6) and the further explanations, the combinatorial equations for the

j function allocators can be assumed to be known (see, for example, Bochmann: "Automatengraphen",

  Akademie-Verlag Berlin 1982).

! Finally, FIG. 9 illustrates the connection of the control line 18 SPECIAL ACCESS to the general ones

i Memory access decoder circuits 19 of the microcomputer. This is inverted in conjunctive connection to one of the

; Permission inputs of the decoder circuit 19 connected, the permission lines for the individual storage means

I are connected downstream, so that during the special accesses with these storage means neither read nor write accesses

> be executed.

The inventive design of a microcomputer makes it possible for the operation of the interface connection faster

j, and thus significantly increase the data transmission rate. The additional expenses are

j low (less than 10 circuits, this is significantly less than a special sequential control of the interface connection

j requires).

  In particular, it is also advantageous that the outgoing interface lines are always fully energized in parallel (there is no "combining" of individual bytes), so that an output register (register 1) is only required if the

; Time conditions of the interface require the holding of the data. Otherwise, a direct connection to the address bus is sufficient

; (REG 1 CLOCK is then the current signal for the interface).

j An application is useful for all types of microprocessors whose address bus has more bit positions than the data bus (that is

^: in the widespread 8-bit types mostly the case) and which allow it (register structure, command list), full addresses

i store and process internally.

Claims (3)

A microcomputer arrangement with a program-controlled interface connection, wherein the interface connection has more information lines in at least one transmission direction than the data bus of the microcomputer, characterized in that • the outgoing leading interface lines (5) are connected downstream of the address bus (6) of the microcomputer, that the inbound leading interface lines (8) via several coupling stages (2,3) to the data bus (9) of the microcomputer are connected, that the Aufschaltlaubnisleitungen (10,11 ) of the coupling stages (2, 3) and the validity line (12) for the assignment of the outwardly leading interface lines (5) are connected to control circuits (4) which are connected downstream of the data bus (9) and the access control lines of the CPU (7) of the microcomputer, in that these control circuits (4) contain decoding circuits (15) for selected machine commands, which are followed by control flip-flops (16, 17) and the control flip-flops (16, 17) to which the said turn-on permission and validity lines (10, 11, 12) are connected downstream, in disjunctive link a common control line (18) is arranged downstream of the permission inputs of the general Speicherzugr Iffsdecodierschaltungen (19) of the microcomputer inverted in conjunctive with parts of said access control lines of the CPU is connected upstream. -1- 246 880 claims: 2. Arrangement according to claim!, Characterized in that the reset inputs of all Steuerflipflops (16,17) of the control circuits (4) with an inverted mode permission line (14) are connected, which is further programmable adjustable means of the microcomputer downstream. 3. Arrangement according to claim 1 and 2, characterized in that the control circuits (4) are formed so that the validity line (12) for the assignment of the outwardly leading interface lines is followed by a first Steuerflipflop in conjunctive connection with the write pulse line of the CPU of the microcomputer, in that the switch-on permission lines (11, 10) of the coupling stages (2, 3) are each followed by another control flip-flop in conjunctive connection with the memory access control line of the CPU, and in that an additional control flip-flop is connected downstream of the decoding circuits (15) for selected machine commands, inverted to conjunctive links (20, 21) connected upstream of the interrupt inputs of the CPU.