DD245068B1 - ARRANGEMENT FOR CHECKING WRITE STORES - Google Patents

Description

Field of application of the invention

The invention relates to an arrangement for testing read-write memories for proper operation. It finds application in electronic devices in which the safe operation depends on the correct functioning of the read-write memory, e.g. Control devices in which computers security-related functions are transmitted.

Characteristic of known technical solutions

There are numerous solutions for checking read-write memories regarding

- error of the read-write device,

- Error in addressing and

 - Failures and data corruption

known (Hölscher, Rader: microcomputer in security technology, Verlag TÜV Rheinland, Cologne 1984).

These can be divided into two groups:

1. Verification of the method of operation with the help of special test programs, which occupy the memory with a content that serves only as a test or calculates a checksum.

2. Double execution of read-write memory and comparison of contents.

The application of special test programs results in a considerable amount of time for the test, which is not acceptable for all applications.

In the dual execution of the read-write memory and checking by comparing the contents of the time problems are solvable. There are two possibilities:

1. Double read-write memory with hardware comparison. For this variant, an error-proof execution of the hardware comparison or its cyclic checking is required.

2. Double read-write memory with software comparison. Here, the program flow is heavily loaded by the necessary additional commands for the double storage of all data. This effort exceeds the effort required for the cyclical execution of the still necessary comparison program.

Object of the invention

The aim of the invention is to provide an arrangement for testing of read-write memories, which allows a review of the operation with little time and without heavy load on the program flow.

Explanation of the essence of the invention

The object of the invention is to provide an arrangement for testing of read-write memories on the principle of double read-write memory with software comparison, which takes over the test-compliant storage of the data and thereby relieves the program flow of additional commands for this task ,

The starting point was an arrangement with two memories, in which data are written both into the first memory and simultaneously inverted in the second memory. The reading of the data is done separately for both memories, whereby the data of the second memory appear inverted on the data bus.

The object is achieved according to the invention by addressing the second memory in memory writing with the same address as the first one, while reading memory, however, with an address attributed only to it. The arrangement takes over the inversion of all addresses directly connected to the second memory when writing, while reading this inversion does not take place. As a result, a maximum Hamming distance of the addresses for the two data values to be compared is given for the comparison process.

By including a high-quality addressing check, a significant increase in significance is achieved in the test of read-write memories.

The arrangement according to the invention for testing read-write memories is characterized in that low-order lines of an address bus are connected to the address inputs of the first memory and the inputs of an inverting driver and a non-inverting driver and higher-order lines of the address bus to the inputs of an address decoder the outputs of the drivers are connected via address lines to the address inputs of the second memory

Furthermore, control lines for memory access to the address decoder, control lines for writing and control lines for reading to the control logic and the control line for writing are additionally routed to the write inputs of the memories by a control bus.

An output of the address decoder is connected to the control logic via a control line, and a second control line connects another output of the address decoder to an input of the control logic and a block enable input of the first memory. The outputs of the control logic are connected via a control line to the output enable input of the non-inverting driver, via a control line to the output enable input of the inverting driver, and via a control line to the device enable input of the memory.

The found arrangement works as follows:

From the address bus, the number of low-order address lines corresponding to the memory capacity of the read-write memory is directly connected to the first memory, while these same lines lead to the second memory via one invertible and one non-inverting driver with three-state behavior via an output enable signal.

The remaining high-order address lines arrive with the memory access control signal to an address decoder, which thus provides each one of the first and second memory associated block enable signal. The block enable signal for the first memory is supplied directly to the latter and passes to the control logic with the block enable signal for the second memory and the control signals for write and read.

In the case of a memory write operation of the first memory, the control logic activates the inverting address driver, the second memory via its block enable input and the inverting bus driver. Thus, a data word written in the first memory is simultaneously inverted and written in the second memory at the inverted low-order address.

A read access to the second memory allows the control logic only under de by the assignment of the higher-order address lines predetermined specific address of the second memory. During read access to the second memory, the control logic activates the non-inverting drivers on the address and data sides. Thus, the maximum Hamming distance with respect to the data word content and its address is given for the subsequent comparison process.

embodiment

The solution according to the invention will be explained in more detail with reference to a possible embodiment in conjunction with the drawings.

In the accompanying drawing, the arrangement for testing read-write memories is shown. The arrangement consists of a first and a second memory 1,2, an inverting driver 5 and a non-inverting driver 6, an address decoder 7, a control logic 10, a non-inverting 4 and an inverting bus driver 3 and bus lines 11-15,24,25 and control lines 8,9,16-23.

The low-order lines 14 from the address bus 12 are connected to the address inputs of the first memory 1, the inputs of the non-inverting driver 6 and the inputs of the inverting driver 5. The outputs of the drivers 5,6 lead via address lines 24 to the address inputs of the second memory 2. The data terminals of the first memory 1 go directly to the data bus 11. The data lines 25 of the second memory 2 lead to the inputs of the non-inverting bus driver 4 and to the Outputs of the inverting bus driver 3. The outputs of the non-inverting bus driver 4 and the inputs of the inverting bus driver 3 are connected to the data bus 11. An output line 9 of the address decoder 7 leads to the control logic 10, while a second output line 8 of the address decoder 7 both the control logic 10 and the block enable input of the first Memory 1 is connected. To the logic 10 also lead the control lines for write 17 and read 18 from the control bus 13. The control line for writing 17 is connected to the write inputs of the first 1 and the second memory 2.

From the control logic 10, a control line 19 leads to the output enable input of the non-inverting driver 6, a control line 20 to the output enable input of the inverting driver 5, another control line 21 to

Block Enable input of the second memory 2, a control line 22 to the output enable input of the non-inverting bus driver 4 and a last control line 23 to the output enable input of the inverting bus driver 3rd

The data to be stored are written into the first memory 1 in the form present on the data bus 11 when the address bus 12 is assigned an address assigned to the first memory 1 with active memory access control lines 16 and write 17. At the same time, the control logic 10 activates via the control lines 20, 21 and 23 the inverting driver 5, the second memory 2 and the inverting bus driver 3. As a result, the data word written into the first memory 1 is simultaneously inverted and placed under the inverted low-order address in the second memory 2 inscribed.

The reading out of the data from the first memory 1 takes place on assignment of the address bus 12 with an address associated with the first memory 1 with active control lines for memory access 16 and read 18. Reading the data from the second memory 2 requires the assignment of the address bus 12 in the Form that the higher-order lines 15 are occupied by the address bus 12 to the base address of the second memory 2, whereas the low-order lines 14 of the address bus 12 have a relation to the write inverted assignment. The control logic 10 activates the non-inverting driver 6 on the address side and the noninverting bus driver 4 on the data side during the read operation of the second memory 2, which is identified by the active memory access memory 16 and read 18 and an assignment of the address bus 12 with an address assigned to the second memory 2 and the second memory 2 via the control lines 19, 22 and 21.

Claims (1)

Arrangement for testing read-write memories for correct operation on the basis of the duplication of the read-write memories with software comparison, wherein low-order lines of an address bus to the address inputs of a first memory and a data bus via data lines to the first memory and a second memory is coupled via data lines to the outputs of an inverting bus driver and the inputs of a non-inverting bus driver and the inputs of the inverting bus driver and the outputs of the non-inverting bus driver to the data bus and outputs of a control logic coupled via control lines to the output enable inputs of the bus drivers and the higher order part of Address bus are routed to an address decoder and applied to the address decoder, the control line for the memory access and the control line is performed for writing to the write inputs of the two memories and the output side control line of the Address decoder for the block enable signal of the first memory is applied directly to the first memory, characterized in that for inverting the address when writing the low-order part of the address bus (12) to an inverting driver (5) and to read on a non-inverting driver (6) and the outputs of which are connected to the second memory (2), in that the control logic (10) has a control line (19) for the output enable input of the non-inverting driver (6), a control line (20) for the output enable input of the inverting driver (5) and a control line (5). 21) lead to the block enable input of the second memory (2) and that the control line for writing (17) and the control line for reading (18) and the output side control lines (8,9) of the address decoder (7) for the block enable signals of the two memories (1, 2) abut the control logic (10). For this 1 page drawing