DD244853A1 - MIS TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF - Google Patents

Abstract

The invention finds application in the manufacture of polysilicon insulated high frequency field effect transistors. The aim of the invention is to produce MIS transistors with gate self-alignment for RF applications. The invention has for its object to provide a method which allows based on the silicon gate technology Selbstjustage the gate electrode on the lying between the source and drain channel region and at the same time a very low gate resistance can be realized without the use of novel materials against the standard silicon gate process is required. According to the invention, this object is achieved by a silicon gate method in which, after deposition of the polysilicon layer, an oxidation-masking layer is deposited, which is patterned together with the poly-silicon layer in the subsequent photolithographic process step, and an additional one after doping of the source-drain regions Siliciumaetzung is carried out, followed by an intensive thermal oxidation and prior to metallization, in which the Polysiliziumgate is contacted over a metal track in full length, the oxidation-masking layer is removed by means of grossflächchiger Überreetzung in selectively acting etching agent again.

Description

For this 2 pages drawings

Field of application of the invention

The invention finds application in the manufacture of polysilicon insulated high frequency field effect transistors.

Characteristic of the known technical solutions

Increasing the operating speed of MIS transistors requires, in addition to the shortening of their electrically effective channel length, a reduction of parasitic capacitances, in particular of the gate electrode.

It is known to reduce parasitic gate capacitance so-called self-adjustment technology, such. B. to use the silicon gate technology. The gate electrode itself serves as a doping mask in the generation of the source and drain regions and thus lies exactly above the transistor channel. As a result, the transistor channel is on the one hand safely covered and full control effect is ensured, on the other hand, the overlap capacitances to the source and drain are only relatively low due to the under-diffusion.

Subdiffusion can be minimized by using ion implantation for doping and keeping the subsequent temperature load low.

However, the use of polysilicon as a gate electrode has the disadvantage that the relatively high sheet resistance of the doped polysilicon does not permit longer gate paths for high-frequency transistors.

The sheet resistance of the polysilicon can be reduced by alloying a metal film (formation of metal silicide) so that, as described by Klaassen in Solid State Electronics, 23 (1980) 23, about 1 mm long gate paths for RF transistors are made possible by Mehrfachkontaktierung. Disadvantages of this technology variant are the larger deviations from the standard technologies and the higher complexity.

A low gate resistive self-aligning technology using refractory metals as a gate electrode has been proposed by Brown in Solid State Technol. 1-5 (1972) 33. Thereafter, RF transistors are also produced. The disadvantage here, however, is the low resistance of the gate metals in high-temperature processes, in particular their high oxidation rate.

Another self-alignment variant is the Self-Alignment Implant Technology described by Shannon in Philips Technical Review 31 (1970/71) 278, the aluminum gate acting as a dopant mask. Thereafter, however, only temperature loads below 570 ° C are possible in which the radiation damage from the implantation does not fully heal, whereby the device properties are adversely affected.

Object of the invention

It is an object of the invention to fabricate MIS transistors with gate self-alignment for RF applications.

Explanation of the essence of the invention

The invention has for its object to provide a method which allows based on the silicon gate technology Selbstjustage the gate electrode on the lying between the source and drain channel region and at the same time a very low gate resistance can be realized without the use of novel materials over the standard silicon gate process is required.

According to the invention, this object is achieved by a silicon gate method in which the deposition of the polysilicon for the gate, the deposition of an additional layer, for. As silicon nitride follows, which is structured in the subsequent photolithographic step together with the polysilicon layer, so that in the subsequent source-drain doping, which is preferably carried out by arsenic implantation, the double layer of polysilicon and silicon nitride acts as a dopant mask for the channel region.

According to the invention, the track width of the silicon gate track is so deliberately reduced after implantation by controlling an additional Siiiziumätzung that the finished device of the silicon gate only the channel to be controlled is covered and overlap capacities are very low.

By means of a photoresist mask, which covers an edge of the silicon gate, the additional silicon etch can be carried out so that the silicon gate is only laterally etched defined side, as it is favorable in DMOS transistors.

It is essential that the additional silicon etching step be followed by intensive oxidation in which the layer on the polysilicon acts as an oxidation barrier. The oxidation creates a thick oxide over the diffusion regions, and also anoxides the silicon gate laterally, which also serves to reduce gate capacitance.

According to the invention, the additional layer is removed by means of a large-area etching step in selectively acting etchant prior to the metallization, thereby exposing the silicon gate. It is essential that in the further metallization and structuring process over the silicon gate, a metal track is created, which causes the low gate resistance.

Owing to the thick oxide over the diffusion regions, overlapping capacities of the metal electrode are kept small, so that the requirements on the quality of the metal structuring are low from this point of view.

The doping of the polysilicon, which can be carried out at the same time as the deposition or in a doping step, also serves to reduce the gate-to-substrate resistance.

embodiment

The invention will be explained in more detail below using an exemplary embodiment. In the accompanying drawings, Figure 1 to Figure 7 show the schematic cross section of a DMOS transistor according to the invention in substantial processing stages.

On the surface of a semiconductor substrate 1 made of high-resistance p-silicon, a thermal oxide 2 of 75 nm is produced. From this oxide layer, a low-resistance phosphorous-doped poly-Si layer 3 of 300 nm thickness is deposited and on this again a about 200nm thick Si ₃ N ₄ layer 4 is deposited. (Figure 1) The diffusion regions are exposed by a photolithographic process, wherein the Si ₃ N ₄ layer 4 and the poly-Si layer 3 are etched in one step by means of plasma planar etching. (Figure 2)

By means of a known method (according to DD-WP 222731), the source and drain regions are now doped and later the simultaneous deep diffusion is carried out to produce a short channel. For this purpose, in a further photolithographic step, a resist mask 5 is produced on the silicon wafer, which has only openings above the source regions. In the subsequent boron implantation 6, the lacquer prevents the doping of the drain region (FIG. 3).

Subsequently, the resist mask 5 is removed and the arsenic doping 7 of the diffusion regions is performed (FIG. 4).

After the implantation of the two dopants 6 and 7, a further resist mask 8 is produced, which now only has openings over the drain regions. On the drain side, the poly-Si is now etched away so far (Si ₃ N ₄ is undercut) that a polysilicon web remains with minimum drift area overlap (FIG. 5).

The resist mask 8 is removed again, and the simultaneous depth diffusion of both dopants 6 and 7 follows, which is carried out in such a way that a penetration depth for the arsenic of about 2μ, ηη and for boron of about 3 μm is realized. During diffusion, the desired double doping profile arises from n ^{+ region} 10a and p region 11 on the source side, as well as the singly doped drain n ^{+ region} 10b. Thereafter, the production of a thick thermal oxide 9, the poly-Si gate 12 is embedded and simultaneously reduced further in its ridge width (Figure 6).

After the oxidation, the contact areas for the source and drain are exposed by means of photochemistry, and the Si ₃ N ₄ -SChIClIt removed by large over-etching, thus exposing the polysilicon gate.

Subsequently, the silicon wafer is vapor-deposited with Al and the connection electrodes for source 13, gate 14 and drain 15 are patterned. The Al-web is pulled over the entire length of the polysilicon electrode in order to reduce the track resistance as far as possible.

Claims (3)

Invention claim: 1. MIS transistor, consisting of a source and a drain region and a polysilicon existing gate electrode, characterized in that the gate electrode embedded in thick oxide, superficially oxide-free and is contacted by a metal strip over it full length low resistance. 2. A method for producing an MIS transistor according to item 1, based on the standard silicon gate technology, characterized in that after the deposition of the polysilicon layer an oxidation-masking layer is deposited, which is structured in the subsequent photolithographic process step together with the polysilicon layer that Furthermore, after the doping of the source-drain regions, an additional silicon etching is carried out, which follows an intensive thermal oxidation, and that prior to the metallization, in which the polysilicon gate is contacted over a metal track in full length, the oxidation-masking layer by means of extensive overetching in selectively acting etchant is removed again. 3. The method according to item 2, characterized in that the oxidation-masking layer consists of silicon nitride.