DD239927A3 - TWO-STEP APPLICATION METHOD FOR TREATING A DEEP III-B DEEP V-SEMICONDUCTOR COMPONENTS - Google Patents

Abstract

The invention relates to a two-step etching process for the wet-chemical surface treatment of light-emitting diodes isolated on carriers, preferably from the group of AIII-BV semiconductors. The aim of the invention is a two-step etching process for the removal of lattice defects as a result of mechanical separation processes and for defined surface roughening. According to the invention, the object is achieved in that first a polishing treatment in a solution of 10-70% by volume of phosphoric acid (85%), 5-30% by volume of hydrogen peroxide (30%) and 20-60% by volume of water followed by uniform structuring etching in a phosphoric acid (85%) / hydrogen peroxide (30%) or sulfuric acid (96%) / hydrogen peroxide (30%) solution in a volume ratio of 1: 1 to 1: 2.

Description

Field of application of the invention

The invention relates to a two-step etching process for the wet-chemical surface treatment of light-emitting diodes isolated on carriers, preferably from the group of A _m B _v semiconductors.

Characteristic of the known technical solutions

For a fully automatic assembly of semiconductor chips, it is common and economically particularly effective to further process the mechanically separated disks on a carrier. The carrier materials used are predominantly flexible organic polymers in the form of films having particular adhesion and spreading properties. The singulation of the semiconductor wafers usually takes place by combined scribing and breaking or more recently by a sawing treatment on a suitable carrier material, preferably the already mentioned carrier foil. After the mechanical treatment, it is necessary to eliminate the defective crystal area, in particular along the saw edges by subsequent treatment to ensure the effectiveness of the semiconductor devices. In particular, wet-chemical etching processes are suitable for this purpose, the following requirements being met by the etching system:

- The removal of the disturbed layers must be uniform in depth, polishing in a 50 μηη wide sawing trench. Usually 20 to 30 μπη are removed.

- By a roughening etching step Strahlstrahl- and long-term stability improvement of the semiconductor chips is sought.

- The etching solutions used must not interfere with existing metallization layers.

- The etching solutions used must not attack the substrates used, leave no etch residues that affect the bondability, and do not reduce the bond strength between the chips and the substrate.

Conventional etching solutions for A _m B _v semiconductors, in particular for GaAs, are, for example, systems based on H ₂ O ₂ and K ₃ Fe (CN) ₈ as an oxidizing constituent, as described, for example, in the patents (British Patent 1,334,717; GB-PS-1 401 114; US-PS-4 100 014; DE-OS-2 340 479; DE-OS-2 638 302; DE-OS 2 736 483; DE-OS 2 728 361; OS-2 730 853) are described. Also known is an inventive solution that seeks by a sequential addition of the components of the etching solution located on the sawing trench etching (DE-OS-2 730 953).

For rough etching etch solutions based on HF-HNO _{3 are also} known from the literature (US Pat. No. 4,094,752). These known etching solutions meet only partially the listed requirements. There is no known etching system that meets all the requirements cited. The crucial common shortcoming is that a continuous treatment of the individual chips on a carrier material is not possible, since under the required technological conditions with the known etching either either no reproducible removal of the faulty saw edges in a 50 μηη wide sawing trench is possible or not reproducible Roughening of the surface takes place or the carrier material is chemically attacked, as a result of which the adhesive strength of the chips is impaired and, moreover, the ability to wire-bond the chips and thus the exploiters of semiconductor components is reduced by the deposition of decomposition production on the metallization layers.

Object of the invention

The aim of the invention is a two-step etching process for eliminating lattice defects as a result of mechanical separation processes and for defined surface roughening. .

Explanation of the essence of the invention

The object of the invention is to develop a two-step etching method for isolated semiconductor chips on carrier material without chip transfer, wherein the crystal defects are removed in the first step and created in the second step by a defined geometric surface roughening conditions for a high emission and a low Degradationsneigung. The entire process must be carried out from separation to chip assembly on the same carrier material, the used carrier materials must not be attacked and the etching solutions used not impair the existing metallization layers. ^: -.

The object is achieved in that the etching solution in a two-step treatment first removes the disturbed grid areas at the edges of the mechanically separated, preferably sawn chips along the approximately 50 μιη wide sawing trench and then increased by a uniform defined roughening the surface of the semiconductor chips, the emission intensity and a lower degradation tendency is created.

The uniform removal of the faulty edge regions of the mechanically separated semiconductor chips takes place in such a way that with an H ₃ PO ₄ (85%) - H ₂ O ₂ (30%) - H ₂ O etching solution in a volume ratio of 5: 3: 3 to 10: 3: 3 the crystal defects that have arisen as a result of the mechanical separation are etched away.

These concentration ratios enable a uniform etching attack on the A _m B _v semiconductor substrate, especially in the saw trench, in particular for GaAs with an etching rate depending on the concentration ratios of the etching solution and the selected temperature in the range between 25 and 50 ⁰ C from 1 to 10 μηη / min.

To ensure a uniform etching attack in the saw trench, the carrier material with the isolated semiconductor chips can additionally be moved by ultrasonic excitation in the etching bath during the etching. After the polishing removal of the disturbed surface area, the first etching solution is removed and treated with H ₃ PO ₄ (SS ⁰ Zo) -H ₂ O ₂ (SO ₂ ) or H ₂ SO ₄ (96%) - H ₂ O ₂ (30 %) - solution etched in the volume ratio 1: 1 to 1: 2. Under these conditions, a roughening etch, which etches several μΓη deep Ätzstrukturen evenly into the semiconductor surface after 30 to 120 s and is the prerequisite for the desired reproducibility of the radiation intensity and the desired long-term stability of the semiconductor device. In this case, the carrier material used and the metallization layer are not attacked and the semiconductor chips do not detach from the carrier material. It is furthermore advantageous that the rough etching of the semiconductor surface makes the contrast between the semiconductor surface and metallization clearer and thus facilitates automatic bonding. The etching solutions used are chemically stable over a long period of time and, in contrast to etching solutions containing hydrofluoric acid in particular, pose no problem in terms of occupational safety.

embodiment

The process according to the invention will be explained in more detail below with reference to two examples:

1. The etched on a support film GaAs chips are in an etching solution of composition H ₃ PO ₄ (85%) - H ₂ O ₂ (30%) - H ₂ O = 7: 3: 3 parts by volume at 40 ⁰ C under the action etched by ultrasound for 3 minutes until about 25 μm of the defective layers of the semiconductor chip have been removed on both sides of the sawing trench.

After removal of the first etching solution, the rough etching of the surface to further improve the radiation power and the long-term stability of the semiconductor device with an etching solution of composition H ₃ PO ₄ (85%) - H ₂ O ₂ (30%) = 1: 1 by volume at 20 ⁰ C in 2 minutes in a static etching bath. In this case, about 2.5 μιη deep, uniformly distributed over the semiconductor surface etched structures are generated.

2. The removal of the disordered layers is carried out as in the embodiment 1.

After removal of the first etching solution, the rough etching of the semiconductor surface is carried out to further improve the radiation power and long-term stability with an etching solution of the composition H ₂ SO ₄ (96%) - H ₂ O ₂ (30%) = 1: 1 parts by volume at 25 ° C for min , In this case, about 2 μηη deep, uniformly distributed over the semiconductor surface etching structures are generated.

Claims (5)

Invention claim: 1. Two-step etching process for the treatment of AmBv semiconductor devices after mechanical separation by sawing, characterized in that first a polishing treatment in a solution of 10-70 vol .-% phosphoric acid (85%)
5-30 vol .-% hydrogen peroxide (30%) and
20-60% by volume of water followed by a uniform structuring etch in a phosphoric acid (85%) / hydrogen peroxide (30%) - or sulfuric acid (96%) / hydrogen peroxide (30%) - solution in a volume ratio of 1: 1 to 1: 2. 2. etching method according to item 1, characterized in that the volume ratio H ₃ PO ₄ : H ₂ O ₂ : H ₂ O in the first etching step preferably 5: 3: 3 to 10: 3: 3 corresponds. 3. etching process according to item 1 and 2, characterized in that the etching attack takes place predominantly in Sägegraben such that as components of the etching mixture diluted H ₃ PO ₄ - and H ₂ O ₂ solutions are used, wherein the diluted H ₃ PO ₄ - Solution is poured over the sawn semiconductor wafer and then the acid located outside of the sawing trench is removed. · 4. The method according to item 1 to 3, characterized in that the etching treatment is carried out on flexible organic substrates. 5. The method according to item 1 to 3, characterized in that the etching treatment is carried out on non-flexible organic or inorganic support materials.