DD218980A1 - CIRCUIT ARRANGEMENT FOR AD / DA IMPLEMENTATION - Google Patents

Abstract

The invention relates to a circuit arrangement for analog-to-digital conversion and / or digital-to-analog conversion, wherein in the case of analog-to-digital conversion in (n 1) clock phases from a reference voltage of the n-bit wide digital value of an analog input voltage or Case of digital-to-analog conversion in (n 2) clock phases, the analog voltage equivalent of an n-bit digital value can be derived. The proposed circuit arrangement uses the principle of charge distribution in switched capacitance networks and is designed using similar substructures, which accommodates implementation in integrated technology. The choice between unipolar and bipolar mode and the determination of the length of the conversion period, ie the number of bits, can be determined with the help of the switch control in a simple manner. The invention is applicable in the fields of news and data transmission, measurement, control and control technology and can be used in particular in the analog interface of microprocessor and microcomputer systems.

Description

Title of the Invention Circuitry for AD / DA conversion

Field of application of the invention

The invention relates to a circuit arrangement for analog-to-digital conversion and / or digital-to-analog conversion, wherein the principle of charge distribution in switched capacitance networks is used.

The invention is applicable in the fields of communications and data transmission, measurement, control and control technology and can be used in particular in the analog interface of microprocessor and computer systems. · '

Characteristic of the known technical solution

It is known to build AD / DA converters using switched capacity networks. In this case, the method of successive approximation is frequently used as the converter principle. Such an AD converter is described in the patent DE 29 42 940 A1. ;

Compared with other known solutions, the circuit arrangement specified there permits an AD conversion of η-bits in n iteration steps instead of n ^2/2 iteration steps. A disadvantage of this arrangement is that the Iteratipnsschritte are not identical to the drive signals of the switches, the clock phases, because each iteration step consists of four clock phases. ,

Object of the invention

The aim of the invention is to provide a new Schaltungsanord- 'tion such that the analog-to-digital conversion and at the same time the digital-to-analog conversion can be performed with a smaller number of clock phases and thus higher Umsetzungsgeschwind.igkeiten can be achieved, at the same time a simple switch control is enabled.

Explanation of the essence of the invention

The invention has for its object to provide a circuit arrangement by means of which an analog-to-digital conversion and at the same time a digital-to-analog conversion is made possible compared to known solutions with a smaller number of clock phases (=, iteration steps). gets along and thus a'here higher conversion speed and a simple switch control allowed.

According to the invention the object is achieved in that in a first iteration step, the voltages U1 (1) and U2 (1) can be adjusted. In this case, the voltage U1 corresponds to (1) the reference voltage U _R and the voltage U2 (1) of the analog input voltage Un, in the case of AD conversion or zero voltage value in the case of DA conversion, the two voltages are from a comparator compared and depending on the result of the comparison, the first bit X1 set and stored in a digital memory. In the DA implementation, this step is omitted.

At each successive iteration step, the reference value U1 (k) or zero is subtracted from the analog voltage U2 (.k,) depending on the bit value Xk. Thereafter, the reference value Ü1 (k) is halved and made available for the next iteration step. This process is repeated until the η-bit width. Value is determined or processed. In the (n + 1y-th) step at the AD conversion or in the (n + 2) th step during the DA conversion, the voltages U1 and U2 are reset and a new conversion cycle can be started 1, a circuit arrangement is proposed for carrying out this method, the principle of which is shown in FIGURE 2. The circuit is constructed around two basically similar analogue memory circuits AS1 and AS2: the reference voltage value U _R and the analogue input voltage U ™ or a charge equivalent to these values are picked up via the input networks Έ1 and E2 and applied to the inputs of the associated analogue

Transfer memory. Thereafter, the inputs U _R and Uy are separated from the circuit for the further conversion cycle. The voltages U1 (1 ) and U2 (1), which are equal to the reference voltage value U _D or the analog value of the input voltage U ₁ , are produced at the output of the memory. ^{R E}

In the case of DA conversion, the analog voltage U "is set equal to zero.

The preferably clock-synchronized comparator. K compares the signals present at its inputs voltage values UI (IJ and U2 (.1 ;, generates the first bit X1 and keeps it sleeps until the next clock. In the JJA conversion entfällt.dieser step. During each following iteration step, depending on the Bit evaluation XIc the reference value U1 (k) from the network KE2 and analog switch Tu transmitted to the input of the second analog memory so that at the output of the difference U2 (k.) - UHk) is formed, which in the subsequent step k + 1 as a new reference voltage is used on the comparator K. The second comparison voltage U1 (k + 1) is obtained by means of the coupling network KE1, which is located in the feedback of the first analog memory, by taking the voltage value U1 (k), dividing it by two, and adding it to the summing input Analog memory AS1 is switched on again.

In the (n + 1) -th step in the AD conversion or in the (n + 2) -th step in the DA conversion, the voltages U1 and U2 are preferably reset to zero by means of reset devices, and a new conversion process can be started become.

Embodiment .

The invention "will be explained in more detail with reference to an exemplary embodiment.

, in Figure 1, the flow chart of the method .in Figure 2, the basic circuit arrangement,. FIG. 3 shows a preferred basic circuit 'using switched capacitance networks according to the invention.

For the sake of clarity, the digital storage and control unit has not been shown in FIG.

The operation of the circuit arrangement in Figure 3 will be described below. It is assumed that - the initial charge on the capacitors C1 and Ü2 is zero. , '. .

In the first clock phase, switches S1, S2 and S1. S2 'closed, all other switches are open and thus the voltages U1 and U2 at the operating amplifier outputs are brought to the values U _R and U. Thereafter, the switches S1, S2 and S1 ',., S2' are opened and the switches S3, S4 and S3 ¹ , S, 4 'are closed for the further conversion process, whereby the signal processing unit is disconnected from the source sources U _R and Un and at the same time the capacitors C3, C3 'are discharged. In the case of the / DA conversion, the switch S1 'remains open in the first clock phase, whereby the desired initial state U2 (1) = 0 is maintained. -

This ¹ 'kind'der implementation requires the reset of the two voltages, UI and U2 in the last clock phase of the previous conversion period by means of the switches S11 and S11 ¹ , which correspond to the reset arrangements. The switches S1. to - S4 'and capacitor C3, correspond to the device E1 of Figure 2, while S1' to S4. ¹ and C3 ^{1 of} the device B2.

The switches S5 bi's S8 and the capacitors C4, C5. correspond to the device KE1 of Figure 2 and cause am'Ausgang the operational amplifier 1 each half of the signal value from the previous clock phase occurs. For this purpose, the capacitances G4 = C5 = 1/2 U1 are multiplexed. While one capacitor receives the charge from the op amp output, the other emits its precharged charge at the input in the same clock phase. This results in the simple control for the switches, it is done in pairs for S5, S8 and S6, .S7.

Basically similar is the arrangement and operation of the switches S5 'to S8 ^! and C4 ¹ , C5 ', which correspond to the device KE2 of Figure -2. This switch-capacitor network causes the! Bit value Xk controlled transmission of the voltage Ui (k) to the input of the second operational amplifier 2 and at the output of the necessary difference formation.

U2 (k + t> = U2 (k) - Xk.U1 (k) for where C4 '= C5' = U2.

This dependence of the signal transmission on the bit value Xk is achieved by the control signals for the. Switch 36 'and So ^{1 are} derived from the bit allocation.

After each iteration step, the bit value Xk is stored in the digital storage unit connected directly to the clock-phase-synchronized comparator K., preferably as a shift register, or provided by the shift register in the case of the DA converter

The switches S9, S10 and S9 ⁽ , S10 ¹⁾ serve to discharge the associated capacitors.

A to / oben- opposite sign of the voltage values at the two operational amplifier outputs, can be achieved in the first iteration step by appropriate switch control. For this purpose, during the reset phase of the preceding conversion period, the switches S1, S4 must be closed and S2, S3 opened, and in the first clock phase the drive signals at these switches appear negated. For the further conversion, the drive signals apply as described above. This feature of the specified circuit arrangement allows the bipolar operation of the AD / DA converter. , '· · ·' '.

The circuit is largely symmetrical and designed using similar substructures, which accommodates a realization in integrated technology .... , , , .

The choice between unipolar or bipolar mode of operation is just like determining the length of the conversion period, ie the number of bits, easily possible, and requires only a slight change of control or can be realized programmatically in microprocessor devices.

Claims (4)

, Claim for invention ,1. Circuit arrangement for AD / DA conversion nach.der iteration method, which in the case of analog-to-digital conversion in (n + 1) clock phases from a reference voltage U _R the η-bit wide digital value of an analog input voltage Ug or in the case of digital Analog conversion into (n + 2) clock phases which derive the analog voltage equivalent of an n-bit digital value, where , an analog voltage value U2 (k) is compared with a reference voltage value U1 (k), which in the • clock phase is equal to the reference voltage value U "and is formed in the following clock phases by dividing the reference voltage value of the previous clock phase by two, so that = ± U _{R U1 (k} ), ₌ in the case of the analog-to-digital conversion, the kth bit Xk has the logical value 1 if the current reference voltage value. U1 (k) is less than, the corresponding analog voltage value U2 (k), and has the value 0 if the reference voltage value UI (k) is greater than the analog voltage U2 (k), the kth bit in each case (k + 1) -th clock phase is provided and, * in the case of digital-to-analog conversion, the η-bit-wide input value is supplied bit-by-bit beginning with "the most significant bit (MSB) from the second clock phase, and the reference voltage value U1 (k) of the voltage value U2 (k), which corresponds to the analog input value U "in the first clock phase in the case of analog-to-digital conversion and equal to zero in the case of digital-to-analog conversion, depending on the Bit evaluation Xk subtracted, and thus the analog voltage value U2 (k + 1) is formed for the next clock phase: fu2 (k) - UKk), if Xk = V, - \ U2 (k) if Xk = 0, using analogue memory, comparator, container, digital storage and control unit, known per se, characterized in that two analog storage units (AS1; AS2) are connected to each other via an input device (.in; JSUJ) in addition to the reference voltage (U _R J or the analog input voltage (Up) can be charged and also have Rückselzanordnungen, the output side individually to the two inputs of a vor- preferably clock-synchronized comparator (K) are performed, the one O / 1- Forms a decision and transmits this as a corresponding bit value (Xk) to a digital storage and control unit (SSE), which stores this signal and at the same time as a control signal to an analog gate unit (TE) and provides the output of the first analog storage unit (AS1) via a coupling unit (KE1; KE2). is routed to the .Summiereingänge the two analog memory, wherein the one coupling unit (KE1) receives the output signal of the: analogue memory and in the next clock phase provides the halved value at the input of the same memory unit (AS1) in opposite phase position, and the other coupling unit (KE2) outputs the output signal of the first analogue memory (' ASi) in phase and via the analog gate unit (TE) depending on the result of the comparison in the comparator arrangement (K) to ^A the summing input of the second analog memory (ASi) transmits or does not transmit. . 2. A circuit arrangement for AD / DA conversion according to claim 1, characterized in that the analog memory (AS2; AS2) of capacitively feedback operational amplifiers and the input and coupling networks (E1; E2 and KE1; KE2) of switch capacitor networks consist. 3 · Coupling unit in a circuit arrangement for ν AD / DA conversion to point "1 and 2, which receives the output of a ~ Xna ± ogspeichers halved the signal value and in the next clock phase output again, characterized in that two similar switch capacitor Arrangements consisting of two series-connected analogue , ^: Switching and a capacitor connected from the common connection of the two switches to the reference point, are connected in parallel and the four switches of this arrangement are time-division multiplexed by the clock signal so that one capacitor picks up the output signal while the other reproduces the previously recorded signal outputs. , ' 4. Koppelei ^ neit for transmitting a signal in a ¹ circuit arrangement for AU / DA conversion according to claim 1 and 2, wherein the signal in the recorded one clock phase und'in the subsequent clock phase phase-rotated, and in response to a digital control signal and the clock signal is outputted again, characterized in that two similar switch-capacitor arrangements are connected in parallel, each consisting of two series-connected switches and a capacitor which 'is switched from the common terminal of the two analog switches to the reference point, the respective '·. because at the common terminal-.The parallel circuit ' ¹ and the series switches are multiplexed controlled by the clock signal, wherein the control signal of the located at the output of the parallel switch-capacitor arrangement switch pair is additionally logically AND linked with a condition statement. For this .3 ... pages drawings