DD212630A1 - ANALOG ACQUISITION SYSTEM - Google Patents

Abstract

The invention relates to an analog value detection system for use in data acquisition systems, in which a high processing speed and data resolution must be realized with temporal correlation of multiple measurement signals. The aim is to increase the scope of application with reduced realization costs. The object is to develop an analog value detection system in which the bandwidth of the number of channels is independent and which is constructed without filter and sample and hold circuits. According to the invention, the analog value detection system consists of n input units and a system controller. In this case, the n input units each contain two comparators, an analog memory, two switchable power sources, a channel control and a back-to-back counter. The system controller includes n tri-state buffers, a digital-to-analog converter, a dual-to-one-out-of-n decoder, a dual counter, and a prescaler.

Description

Title of the invention

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Field of application of the invention

The invention can be applied in Meßwerterfassungssysteinen, where a high processing speed and data resolution and a temporal correlation of multiple measurement signals must be realized.

Characteristic "of the known technical solutions

In automation systems with high demands on the transmission quality for computer-aided measurement data processing, the digitization of analog signals is becoming increasingly important. Economically, the digitization of several analog input signals takes place in a single functional unit. "

The most common arrangement today is serial systems consisting of analog multi- read and analog-to-digital converters. However, with a larger number of input signals, the possible bandwidth and thus the scope of application of such an analog value acquisition system is considerably restricted.

When using per se fast analog-to-digital converter also sample and hold circuits are required, the arrangement of increased system implementation costs as well as the necessary pilters with steep Cha

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Characteristics * Finally, it is hardly possible to use serial systems within control systems where high data quality and temporal correlation of multiple input signals is required.

Object of the invention

The aim of the invention is to provide an analogue value acquisition system whose scope of application is significantly expanded while at the same time having a lower realization cost.

Explanation of the essence of the invention

It is the object of the invention to develop an analog value acquisition system whose bandwidth does not depend on the number of channels and which is constructed without the use of a pilot as well as sample and hold circuits. The system is furthermore intended to ensure high data quality and temporal correlation of the measured values of the individual channels »

According to the invention, this object is achieved in that the one of the number η of the analog signals to be processed corresponding number of input units and a system controller and a R-Sit data bus existing analog value acquisition system has the following circuitry: The η input units are each composed of two comparators, an analog memory, built two switchable controllable power sources, a channel control and a gate-reverse payer. The system controller has a tri-state buffer, a digital-to-analog converter, a dual-to-one out-of-decoder, a dual counter, and a prescaler. "

The η Singangseinheiten are each connected as follows: An input of a Blomparators is connected to an analog input signal, while "the other input of the mentioned! Comparator is connected to an input of a second! Comparator and the output of the analog memory.

The second input of the second comparator is connected to the output signal of the digital-to-analog converter of the system controller.

The outputs of the two comparators, as well as a clock signal and control signal, are connected to inputs, the channel control «

At the input of the analog memory are the outputs of the two switchable controllable energy sources whose control inputs are connected to one output of the channel control. "Another output of the channel control leads to the input of the up-down counter whose outputs form the digital output of the respective input unit."

The system controller has the following interconnection: The digital outputs of the η input units are each connected to the inputs of the associated tri-state buffers whose outputs lead to the Ii-bit data bus to which the input of the digital-to-analog converter also leads. In this case, the staging inputs of the η tri-state buffers are connected to the output of the dual-to-1-out n-decoder, from which one of the control signals for the η input units is also removed. Its input is 8Ji the output of the dual counter connected, the input of which in turn leads to the output of the supplied with a clock Yorteilers, in addition to another control signal for. the η input units have been removed «

The particular arrangement of the analogue acquisition system according to the invention ensures high data quality and a lateral correlation of the measured values of the individual channels. The special part of the gate is that the bandwidth of the system according to the invention does not depend on the number of channels, the system is constructed without filter and sample and hold circuits and only has a common maturity

exemplary

In the following embodiment, the invention will be explained in more detail «. The accompanying drawings show in

Fig. 1: the block diagram of the analog value detection system according to the invention, in

2 shows the block diagram of an input unit, in FIG. 3 the block diagram of the system control and in FIG. 4 a detailed variant of an input unit.

According to FIG. 1, the analog value detection system consists of a number η input units EE .. to ES, which corresponds to the number of analog input signals to be processed> and a system controller SS, which is connected to an IT bit data bus B.

An arbitrary input unit 'SE consists of two comparators K .., Kp, two switchable controllable energy sources BQ ₁ , EQp, an analog memory A3, a channel control SIC and an up / down counter YRZ and is shown in FIG. 2 interconnected.

The system controller SS shown in FIG. 3 consists of ηIri-state buffers P ^ to P, a digital-to-analog converter DAU, a dual-to-one-out-of-n decoder D, a dual counter DZ and a prescaler Ϊ together and feeds the ^ -bit data bus 3.

According to FIG. 4, a more detailed variant for realizing an input unit EE has the following further components:

The analog memory AS is represented by a capacitor G. ^, two switches S ^, S ~, which are controlled by OR Gattem G ^, G ₂ form with a positive or negative voltage controlled current source SQ or "SQ and two capacitors C ,,, Cp the. Energy sources EQ ,, and EQp and become

of correction current sources KQ, KQ supplemented with switches S-, S ^. The effect of the arrangement described will be described at the beginning of the page.

In the comparator K., a comparison is made between the analog input signal U and the voltage U _n . at the condenser C ..

If U is greater than U ^ _Δ , the switch S- closes. for a time t. with t ^ * ¹ / 2fc. This gives the capacitor G.

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a charge that increases its voltage by one quantization unit. At the same time, the count in the front-to-back counter VRZ is increased by one.

If U is smaller than Ü _CÄ , the switch closes S ^ for a time t. and the voltage across the capacitor C becomes smaller by one quantization unit, which also entails a reduction of the count by one.

To balance the only short-term stable current sources SQ, SQ to compensate for the discharge of the capacitor C and to reduce the influence of the also only short-term stable time t .. must be made a cyclic comparison with a reference. For this purpose, the digital output DA., To DA _1n - of the front-to-back counter VRZ via the tri-state buffer Pu. and the H-bit data bus 3 connected to the digital-to-analog converter DAU, which functions as a digitally controllable reference. The cyclic polling is controlled by the prescaler T, which divides the clock signal f by the divisor K, the binary counter DZ for η bits and the dual-to-1-out-n decoder D, which supplies η channel selection signals CS '.

After a settling time ψ - t _? For the digital-to-analog converter DAU, the evaluation of the comparison in the comparator K ₂ between the output voltage of the digital-to-analog converter υ _πΛΤΤ and the voltage TJ _{n A} at the capacitor C takes place for a time tp with 1 / f = t _i + t ..

If U _{DAU is} greater than U _CA , the switch S ^ is closed for a time t ₂ * This gives the capacitor C _{) V} a

Amount of charge and its voltage IL-, ₄ is approximated to the output voltage Uj-JAg. At the same time, the switch S closes for a time t _? , whereby the charge on the capacitor C ₂ becomes smaller and the amount of current from the negative voltage controlled current source SQ also decreases.

If U ^- T) ATj is smaller than TL -, * > the capacitor voltage IL-,. », Is reduced via the switch Sp and via the switch S-there is a reduction of the current from the positive voltage-controlled current source SQ.

ir

To the over the voltage U _C o, U ^ controlled current sources SQ, SQ here the! Requirement is made that they slowly charge the capacitors C., C ~ via their input currents and thus slowly increase the amount of their output current »

On the other hand, the voltage-controlled current sources SQ discharge. SCL the capacitors CL, Cp. and thereby reduce their output current, so switches S ^ and S are to be swapped,

Claims (1)

Erfindungsansprucli Analog value acquisition system, consisting of a number of input units corresponding to the number η of the analog signals to be processed and a system controller and an I-bit data bus, characterized in that the η input units (ΕΞ * to EE) from each two comparators (K ₁ ; Kp) j an analog memory (AS), two switchable controllable energy sources (ECL; EQ ^), a channel control (SK) and a Yor reverse counter (YRZ), the system controller (SS) has η tri-state buffers (P) to P), a digital-to-analog converter (DAU), a dual-to-one-out-of-n decoder (D), a dual counter (DZ) and a divider (T), that the η input units ( EE .. to EE) each have the following interconnection: An input of a comparator (K.) is connected to an analog input signal (U ^), while the other input of this comparator (K-) is connected to an input of the second comparator (Kp) and the output of the analog memory (AS) and the second input of the second comparator (Kp) is applied to the output signal (U ^, -j) of the digital-to-analogue converter (DAU) of the system controller (SS), the outputs of the two comparators (K-; Kp) as well as a clock signal (f) and control signals (st) are connected to the inputs of the channel control (SK) and at the input of the analog memory (AS) are the outputs of the two switchable controllable power sources (EQ- j EQp) whose control inputs to an output of the channel control (SIC ) while another output of the channel controller (SK) leads to the input of the Yor-Reverse counter (YRZ) whose outputs (DA ^ _f to DA _V ) form the digital output of the respective input unit (EE ") ', and that further the system controller (SS) is interconnected as follows; The digital outputs (DA to DA _TTi ) of the η input units (ES- "to SS) sixld each to the inputs of the zui η connected tri-state buffer (P- to P) whose outputs lead to the H ™ "3 it data bus (B), in which also the i7, DE! * 1,882 O55774 Input of the digital-to-analog converter (DAU), v / o at the control inputs of the η Tri ^ · State buffer (P. to P) with the
Output of the buff-to-1-out-n decoder (D), at which one of the control signals (st) for the η input units (SE _) is connected, whose input is connected to the output
of the dual counter (DZ) is connected to the input
in turn, the output of the Yorteilers (T) fed with the clock signal (f) leads, from which also the second control signal (st) for the η input units (EE to EE) is removed » For this 3 pages drawing