DD211027A1 - CIRCUIT ARRANGEMENT FOR THE INITIAL SETTING OF FLIP FLOPS - Google Patents

Abstract

The invention relates to a circuit arrangement for the initial adjustment of flip-flops in integrated MOS technology. The object of the invention is to obtain a time-delayed switching by means of a voltage divider for obtaining a reset signal. According to the invention, an inverter with enhancement switching transistor and depletion load transistor is driven via a voltage divider, so that the voltage at the gate of the enhancement switching transistor is reduced at least by the amount of the enhancement threshold voltage of the enhancement transistor in the voltage divider with a time-dependent increase in the operating voltage. A controlled by the negator flip-flop causes a safe control of the voltage divider in case of operation.

Description

Circuit arrangement for initial adjustment of flip-plops Field of the invention

The invention relates to digital MOS circuits with enhancement and depletion transistors, in which a reset signal is required to generate a ground state of the flip-flops after the operating voltage has been switched on.

Characteristic of the known technical solutions

The known reset circuits include a flip-flop, which is forced laterally when switching the operating voltage in a preferred position to get out of this time delay a reset signal for other flip-flops ·

In DD-WP 108 160, the time delay is realized by charging an RC element. The lack of this solution is that in addition to the presence of capacitances of the charging resistor is usually realized by an enhancement transistor, so that when switching off the operating voltage of the capacitor is charged up to the enhancement threshold voltage. This prevents a renewed reset of the flip-flop u · U ·, so that additional circuit measures must be taken to completely discharge the capacitor.

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In the DD-WP 14-3 194- a solution is described which additionally uses a negator with an auxiliary voltage source - here another capacitor. The disadvantage here is that this circuit does not work at any increases in the operating voltage.

Object of the invention

The object of the invention is to develop a circuit arrangement for the initial adjustment of flip-flops, which has a high reliability independent of the rising edge of the operating voltage. Furthermore, when the operating voltage is switched off, all gate capacitances are to be discharged in order to ensure an immediate readiness of the circuit arrangement.

Explanation of the essence of the invention

The invention has for its object to provide a circuit arrangement for the initial setting of flip-flops, in which a reset ζ signal after switching on the operating voltage by means of a voltage divider time-delayed off »

Features of the invention

The inventive circuit arrangement for the initial adjustment of flip-flops in integrated MOS technology comprises a voltage divider, which consists of an enhancement transistor and a depletion transistor. The enhancement transistor is connected to the operating voltage and the depletion transistor to ground. The output of the voltage divider is connected to the gate of the enhancement switching transistor of an inverter.

The output of the inverter performs the Bücksetzsignal. Furthermore, the gate of the enhancement transistor in the voltage divider with operating voltage and the gate of the depletion transistor is connected to ground. In an embodiment of the invention, the output of the inverter is connected to the first input of a flip-flop. The first output of the flip-flop is connected to the gate of the depletion transistor and the second output to the enhancement transistor in the voltage divider · J

The operation of the circuit arrangement is the following: In a - not short-term in normal operation - |. Increase of the operating voltage - arises in the node of the voltage divider a reduced voltage which is smaller by at least the amount of the enhancement threshold voltage. This reduced voltage causes the gate of the enhancement switching transistor in the inverter to be delayed. The enhancement switching transistor will thus become conductive later. Since the instantaneous operating voltage is already present at the inverter, the potential of the output from the inverter rises to "high" via the load transistor of the inverter. Upon reaching a certain operating voltage, the output voltage of the voltage divider reaches a value at which the inverter turns on and pulls the potential of its output to "low".

This results in a Bücksetzimpuls at the output of the inverter.

If the circuit is extended by the described flip-flop, the reset signal sets the flip-flop in the appropriate position, whereby the voltage divider is completely turned on.

When short-term switching off the operating voltage are voirbeilhafterweise all nodes and the gate of the enhancement-switching ttransistors in the negator, whereby even when fast reconnection of the circuit an immediate

Operational readiness is reached · The circuit arrangement thus functions independently of the rising edge of the operating voltage.

embodiment

The invention is explained in more detail in two exemplary embodiments and with reference to two drawings. In the drawings: Pig 1: the first embodiment

Fig. 2 χ the second embodiment _.

The exemplary embodiment illustrated in FIG. 1 consists of a voltage divider 1 and an inverter 2. The voltage divider 1 consists of an enhancement transistor 3 connected to the operating voltage .sub.1 and a depletion transistor 4-connected to ground. The gate of the enhancement transistor 3 is likewise connected to the operating voltage U.sub.1 and the gate of the depletion transistor connected to ground.

The output A 1 of the voltage divider 1 is connected to the gate of an enhancement switching transistor 5 in the inverter 2, which also contains a depletion load transistor 6. The output A _{2 of} the inverter 2 then carries the reset signal K, which is not shown in circuit parts is further processed.

The embodiment shown in FIG. 2 is extended by a flip-flop 7. The first input E 1 of the flip-flop 7 is connected to the output A _2. It is also possible to apply the conditioned reset signal to the input E 1 of the flip-flop. In contrast to the first embodiment, the gates of the enhancement transistor are in this case 3 connected to the output Q ₂ and the depletion transistor 4 to the output Q ^

Claims (3)

invention claim 1 · Circuit arrangement for the initial adjustment of flip-flops in integrated MOS technology, characterized in that a voltage divider (1), the enhancement transistor (3) with operating voltage (TQ and its depletion transistor (4) is connected to ground, with its output (A ^ ) is connected to the enhancement switching transistor (5) of an inverter (2), the output (Ag) of the inverter (2) being connected to the following circuits 2. Circuit arrangement according to item 1, characterized in that the gate of the enhancement transistor (3) is connected to the operating voltage (£) and the gate of the depletion transistor (4) is connected to ground. Circuit arrangement according to item 1, characterized in that the output (A ) and the ^negative (2) are connected to a first input (B) of a flip-flop (7) and that a first output (Q ₄₁ ) of the Flip-flops (7) to the gate of the depletion transistor (4) and a second output (Q ₂ ) to the gate of the enhancement transistor (3) is connected.