DD201833A5 - PROCEDURE FOR ERROR CORRECTION - Google Patents

Abstract

The aim and the object of the invention are to present an improved method for error correction, with which both error bursts and random errors can be effectively corrected. The data is received as blocks of digital data words and applied to a first decoder as first error correction blocks consisting of a plurality of informational sources, a series of first verification words, and a series of second verification sources. The received words are decoded therein and the information words and the first checks are corrected by forming error syndromes using the second checks. A display address, i. an additional bit is added to the words to indicate if an uncorrected error remains in such words. For example, the display address is "1" if the associated word contains uncorrected errors while the display address is otherwise "0". Thereafter, the words are deinterleaved in a deinterleaving stage by delaying the words by different amounts and given as second error correction blocks to a second decoder.

Description

232224 4

Berlin, 3.3.1982 59 543/13

Field of application of the invention

The present invention relates generally to a method for error correction.

Characteristic of the known technical solutions

An effective data transmission system for correcting error bursts using a so-called bi-directional interconnection c'cross-interleave technique has already been proposed in the application Έχ.218,256 of Dec. 19, 1980 of the same assignee. In the interleave technique, words of a PCM data signal sequence are provided in multiple sequences or multiple channels arranged in a first order state and applied to a first error correction coder for generating a first check word sequence Then, a word in the second order state is applied to a second error correction encoder for each of the PCM data signal sequences in the multiple channels to generate a second test word sequence thereby causing a double interleaving (ie, a double reordering). for every word The purpose of this double interleaving is to reduce the number of erroneous words in each word group contained in a common error correction block when the check word contained in such error correction block

r around ΛΟ O 0 * 0 «

232 224 4>

3.3,1982

and the associated PCM data is distributed and transmitted. At the receiving end all erroneous words are distributed between the different blocks and transferred to their original state. In other words, an error burst can be distributed when it arises in the course of the transmission. When the interleaving described above is performed twice, the first and second checkwords are respectively used for correcting words in various error correction blocks. Thus, an error, even if it can not be corrected by a first and a second check word, can be corrected by other check words. This technique offers a significant advantage in error correction capability of error bursts.

However, if only a single bit in a word is detected as faulty, the entire word is said to be faulty. Therefore, if a received data signal has a relatively large number of statistical errors, then said double-interleaving method is not always sufficient to correct these random errors.

In the event that a first decoding step is performed for the second error correction block, then a conversion to the first order state, and a subsequent decoding step is performed on the first error correction block, it is possible that even if an error occurs in the subsequent decoding it is not assumed or recognized as an error, or that four word errors are erroneously considered to be a single error, Therefore, if such an error is overlooked and an erroneous error detection false

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Error correction is executed, a subsequent overlook of errors and erroneous error detections is caused in the next decode stage. Therefore, erroneous operation is most likely to occur. Moreover, if the number of word errors increases, the probability of occurrence of the above erroneous correction becomes unacceptably high. Therefore, an allophone occurs in the analog audio output if, for example, data with an unrecognized error occurred in PGM audio signals and the incorrect data is uncorrected in a digital-to-analog converter,

t aim of the invention

The aim of the invention is to provide an error correction method with which the proportion of overlooked errors can be reduced.

A further object of the invention is to provide a method for error correction with which the proportion of erroneous error correction can be reduced,

Another object of the invention is to provide a method for error correction, after which the construction of a first stage of a decoder can be simplified, as it is in the V _he go to error correction with the cross-interleave technique used.

Another object of the invention is to describe a method of error correction that prevents the development of allophones when a PCM audio signal is transmitted.

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59 54-3 / 13

It is another object of the invention to disclose a method of error correction that is particularly effective when used in a decoder of a digital audio-disc system.

Explanation of the essence of the invention

The object of the invention is to present an improved method for error correction, with which both error bursts and random errors can be effectively corrected.

Bs it is proposed that an error correction code with a high error correction capacity, for example a Beed-Solo · mon (ES code), Bose-Chaudhuri-Hocquenghem (BCE) code, or a variant of a b-adjacent code, with the E word error, z. For example, two word errors in a block, and also M word errors can be corrected, eg, three or four word errors, if the location of the error is known, combined with the multiple interleaving technique described above.

With this error correction code, it becomes possible to simplify the construction of a decoder if only a single word error is to be corrected.

In accordance with one aspect of the present invention, a method for error correction of received transmitted data, such as a PCM digital audio signal, is disclosed. The transmission may be via a carrier, such as radio or cable, or may include recording the signal on a magnetic tape, optical disk or other medium. The data will be

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received as blocks of digital data words and given to a first decoder as first error correction blocks, a group of first test words and a series of second test words. The received words are decoded therein and the information words and the first check words are corrected by forming error syndromes using the second check words. A display address, d. h, an extra bit, is added to the words to indicate whether an uncorrected error remains in such words. For example, the display address is "1" if the associated word contains uncorrected errors while the display address is otherwise "0". Thereafter, the words are deinterleaved in a deinterleaving stage by delaying the words by respective different amounts and given as second error correction blocks at a second decoder. By means of the first test words, the information words are decoded there by forming error syndromes, while in case of existing errors the word location of all erroneous words within Whenever there are more than a predetermined number of erroneous words in the first error correction block, all words therein are given a display address by the first decoder. Then, in a second decoder, up to a second predetermined number, erroneous words in the second error correction block are corrected. if the location of each erroneous word calculated from the error syndromes matches at least one of the erroneous words, it is represented by the added display codes

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Thereafter, the erroneous ones (determined by the display address) are compensated, for example by interpolation.

The method is further characterized in that even if all the erroneous words are corrected up to the first predetermined number in the first decoder, an error indication code is added to each corrected word. The first predetermined number is set smaller than the highest number of erroneous words that can be reliably corrected in the first decoder by using the error syndromes when the location of the erroneous words is known.

The first predetermined number is selected to be the maximum number of error words that can be reliably corrected in the first decoder by applying the error syndromes when the location of the erroneous words is known. In the first decoder, up to K words of the information words and first check words are corrected, and if the number of erroneous words within the number of information words and first check words is equal to or greater than K, all such words receive a display code for indicating an error. In the first decoder, bi-to-k errors within the information words * and first test words are corrected and corrected for each one. Word is added a display code for indicating an error, and if the number of erroneous words within the information words and first test words is greater than a number set smaller than K, all the information words and first test words are given a «

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correcting errors occurring in the information words and check words of all second error correction blocks by calculating the error syndromes and obtaining the locations of the erroneous words therefrom, but determining the error locations for M <K for up to M words before error correction. In the second decoder, when the display codes are commonly connected to the second error correction block which indicates the error number up to the predetermined number of not more than M and the location of each erroneous word indicated thereby is calculated to be correct, an error syndrome is calculated from the information words and first test words and correcting the preselected number of the error words by applying the location of the erroneous location and the error syndrome. If the number of erroneous words within the words of the second error correction block is greater than a predetermined limit, the second decoder corrects the indication of the added display code as erroneous Y / loci. A second predetermined number is chosen as the maximum number of erroneous words that can be reliably corrected in the second decoder by applying the error syndromes when the location of the erroneous words is known. A second predetermined number is chosen smaller than the maximum number of erroneous words that can be reliably corrected in the second decoder by applying the error syndromes when the location of the erroneous words is known. The number and the type of F nlerkorrekturblock contained in the second _{e e} F counter determines whether the second decoder performs error correction of the information words or not. The method for error correction is characterized in that a first error correction block is formed from a word contained in each of the data sequences of multiple channels in a first order state and a first check word for a word, wherein the data

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following the multiple channels and first check word sequences are delayed by different times in the respective channel to be converted into a second order state, and a second error correction block is formed from a word contained in each of the data sequences of the multiple channels and first check word sequences in the second order state, and a second test word for the latter word, said first and second error correction blocks are formed in accordance with the error correction codes, so that the P _e hlersyndrome be calculated and errors up to K words that are contained in the same block, by obtaining the error locations from the Error syndromes can be corrected, and a first decoding is performed in a first decoder for the second error correction block of the transmitted data sequences and PCM data sequences of the multiple channels and first test word sequences in the first order state by different times in their n corresponding channels to be converted to a first order state, and then a second decode is performed in a second decoder for the first error correction block and the error correction method consists of the following steps:

Correction of errors up to a predetermined number of words in the second error correction block during the first decoding j

Adding a display code for indicating an error in the respective word within a block when error words exceeding the predetermined number are detected, indicating that all words in the block are unreliable and can be assumed to be erroneous, and

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Calculation of an error syndrome from a plurality of words contained in the first error correction block. Subsequently, the error words are corrected by a predetermined number by obtaining the errors β on the basis of the error syndromes used in the second decoder

embodiment

The invention will be explained in an embodiment with reference to the accompanying drawings. Show it;

Fig. 1: (consisting of Figures 1A and 1B _e) is a block diagram showing an example of an error correction encoder that is applied in the present invention;

Fig. 2 shows an arrangement of a block of encoded data in transmission;

Fig. 3: (consisting of Figs. 3A and 3B) a block diagram showing an example of an error correction decoder to which the present invention is applied;

Figs. 4, 5, 6, 7j, 8 and 9 are diagrams for explaining the operation of the error correcting decoder.

First, an error correction code used in this invention will be explained. In this description, the error correction code is represented by a vector representation or by

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the representation of a cyclic group expressed.

First, consider an m-order irreducible polynomial on a Galois field GF (2). On the field GP (2), which contains only the elements "0" and "1", the irreducible polynomial Kx) has no real root. Therefore, consider an imaginary (or complex) root OC that satisfies the polynomial Kx) = O. Here are 2 ^m different elements Q ₉ & C. i & L _} <Cj ..... · * <y_ ^m , which are each a power of -al and contain a null element, an extended Galois field GF (2 ^m ). This extended field GF (2 ^m ) is a polynomial ring with an irreducible polynomial F (x) mth order over the PID GK2) as modulo. The element of GP (2 ^rn ) can be represented as a linear combination of 1, ot = £ xJ, cC = £ x j »··· ^ a ^0- J = £ x ^m " * J. These elements can be represented as follows become:

^a o ^{+ a}

^a 0 ^{+ a} ^ ^{+ a} £ ^{+ a} ^

or

^ ^a m-1 * ^a m-2 * ··· ^a 2 » ^a l» ^a o ^ »

where a _Q , a... a_-j in GP (2) are elements »

As an example, the extension field GP (2) and as

8 4-32

Modulo the polynomial Kx) = x + x + x + x + 1 (all variables represent 8-bit data). This field

GK2) can be printed out as follows:

a ^ x + agx + aj-x + ax ^H + a ^ x + a ^ x + ax + aQ or

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3.3.1982 59 543/13

Therefore, by way of example, a.sup. Is considered to be the highest order bit (MSB) and _{a.sub.Q is} considered to be the lowest order (LSB) bit. Since a _n belongs to ^{; /} , .GP (2), its elements are either O or 1 ·

P _e rn is the following matrix T derived with rows and m columns of the polynomial P (x):

T =

1 O

O O 1

O O O

^{1 oil} 1

I ₂

O O

¹ Oi-I

Otherwise, can use an expression to this representation, containing a cyclic group and in which considering that the rest of the Galois ^f chen extender field GP (2 ^m) (with the exception of the zero element) forms a multiplying group of degree 2 ^m If the elements of GF (2 ⁿⁱ ) are represented by a cyclic group, the following expression is obtained:

2m-2

In the present invention, H k check words are generated on the basis of a parity-preform matrix if m bits form a word and η words form a block:

2 3 2 2 2 4 4

- ¹² -

rn-2

oil

2 (n-2)

2 OL

3.3.1982 59 543/13

(N-2)

In addition, the test matrix H using the matrix T can be represented as follows:

I _Tn -1 T _T 2 (n-1) T 9 • O »

n-2 2 (n-2) '

Here, I is a unit matrix with m rows and m columns * As already mentioned, the expressions using the root ^ are basically the same as when using a generation matrix T ₀

Further, taking as an example the pail of four (k = 4) check words, the check matrix H is given the form:

n-1

1 _L n-2

2 (n-2) 3U-2)

• ·. c /

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In this case, if a single block of received data

as column vector ν =

_n «2»

^W 1 »

^{with Wi}

When E i + e i is expressed and e i is an error pattern, four syndromes S q, S ₁ , S _2, and S i generated at the receiver side can be expressed as follows:

's "I O S 1 S 2 S 3

= H · V ^J

This error correction code can correct up to two word errors in one error correction block and also three word errors or four word errors if the error location is known.

There are four check words in each block (p = W ^, ^ = Wp »T = W ₁ , S = Wq). These test words can be obtained from the following relationships:

r r

= a

= b

= C

= d

in that means the sum of i = 4 to n = 1.

If the calculation process is omitted, the result of the calculation can be represented as follows:

232 224 4-η-

212 _C 156, 158

218

153 2

138 158

152 135 2 156

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209 ' a 152 b 153 C 212 .d ..

The coder provided on the transmission side has the test words p, q, r and s in the above

Way to form.

Next, the fundamental algorithm of error correction will be described when data, including the test words generated in the above manner, is transmitted and received.

(.1) The syndromes are all Hull if there is no error:

S ^. = S ^. = Sp = So = Oo

(2) In the presence of a single word error (an error pattern is represented as egg):

S ₀ = ei, S ₁ = oC ' ^L ei,

= <* L ^{2: L} ei, S ₃ =

This results in the following relationships:

= S

S ₀ =

3 *

Whether there is a single word error or not, can thereby

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judgment is made as to whether or not the above relationship holds when i is successively changed · The following relationship is established:

S ₁ Zs ₀ = S ₂ Zs ₁ = S ₃ Zs ₂ = <χ ^χ ₀

Consequently, the pattern for oC is compared with the patterns previously stored in a ROM (Read Only Memory) for detecting the defect i. At the same time, the syndrome S ₁ becomes the error pattern ei itself.

(3) When two word errors occur (ei and ej), the syndromes follow the relationships:

= ei + ej

= oc ^ i +

The above equations can be modified as follows:

S ₃ =

If the following equations can be established, two word errors can be distinguished accordingly:

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+ S ₁ ) ^ s ₁ + S ₂

S ₁ + S ₂ ) = dL ^J S _2. + S ₃₀

With the above equations established, it is assumed that there are two word errors in the block. Thus, the error patterns are expressed as follows:

b ₀ + cc O ₁ b ₀ + * c O ₁

ei = and ej

C4) If three word errors occur (ei, ej and ek), the syndromes are represented as follows:

S ₀ = ei + ej + ek

j ₊ o6 ^3k ek

The preceding equations can be modified as follows:

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Accordingly, the following equations can be derived:

<J (^ ^k S ₀ + S ₁ ) + (Ct ¹⁵¹ S ₁ + S ₂ ) = (oc ¹ + ^ K «* ³ - ₊ cC ^k ) ei

Therefore, if the following equation is satisfied, which is a necessary condition for three word errors, three word errors can be distinguished. In this case, the conditions

S 7 ^ 0, S ₁ ^ O and S ₂ φ O are considered fulfilled:

oi. ¹ ^ cL ³ U ¹⁵¹ S ₀ + S ₁ ) + (S ^ S ₁ + S ₂ )] = o ^ ^j (oC ^k S ₁ + S ₂ ) +

The respective error patterns are expressed as follows:

ei =

(1

S ₀

(1

4 -18-

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Sq + (oL

ek =: -

In fact, the construction of a circuit for the correction of three word errors is extremely complicated and the time required for the correction is long. Therefore, in practice, a method of error correction is used in which the above operation is combined with an error correction method in which the error locations i, j, k and 1 are known by an error indication bit or a display address and the above equations are applied for the test »

(5) If there are four word errors (ei, ej, ek and el), the syndromes are represented as follows:

Sq = ei + ej + ek + el

oC ^3k ek

The above equations can be modified as follows:

(1

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(1 + OCjJ- ¹ Xi + OiJJ- ^k Xi

(1

(1 + oL ^l " ⁱ ) (1

Therefore, if the error locations (i, j, k, 1) are represented by display addresses, the error can be corrected by the above calculation.

The basic algorithm of the above error correction is that, in a first step, it is checked by means of the syndromes S _Q to S ^ whether an error exists or not, while in a second step it is checked whether it is a one-word error or not , and in the third step it is checked whether the error is a two-word error or not. When up to two word errors are corrected, the time required for all steps becomes very long, which becomes a problem especially when the error location is formed by two word errors

A modified algorithm will now be described, which is very effective when the correction of two word errors is assumed without the above problem arising.

The equations of the syndromes S, S., S ^ and S ^ in the case of two verbal errors (ei, ej) are as follows:

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S _Q = ei + ej

S ₃ = ^3l oC ei J The above equations modified as follows: CoL ¹ S ₀ + S ₁₎ (OL ¹ S ₂ + S ₃₎ = (^ ¹ S ₁ + S ₂₎ ² _O

The equation is further modified and the following error-position polynomial is formed:

(S ₀ S ₂ + S ² ) ^ ²¹ + (S ₁ S ₂ + S ₀ S ₃ ) ^ ¹ + CS ₁ S ₃ + S ₂ ² = O

The constants of the respective terms of the above polynomial are now assumed as follows:

S ₀ S ₂ + S ₁ ² = A

S ^ S ₂ + SqSo = B

S., S-, + S ^ = C β

By using the above constants A, B and C, the error location of two word errors can be formed:

(1) In case of no error:

A = B = C = O, S ₀ = O and S ₃ = O ₀

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(2) In case of a one-word mistake

If A = BC = O, S _Q ^ 0 and S ^ φ 0 is satisfied, the error is assumed to be a one-word error. From the relationship

oil t ^s o

the error location i can be easily determined. This will be the error when using the relationship

ei = Sq corrected.

(3) For two word errors:

If an error occurs for more than two words, A / 0, B / 0 and C / 0 are met and the decision becomes quite simple. , -

The following equation is set up:

Atf. ²¹ + B ^ ¹ + C = O, where i = 0 to (n-1) _e

Assuming B / A = D and C / A = E, the following equations are formed:

D = <* E = oL ^x _{+ &} lK Thus, the equation can be derived:

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o ^ ²ⁱ + D ⁱ + E = 0 ·

If the difference between the two error locations is assumed to be t, d, h _oj = i + t, the following equations are formed:

D = ^ ¹ O ₊ *) B = C ^ ^{1 +} *.

Therefore, this equation can be derived:

D ² ₌ (1 + d}) ² -t ^ t ₊₀

Ξ " ς £ *

If the value of CC + et for each value from t = 1 to (n-1) previously written in a ROM and found

ο will match the value with the value of D / E, the

from the output of the ROM and a received word, t can be obtained. If such a match is not found, this means that the errors occur in more than three places »

Therefore, if the expressions are presupposed

Y = 1 + £ C ~~ - J)

The following expressions can be made:

<£ ^X = D / K

C ^ ^ = D / Y ρ

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From the above equations, the error locations i and j are formed. Then the error patterns ei and ej can be represented as follows:

_{ei =} _2L-2 L_ ₌ s / Y + S ₁ / D

¹ S ₀ + S ₁ ) ₌

On the other hand, the errors can be corrected.

The above modified correction algorithm can significantly shorten the time required to calculate the error location in the correction of two word errors compared to the fundamental algorithm.

In addition, if the number of check words is increased, the error correction capacity can be improved accordingly. For example, if k is 6, three word errors can be corrected and six word errors can be corrected if the error location is known. ·

An embodiment of the present invention will now be described with reference to the accompanying drawings.

Therein, the invention is applied as an example of the recording and reproduction of a PGM audio signal.

? 2 2 Λ k - ²⁴ "3.3.1982

Pig. FIG. 1 shows as a whole an error correcting urcoder which. is arranged in Aufnähmesystem to which a PCM audio signal is supplied as an input signal. The PCM audio signal is applied so that the left and right stereo signals are sampled at a sampling frequency fs (e.g., 44.1 kHz) and each sampled value is converted to a digital word (e.g., a 16-bit number in two's complement representation is implemented). Accordingly, PCM data words Lq ₉ L ₁ , Lp oo are formed for the left channel of the audio signal and PCM data words R-, R ₁ , R _2. · · Are formed for the right channel. The PCM data words of the left and right channels are separated into six channels each; Thus, a total of twelve channels of PGM-D _a are supplied to the error correcting tenfolgen. At any given time, for example, twelve words L _6n , R _6n , L _{6n + v} Rg _{n +} 1 "L _{6n + 2} , R _{6n + 2} ,

^L 6n + 3 » ^R 6n + V ^L 6n + 4 ' ^R 6n + 4» ^L 6n + 5 ^{and R} 6n + 5 are given to the encoder.

In the illustrated example, each word is set in eight more significant bits and eight less significant bits, and the twelve channels are processed as 24 channels. For simplicity, each individual word of the PCM data will be referred to as Wi, with the eight higher bits designated as Wi, K and the eight lower bits as Wi, B. For example, the word L ^ _{n is divided} into two words: W _{12n A} and W _12n , B ₀

The PCM-D _a tenfolgen channels 24 are first placed on an even-odd interleaving. 1 If η is an integer 0, 1, 2 ..., then the words are

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L _6n (ά ho, W _12n , A and W _12n , B), Rg _n Cd. h _o W _{12n + 1} , A and ^W 1

12n ₊ 1 · ^Β > · ^L 6n ₊ 2 ^(d · * · ^W 12n + 4, ^A ^ ^W 12n ₊ 4 ' ^B) ' R _{6n + 2} Cd. H. W _{12n + 5} A and

CD. H. W _{12n + 8} , A and W _{12n + 8} , B), and that is W

each with even-numbered order, while the remaining words are odd-ranked words. The PCM data sequences, which consist of even-order words, are run with a single interval int erum by means of the delay circuits or delay lines 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6S, 7A and 7B of the even-odd interleaver 1 is delayed. Of course, it is possible to delay words by more than one word, e.g. For example, eight words. Moreover, in the even-odd Ygrschachtelungseinrichtung 1, the even number of words hierarchy existing 12 D _a tenfolgen be so converted or shifted so that the first 12 transmission channels are occupied, whereas the odd-numbered of words hierarchy existing are converted 12 D _a tenfolgen so that they each have the transmission channels 13 to. 24 occupy.

The even-odd interleaver 1 has the function of preventing more than two consecutive words of the respective left and right stereo signals from being false; In this Pail it is almost impossible to correct the mistakes.

To illustrate the advantage of this feature, consider, for example, three consecutive words Li-1, Li and

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Li + 1 considered "If the word Li is erroneous and uncorrectable, it is highly desirable that both adjacent words Li - 1 and Li + 1 be correct. The reason for this is that to compensate for an uncorrectable erroneous location Li, this word is interpolated between the previous correct word Li-1 and the following correct word Li + 1, typically using the mean of Li-1 and Li + 1 is formed. The delay lines 2A, 2B. 7A and 7B of the even-odd interleaver 1 are arranged so that the adjacent words appear in different error correction blocks. The reason for combining the groups of transmission channels for the even and odd-order words is that when the data sequences are interleaved, the distance between the recording positions of the adjacent even and odd-order words is as large as possible.

At the output of the even-odd interleaver 1, the words of the 24 channels appear in a first order state. From the interleaver 1, the respective PCM data words are passed word by word to an encoder 8, which then receives the first check word QJ _2n '^ 12n + 1 Q _{12 2} , and Q- | _{2n +} 3, as shown in the above expressions p, q, r, s ₀

Then comes an error correction block containing the first check words:

< ^W 12n-12 » ^A ·· ^W 12n-12 ' ^BW 12n + 1-12, ^k \ ^W 12n + 1-12' ^{By W} 12m H- 4-12» ^A 5 ^W 12n ₊ 4-12> ^B i ^W 12n ₊ 5-12 » ^{Ai W} 12n ₊ 5-12> ^Bj

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^η 12x1 + 5-12 '

^W 12n + 9-12 ^{> Ai} . ^W 12n + 9-12 » ^B * ^W 12n + 2» ^{A; W} 12n + 2 ^{>B; W} 12n + 3 » ^{A; W} 12n ₊ 3 ' ^{Bj ¥} 12n ₊ 6>^{A; W} 12n ₊ 6 ' ^{Bi W} 12n ₊₇ » ^{Ai W} 12n ₊ 7' ^{B5 W} 12n + 10» ^AW 12n + 10 » ^BW 12n + 11» ^A ' ^// 12n + 11 » ^{B; Q 5 Q} 12n

12n + 10 » ^AW 12n + 10» ^BW 12n + 11 » ^{A //} 12n + 11» ^{B; Q} 12n ^{5 Q} 12n + 1 ^; 12n + 2 » ^Q ^

The first encoder 8 performs its function by calculating the first check words Q- | ₂ nk ^is ^ i2n + 3 ^en ^ ^s P ^rec ^ - ^erii l of the number of words of a block (n = 28), the bit length m of each word (m = 8) and the number of test words (k = 4) out"

The 24 PCM data word sequences and the four Prüfwortfolgen are then fed to an interleaver 9 _o In this interleaver 9, the relative positions of the channels are changed so that the Prüfwortfolgen between the PCM data sequences are arranged, there are the even number of words ranking and the PGM Data sequences consisting of odd-order words, after which a delay operation for these interleaving sequences expires. This delay process will start with the. second transmission channel, carried out on 27 transmission channels by means of delay lines with a delay amount of 1D, 2D, 3D, 4D ··· 26D or 27D (where D represents a delay unit) ·

At the output of the interleaver 9, 28 sequences of data words appear in a second order state. The data words are taken word by word from the respective data sequences and brought to the encoder 10, which

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the second test word he-j2n '^ 12n + 1 ¹ ^ ¹ ^ n 3

same way as the check words Q-j? is ^ 9ip 3 *

Just as the above encoder 8 supplies the first check words corresponding to the parameters η = 28, m = 8 and k = 4, the similar encoder 10 provides the second check words corresponding to the parameters η = 32, m = 8 and k = 4.

An error correction block is formed which contains the "second test words and is formed of 32 words as follows:

12 ^»A * ^W 12n-12 (D + 1) ^{'B' W} 12n + 1-12 (2D + 1 ^W 12n + 1-12 (3D + 1) * ^Bi

^W 12n + 4-12 (4D + 1) ^{> Ai W} 12n + 4-12 (5D + 1) ^{>B; W} 12n + 5-12 (6D + 1) » ^A * ^W 12n + 5-12 (7D + 1) ' ^B * ^{om> Q} 12n-12 (12D) ^{i Q} 12n + 1-12 (13D) ^SQ 12n + 2-12 ( ^Q 12n + 3-12 (i5D) * * "* ^W 12n + 10-12 (24D) ^{iA; W} 12n + 10-12 (25D) ^jB » ^W 12n + 11-12 (25D) » ^A * ^W 12n + 11-12 (27D) » ^Bi

, ρ. ρ

» ^R 12n + 2 ' ^r 12n + 3

23222A 4 - ^ - ^ -

59 543/13

Thereafter, an interleaver 11 is provided, the delay lines having a delay of a location for the transmission channels of the 32 even-order data sequences including the first and second test words and inverters 12, 13, 14 and 15 for inverting the second test word sequences. The interleaver 11 serves to prevent errors occurring in the area between the blocks and to act on so many words that their correction becomes impossible. The inverters 12, 13, 14 and 15 are intended to avoid a malfunction when all the data in a block is switched by a failure in the transmission "UuIl". This means that in the event of a failure, the inverted test word sequences in the playback star are correctly distinguished. For the same purpose inverters can be provided for the first check word sequences.

To produce the in Pig. 2, the finally-derived 24 PCM data sequences and 8 check word sequences are serially connected as 32 word blocks, and a 16-bit sync signal is added to the obtained serial data at the top. The block thus obtained is transmitted over a transmission medium or on a carrier. In Fig. 2, the word obtained on the ith transmission channel is represented as U.

Practical examples of the transmission medium or the carrier for the transmitted signal may be magnetic recording and reproducing apparatus, disk for use in a disk player or the like. _E

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The reproduced data of all 32 words of each block of the transmitted signal v / is applied to the input of an error correcting decoder, as shown in Pig, FIG. The transmitted data received at the error correction decoder may contain one or more errors since the input data is reproduced data. If there is no error, then the 32 words that are. to the input of the decoder, correspond to the 32 words at the output of the error correction encoder. In the error correction decoder, a deinterleaving process complementary to the corresponding interleaving process at the encoder is performed to reverse the data to its original state. In the presence of an error, the error correcting process is performed after the restoration of the original state of the data.

As shown in Fig _o 3, a deinterleaver 16 is first provided with delay lines, each having a delay amount of ei em word for the transmission channels of odd ranking, and inverters 17, 18, 19 and 20 for the reversal of the received second Prüfwortfolgen. The outputs at the deinterleaver 16 and at the inverter 17 · .. 20 are coupled to a first decoder 21. In this first decoder 21, the syndromes S ^ ₀ , S .., S ^ and. Is p ^ generated according to a matrix, such as the Reed-Solomon parity check matrix E _n, (Fig. 4) by 32 input words V in Fig. 4, wherein the above-mentioned error correction on the basis of the syndromes S ^ ₀ to S , ^ is performed. In Fig. 4, oC is an element of GF (2) and a root of

O / -2 O

F (x) = χ + XT + χ + χ + 1. The decoder 21 passes the corrected 24 PCM data sequences and four first check word sequences

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from · Each display word or error detection code (at least 1 bit) is added to each word of the data strings to indicate whether or not there is an error in the word (error display address "1") or not (error display address "0"). In Figs. 4 and 5 and in the following description, the received word vVi is referred to as Wi only.

The output data sequences from the decoder 21 are applied to the de-interleaver 22, which serves to compensate for the delay process performed by the interleaver 9 in the error correction coder and has corresponding delay lines with correspondingly different delay values 27D, 26D, 25D _βββ 2D and 1.D, which are provided for the first 27 transmission channels. The output of the de-interleaver is fed to a second decoder 23 in which the syndromes Sp ₀ , Sp ₁ and S ₂₂ and S ₂ ^ are formed according to a matrix such as the Reed-Solomon parity check matrix Hq ₂ (Figure 5). The 28 words Vm as shown in Fig. 5 are input, and the aforementioned error correction is performed on the basis of the syndromes S ₂₀ to S ₂ -.

The decoder 23 clears the display address with respect to each word whose error is corrected, but does not erase the display address with respect to any word whose error can not be corrected.

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The data sequences appearing at the output of the decoder 23 are applied to a device odd deinterleaver 24 in which the PCM data sequences consisting of the even-order words and the PCM sequences consisting of the odd-order words are rearranged, that they are in alternate transmission channels, with delay lines provided with a one word delay for the PCM data strings consisting of the odd-order words. This compensates for the operation performed in the encoder prior to transmission. At the output of the G _e rade-odd SntSchachtelungseinrichtung 24, the PCM data sequences are provided that have the original state of order, and the predetermined order of precedence of the digital signal is completely restored as it had existed before input to the error correction encoder.

To eliminate the non-correctable errors, a compensation circuit is preferably provided in the next stage after the even-odd deinterleaver 24, which is not shown in Fig. 3. For example, averaging interpolation may be applied whenever errors are not corrected by the decoders 21 and 23 so that any remaining errors are obscured and eliminated.

In the second decoder 23, the error correction is carried out by means of the display address, but in the run-up to the second decoding there are some modifications. Such an error correction is a process (RC.,) In which a one-word error is corrected, and another process (Fig.

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in the zv / ei word error, be corrected. Further, there is such a process (RG-,) in which 3 word errors or more are corrected. In addition, however, it is also possible to perform the error correction using the Fghlerstelle determined by the Änzeigeadresse in conjunction with the respective error correction process mentioned above.

The probability that within the respective processes FCj, FC ₂ or FG- which assign the first decoder 21 for a single word error, zv / ei word error or three or more word errors to a display address · error detection is overlooked or erroneous error correction in the next decode stage may be performed by the relationship of FC. to FC ₂ and from FC ₂ to FCt. In contrast, however, the case can occur very frequently in which an error of a word, albeit already corrected or a word containing no error, has a display address of "1". Thus, the next decode stage of the error correction becomes difficult or even impossible For this reason, the joint operation of the first and second decoders 21 and 21 is

23 with the combinations of FC ₂ - ^ RC., FC, ⁵ ^ RG ₂ ,

FC ₂ => RF ^, FC ₂ - ^ RC ₂ and FC ^ ^ RF ^ very convenient.

In the example of the invention shown in FIG. 3, up to a word error is performed in the first decoder 21

Using the combination FC ₉ ^ RC ₁ in the above

Combinations corrected. If it is detected that more than two word errors exist in one error correction block, all 28 words in the error correction block

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address with at least one bit added, d. H. all the words of the 32-word block except for the second check words to indicate errors in the manner set forth above. "This display address is" 1 "if there is an error, but is" 0 "if there is no error. In the case where a Y / often consists of 8 bits, the display address is added one bit more than MSB so that one word thereof consists of 9 bits. Then, the words are processed by the descrambler 22 and thereafter to the second one Decoder 23 given.

In this decoder 23, a one-word error is corrected by using the number of error words in the first error correction block indicated by the display address or the error location.

FIG. 6 is a chart showing an example of the process of error correction performed in the second decoder 23. In Fig. 6 and the following description, the number of erroneous words represented by the display address is expressed by N, and the error location represented by the display addresses is designated by Ei. Moreover, Y in Fig. 6 represents "yes" and N represents "no".

(1) The presence or absence of an error is determined by means of the syndromes S ₂₀ to S ₂ ^. If

^S 20 ^{= S} 21 ^{= S} 22 ^{= °} "so it is decided that no error is present ₀

3 2 224 4 -3 ₅ -

At the same time, it is checked whether

3o3.i982 59 543/13

is satisfied or not.

If i \ f £ z ^, there is no error and the display addresses in the error correction block are cleared ("0"). Conversely, if Ή> z ^ , the error detection by the syndromes is erroneous and the display addresses remain unchanged or the display addresses are set to "1" for all words in the block. In the latter case, the value of z. chosen relatively large, z, B, 14o

(2) In the case of an error, it is determined by calculating the syndromes whether or not this error is a one-word error. In case of a one-word error, the error location i is obtained. Then, it is determined whether the error location i obtained by calculating the syndromes coincides with that indicated by the error indication addresses. When the plurality of error locations are indicated by the display addresses, it is examined which error location i coincides with which of the multiple error locations indicated by the display addresses. If i = Ei, then it is examined whether the relationship N "SZ ₁ holds or not, in which z _?

P s

way is 10. If the relationship N =. Z ₂ gil * j ^s °, the error is accepted and corrected as a one-word error. If the relation ^ _Ό > ζ ₂ holds, then it is possible that the error will be incorrectly held as an error-prone word. The display address therefore remains unchanged, or all words are assumed to be erroneous and the corresponding display addresses are set to "1".

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For the Pall that the relation i ^ Ei holds, it is determined whether 3SL = z, or not, where Z _{3 has} a very small value, z «B ₀ 3. If Ii iz ^, then one becomes One-word error at the error location i corrected by calculation of the syndromes.

In the case of L) z ^ is also checked whether I \ f = z. applies or not ο

is true, this means that although the decision of one-word error by the syndromes is erroneous, N is too small. In this case, therefore, the display a that sen all words of the block are set to "1". In the opposite case of N> ζ . all error indication addresses remain unchanged. In this case z * is for example 5

(3) In the case of at least one error, but the error is not a single word error, it is decided whether or not the relation H is less than or equal to Z ₁ . If N 2 Z ₁ -, then the display address is poor or not reliable sufficient, so that the display addresses for all words are set to "1". If, however, Ή > Zr holds, then all display addresses are retained.

Although up to two word errors in each of the first and second. Decoders can be corrected, in the example, only the correction of a one-word error is performed, which reduces the probability that it in the decoders to an erroneous error detection

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^ZZZ4 ^ 59 543/13

or incorrect correction of errors. In addition, since the error correction by calculation of the syndromes is limited to binary word errors, the structure of the decoders can be greatly simplified.

(4) As in Fig. 6 by the. broken line is shown, it is possible to correct errors in up to M words using the error locations indicated by the display address. "Up to four word errors can be corrected, but a method of solving the display addresses can not avoid a misregistration. Therefore, given the time and complexity required for a correction process, M is chosen to be about 2. Then, two word errors with respect to the error locations i and j indicated by the error display addresses are corrected. In the case of U Φ M, the display addresses remain unchanged or the display addresses of all the words are changed to those indicating errors.

In the foregoing description, the practical values of the comparison are the values of e.g. to Z _n - in terms of the number N of error indicating display addresses in a block are only examples. In the above example, the error correction code has a possible advantage in that it is erroneously evaluated as error-free if there are more than 5 word errors in a block can, but even if more than 4 word errors in a block can be falsely judged as containing only a word error. Therefore, comparison values may suitably be selected taking into account the possibility that errors may be missed or erroneous corrections occur.

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As already stated, if two word errors are corrected in the second decoder by the application of the added display addresses, then the error correction capability can be made very high. In this case, after it has been determined that there is no error and the error is not a one-word error, the error correction is performed by the display address. The probability that the correction by the display address becomes erroneous can thereby be reduced.

In a second example of the invention, the combination of FO ..- ^ RCp of the already illustrated combinations is applied, as shown in the figure of Fig. 7. That is, two word errors in the first decoder 21 are corrected. The error-correcting algorithm used in this case is the already mentioned modified algorithm. If it is recognized that more than three word errors exist in an error correction block, each of the 28 words is assigned a display address with a bit representing the presence or absence of an error. This concerns all the words of the ^ word block except the check words in the second error correction block. In the second decoder 23, two word errors are corrected by means of the number of error words in the first error correction block indicated by the display address or the error location. Since two local errors are corrected at the second decoder 23, the modified error-corrected ur algorithm is recommended. In other words, it becomes the fault locus already mentioned at the beginning of the flow chart shown in the figure

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+ Βο6 ^χ + 0 = 0

calculated and the error correction by means of the constants A, B and G of the preceding polynomial and the syndromes S ₂₀ to Sg- performed. At the same time, it is possible to use the fundamental algorithm in which, as shown by the dotted line in Fig. 1, by using the syndromes, the error-freeness Existence of a one-word error and thereafter the existence of two word errors is demonstrated step by step,

(1) It is examined whether an error exists or not. If

A = B = C = O, S ₂₀ = O and S ₂₃ = O,

As a rule, it is assumed that there is no error ο At this point, it is examined whether the relation Ή = z ^ is satisfied or not.

ΙΓ _ρ = Z ₁ ,

it is assumed that there is no error and the display address in the error correction block is cleared (ie set to "0"). In contrast, if ü_> Z ₁ , syndrome error detection is considered false and the display address is left unchanged or else all words in the block are assigned a display address of "1", in which case the value of z ^

2 3 2 2 2 4 4 - ^ - 3.3e982

59 543/13 chosen relatively large, ζ. B. H.

(2) It is checked whether an error is a one-word error or not. If

A = B = C = 0, S ₂₀ Φ 0 and S ₂₃ φ 0,

the error is usually regarded as one-word error and the error i from the relationship

receive. It is determined whether the error location i coincides with the position indicated by the display address or not. If the majority of the error locations are indicated by the display addresses, it is checked whether the error location i coincides with 'any one of them or not. If i = Ei, it is checked if

ET = Z ₂ or not, where Z _{2 is,} for example, 10. If I7 _p i Z ₂ ,

the error is considered as a one-word error and corrected by using ei = S ₂₀ . If N> z ₂ , even if i = Ei, then there is a risk that the error will be misinterpreted as a one-word error, 'because the number of display addresses for Sinwortfehler is too large. For this reason, the display addresses remain unchanged or all words are considered to be defective and the corresponding display

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aaressen set to "1"

 For the pail that i ^ Ei applies, it is checked whether

is satisfied or not, where Zo is a very small value, z, B, 3. If.

N _p = z ₃ ,

a one-word error at the error location i is corrected by calculating the syndrome.

In the case of N> Ζλ, it is further checked whether

N 2 ζ. is satisfied or not »

If the relationship

Z ₃ ^ N _p = Z ₄

is true, this means that, although the estimation of a one-word error by the syndromes is wrong, I \ L is too small. In this case, the display addresses of all words of the block are therefore set to "1". In contrast, the display addresses remain unchanged when

H> z, applies.

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(3) It is checked whether an 'error is a two-word error' or not. If the error is a two-word error, the error locations i and j are determined by calculation. If

A φ 0, B φ 0, C / 0 and D ² / B = ^ ~ ^t ". ₊ oo " ^t , _

where t = 1 ·· 27, the error is considered to be a two-word error and the error locations i and j to

and <* 3 = D / Y

receive. It is determined whether or not the error locations i and j coincide with the error locations Ei and Ej indicated by the display addresses. If i = Ei and j = Ej, the number 'IT of the error-representing display addresses is compared with a predetermined value z, - . If

is true, two _; Word error with respect to the error points i and j corrected. This correction is made by determining the error patterns ei and ej, as stated above »

no correction is made on the assumption that z. More than three word errors were erroneously recognized as two word errors, with the display addresses remaining unchanged or all words in the block being considered erroneous.

232 22 4 Λ - «- 3.3.

59 543/13

If one of the error locations i and j coincide with one of the error locations Ei and Ej, i. h _o i = Ei, j ^ Ej or i ^ Ei, j = Ej, it is checked whether

is fulfilled or not »If

is true, two word errors are corrected with respect to the error locations i and j. If

is, it is checked whether ^;

is satisfied or not _o This check is performed so that if the faults partially match, the number of fault-indicating display addresses is checked to see if it is large or small

holds, then, it is assumed that the number of display addresses is too small and the display addresses of all the words in the block is set to "1. ¹¹

However, if N ^ z ₇ , the reliability of the display addresses can be considered high, so that the display addresses remain unchanged.

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· 59 543/13

If i ^ Ei and j? Ί Eg apply, it is checked whether

^N p =

applies or not. If N is very small, the result is considered more important than the display addresses by using the error location polynomial, and two word errors are corrected with respect to the error locations i and j,

If N> Zg, it is further checked if the relationship

is satisfied or not. This test is similar to the one of

to leave the display addresses of the block unchanged or to set the display addresses of all the words in the block to "1".

(4) If a case deviates completely from cases (1), (2) and (3), ie where there are more than two word errors, no error correction is made. In this case, it is checked if the relationship

is satisfied or not ·

232 22 4 4 - * 5- 3.3.1982

59

= ^Ζ 1Ο

is true, the reliability of the display addresses is set as low and the display addresses of all words are set to "1".

^Z 1O

applies, the display addresses remain unchanged.

(5) In the case where there are less than two word errors, for example, it may be possible to correct three word errors by using the error locations determined by the display addresses. In other words, at Ή = 3, three word errors are corrected with respect to the error locations i, j and k as indicated by the display addresses. If N 4 3, the display addresses remain unchanged or the display addresses of all words are set to "1".

Moreover, the value zi, which is compared with the total number N of the error-representing display addresses in a block, is set as an appropriate value with respect to the probability of forming an erroneous recognition due to the error correction code (in the above example, there is a danger that one more error contains 5 word errors that the above error is not considered an error} if an error contains more than 4 V / location errors, this error can be regarded as a one-word error and "if an error contains more than three word errors

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59 5 * 3/13

this error can be considered a two-word error).

Hereinafter, a more practical example of the error correction method performed in detail will be described with reference to Figures 8 and 9 ", a block of data is driven (step 0,.) In the first decoder 21 in which the existence of an error by use of said error location polynomial and error syndrome is recognized.

(1) If the block is recognized as being error-free, no display address is added and the data is unchanged due to the second decoding (C ₂ ).

(2) If a one-word error exists, the error is obtained. If the error location is less than or equal to a value 31, then this word is corrected. However, if the error is greater than 31, then four word errors are erroneously taken as one-word errors. Accordingly, display addresses are added to all words and the data is then decoded in the next stage Cp.

(3) In the case of two word errors, the error locations are calculated. "If the error locations are each determined to be less than or equal to a value of 31, two words are corrected and display addresses are also added to all the words If more than 31 error locations exist, more will be added Therefore, all words are therefore added to display addresses of "1", which are then assigned to the next stage of decoding (G ₂ ).

(4 ·) In the case of more than three word errors, no correction is made, but all words are displayed.

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addresses are added and the data is then subjected to decoding (C ₂ ) in the next stage.

Subsequently, similar to the first decoder 21, according to the flow chart of Hg, 9 in the second decoder 23, the type of the errors is first determined by means of the error locus polynomial and the error syndromes.

(1) In the case of no detected error, if the display address has been added by a first decoder with "1", it is deleted.

(2) In the case of a sinword error, the error location is calculated. If the error is smaller than or equal to a value of 27, the erroneous word is corrected and the display address added by the first decoder 21 is cleared. However, if the error is greater than 27, no correction is made and the previously added display address bMbt is unchanged.

(3) In case of two word errors, the error locations are calculated. If the error locations are greater than 27, more than three word errors are erroneously recognized as two word 4 errors. At this moment, however, the number of display addresses added in the first decoder 21 is controlled. If the number of display addresses exceeds a value of two, the display addresses remain unchanged If the number of display addresses is less than two, even if two word errors are detected, display addresses are added to all words because the data is invalid as a whole block ,

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Even if the error locations are smaller than 27 and the number of display addresses added in the first decoder 21 is less than three, the display addresses remain unchanged. However, if the number of display addresses is greater than four, the error locations obtained in this stage are compared with the display address added in the first decoder 21.

(a) If no two words are coincident, no error correction is performed and the number of display addresses is checked. If this number equals two or exceeds two, the added display addresses remain unchanged. However, if the number of display addresses is less than two, display addresses are added to all words.

(b) If only one of the words is coincident, the number of display addresses N is also checked if that number exceeds a value of three, e.g. For example, if four is set, the added display addresses remain unchanged. However, if the number is less than three, display addresses are assigned to all the words.

(c) If both words coincide, two words are corrected and the display address is subsequently deleted.

W In case an error is accepted in more than three words, the number of display addresses is checked. If the number exceeds a value of two, the added display addresses remain unchanged, while a display ad- dress is added to all words if the number is less than two.

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During the decoding process, as mentioned earlier, the words identified as erroneous by the display addresses are later compensated for as uncorrectable. In the error correction decoder, as shown in Fig. 3, the error correction is performed using the first check words Q _12n , Q _{12n + v} Q _{12 + 2} , and Q _{12n +} 3, and the error correction using the second check words ^P 12n ' ^P 12n + V ^P 12n + 2 and ^P 12n + 3 3, ^{respectively, once} performed, if the above error corrections respectively twice or more (in practice about twice), the error correction capacity can be substantially increased since the corrected result has fewer errors each time As already stated, in the case where an additional decoder is provided in the last stage, necessary that the check word in the decoder 21 and 23 is corrected.

In the illustrated example of the delay process in the interleaver 9, the delay value differs from one channel to the next by a constant amount of change D, but it is also possible to apply a non-constant change in the delay value, rather than the above-mentioned constant change. Further, the second checkwords Pi are error correction codes formed not only from the PCM data words but also from the first check words Qi. Similarly, it is possible that the first check words Qi are formed of words containing the second check word Pi. Here, a feedback technique can be used so that the second test words Pi are fed back to the encoder which generates the first test words.

As will be apparent from the foregoing description of an example of the present invention

232224 4

each error buzz is distributed through the cross-interleaving process so that both random and error bursts can be effectively corrected according to the method of the present invention.

Since, after the error correction code of the present invention, a display address indicative of the presence of an error is added to each word in accordance with the error detection in the first stage, any risk that the error detection has been overlooked and an erroneous correction has been carried out thereby becomes possible to minimize the number of display addresses and the error locations indicated by the display addresses in the next stage decode.

Further, more than two Dehler can be corrected in a D _e coding system having a simple structure according to the vorli egenden invention using the fault location by the display address. This fact far outweighs the fact that the structure of the encoder is very complicated when the invention is applied to a digital audio-disk system (in theory similar to a video disk) and the encoder uses a recording device of a different construction. In other words, some of the complex encoders are used in the production of digital audio disks, but several thousand very simple decoders are used in almost every disk player. Thus, the application of the present invention to such a system is extremely effective.

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It will be apparent that many modifications and changes can be attained by the skill of the art without departing from the spirit and the scope of the present invention as defined by the appended claims.

Claims (8)

invention claim Method for error correction of digitally transmitted information occurring as a result of the transmission, characterized by the information received in the form of blocks of digital data words and supplied to a first decoder, in the form of first error-correcting blocks consisting of a plurality of information words, a set of first test words and a series of second test words and consists of the following steps: Decoding the received digital words in said first decoder and correcting decoded digital information words and first test words up to a predetermined number by forming error syndromes using the second test words, the corrected and decoded digital information words forming a block of interlaced words, Adding a display code to each of the words of the block of interleaved words to represent whether an uncorrected error remains in such words, and in the event that they exceed the predetermined number of erroneous words in such a block, an error pointer is given to all words ; Delaying the words of each block of nested words in a deinterleaving step by correspondingly different amounts to form such words in one 232224 k · * - 3.3.1982 59 543/13 to de-interleave different order state, providing a second error correction block j Decoding the digital information words of each of these second error correction blocks in a second decoder by forming error syndromes using the first test words and correcting to another predetermined number of erroneous words in such second error correction blocks where the location of any erroneous word calculated from error syndrome η matches at least one of the erroneous words as indicated by the associated display codes, as well as Subsequent combination of any uncorrected and erroneous words determined by the display codes. 2. Method according to item 1, characterized in that, when correcting all the erroneous words up to the first predetermined number in the first decoder, an error indication code is added to each corrected word. 3. "Method according to item 1, characterized in that the first predetermined number is chosen smaller than the highest number of erroneous words that can be reliably corrected in the first decoder by using the error syndromes when the location of the erroneous words is known. 3 2 2 2 4 k £ 33.1982 59 543/13 4 ·. The method according to item 1, characterized in that the first predetermined number is selected to be the maximum number of erroneous words that can be reliably corrected in the first decoder by applying the error syndromes when the location of the erroneous words is known. 5. The method of item 1, characterized in that up to K words of the information words and first test words are corrected in the first decoder and, if the number of erroneous words within the number of information words and first test words is equal to or greater than K , all such Words receive an indication code to indicate an error. Method according to item 1, characterized in that up to K errors within the information words and first test words in the first encoder are corrected and a display code for indicating an error is added to each word thus corrected and, if the number of erroneous words within of the information words and first check words is greater than a number set smaller than K, all the information words and first check words are a display code for indicating an error. receive. The method of item 1, characterized in that first and second decoders are collectively capable of correcting, up to a maximum of K, word errors occurring in the information words and test words of all the second error correction blocks by calculating the error syndromes and therefrom the digits the 3 2 2 2 4 4 - * - 3.3.1982 59 543/13 erroneous words are obtained, but the error locations for "up to M words before error correction are determined for M <K, The method according to item 7, characterized in that in the second decoder, when the display codes are connected to the second error correction block, indicating the number of errors up to the predetermined number of not more than M, and the location of each erroneous word indicated thereby is considered correct , an error stream is calculated from the information words and first test words and the preselected number of error words is corrected by applying the location of the erroneous word and the error syndrome » 9. The method of item 7, characterized in that, if the number of erroneous words within the words of the second error correction block is greater than a predetermined threshold, the second decoder corrects the words indicated as being erroneous by the added display code. Method according to item 1, characterized in that a second predetermined number is chosen as the maximum number of erroneous words which can be reliably corrected in the second decoder by applying the error syndromes if the location of the erroneous words is known. 11, method according to item 1, characterized in that a second predetermined number is chosen to be smaller than the maximum number of erroneous words that are used in the second decoder by applying the error syndromes. 2 3 2 2 2 4 4 - ^ - 3.3.1982 59 5 ^ 3/13 can be corrected casually if the location of the erroneous words is known. The method according to item 1, characterized in that the number and the type of errors included in the second error correction block determines whether or not the second decoder performs error correction of the information words. . 13. A method for error correction, characterized in that a first error correction block is formed of a word contained in each of the data sequences of multiple channels in a first order state and a first check word for a word, wherein the data sequences of the multiple channels and first check word sequences by different Times are delayed in the respective channel to be converted into a second order state, and a second error correction block is formed of a word contained in each of the data sequences of the multiple channels and first check word sequences in the second order state, and a second check word for the latter one Word, wherein first and second error correction blocks are formed in accordance with the error correction codes, so that the error syndromes are calculated and errors up to K words included in the same block are corrected by obtaining the error locations from the error syndromes and a first decode is performed in a first decoder for the second error correction block of the transmitted data sequences and POM data sequences of the multiple channels and first check word sequences in the first order state through different times 2322244 59 54-3 / 13 in their respective channels to be converted to a first order state, and then a second decode is performed in a second decoder for the first error correction block and the error correction method consists of the following steps: Correcting errors up to a predetermined number of words in the second error correction block during the first decoding; - adding a display code for indicating an error in the word within a block when error words exceeding the predetermined number ^s are detected, indicating that all words in the block are unreliable and can be assumed to be erroneous, and Calculation of an error syndrome from a plurality of words contained in the first error correction block, and subsequently correction of the error words of a predetermined number, by obtaining the error locations on the basis of the error syndromes used in the second decoder. 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