DD154408A5 - CIRCUIT ARRANGEMENT FOR STORING INFORMATION IN DATA TRANSMISSION TECHNICAL SUBSCRIPTION POINTS - Google Patents

Abstract

1. Circuit arrangement for the storage of information in technical data-transmission subscriber stations, which comprises a data-word store unit (KE), a block store unit (BE) connected to its output and comprising a block store sub-unit (BT) with output connected as a feed-back to its own input, as well as a control and delay unit (VIE) connected to the data-word store unit and to the block store unit, characterized in that the data-word store unit (KE) comprises a first data-word store sub-unit (KT1) and a second data-word store sub-unit (KT2) connected in series, and in that there is provided a data-word store control sub-unit (KTV) which is connected to the first data-word store sub-unit (KT1) by way of a first decoder (D1) and to the second data-word store sub-unit (KT2) by way of a second decoder (D2).

Description

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Circuit arrangement for storing information in data transmission technology Subscriber points

Field of application of the invention:

The invention relates to a circuit arrangement for storing information in data transmission subscriber points.

Characteristic of the known technical solutions :

In the field of computer technology, the question of the possibility of transmitting information on recording and processing systems via telephone or telex channels is becoming more and more important. The most important assemblies of such systems are the subscriber points in the form of terminals or terminals, which are generally composed of a control unit, a character conversion unit and peripheral devices such as input and output devices for inputting and / or outputting the information.

A basic requirement for such systems is the error-free transmission of information between transmitter and receiver side. Given this principle, appropriate error protection must be provided in these systems, and upon discovery of an error, automatic character repetition must be requested. For error detection and data repetition 'the data transmitted must be stored for a certain period of time, and for the data transmission subscriber points therefore often a memory unit and an associated control unit are provided.

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The availability of such information storage circuits in conventional data transmission subscribers is severely limited by the following shortcomings.

1. Simultaneous reading in / out of the storage unit is impossible ": only after reading the memory completely can be read!

2. The characters can only be repeated after repeated reading into the memory!

3. There is no way to check, add, or delete memory read characters during the function.

Object of the invention:

The present invention aims at eliminating the above defect.

Explanation of the essence of the invention:

The invention has for its object to provide a circuit arrangement for storing information in Datenübertragungstechnischen SubscriberpunKten with which the information, apart from the functional life, substantially simultaneously and stored simultaneously and the characters without repeated reading any of reproduced, added or deleted and in the Can be checked during operation.

This object is achieved by a circuit arrangement for storing information in subscriber subscription points, comprising a character storage unit, a block storage unit connected to its output, and a storage unit having the character storage unit and the block storage unit.

Storage unit connected according to the invention a first character storage subgroup and a second character storage subgroup connected in series and the block storage unit has a block storage subgroup with an output coupled back to the input.

In an advantageous embodiment of the circuit arrangement according to the invention, the control and delay unit connected to the character storage unit and to the block storage unit is equipped with a character storage control subgroup and a dice storage control and delay subgroup.

In a further advantageous embodiment, the character storage control subgroup communicates with the first character storage subgroup via a first decoder and with the second character storage subgroup via a second decoder.

In a further advantageous embodiment, the parallel input of the first character memory subgroup is connected to the parallel information input of the character memory unit via a first combination circuit.

Another advantageous embodiment results from the fact that the parallel output of the second character storage subgroup is connected via a second combination circuit to the parallel information output of the block storage unit.

Advantageously, tier output of the block storage subgroup is connected to the serial input of the first character storage subgroup via a third combination circuit and a fourth combination circuit.

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It is also advantageous if the third combination circuit is connected to the series information output of the block storage unit via a fifth combination circuit located at an output of the third combination circuit.

In an advantageous embodiment, the input of the block memory subgroup is connected via a sixth constellation circuit and a seventh combination circuit to the series information input of the character memory unit.

In a further embodiment, the output of the second character storage subgroup is expediently fed back to its input via an eighth combination circuit.

Finally, advantageously, the first character storage subgroup is connected to the second character storage subgroup via the eighth combination circuit.

The basic advantage of the circuit arrangement according to the invention is that the input or output of the information is carried out practically simultaneously and independently of each other. The ability to control, repeat and delete during the traffic sign also means another advantage. The inven tion proper circuitry can be equipped to perform all combinations of serial and parallel input and output.

Embodiment:

In the following, the invention will be explained in detail with reference to a Ausführunysbeispiel the reference to the drawing.

The sole figure of the drawing shows a Blockschaltbi Id the circuit arrangement for information storage.

The exemplary embodiment of the information storage circuit has a character storage unit KE, a block storage unit BE and a control and delay unit VIE. The character storage unit KE has a Serieninformtionseingang IBs, a parallel information input IBp, a third input 11 and a first, second and third output 12, 13 and 14 and the block storage unit BE a serial information output IKs, a parallel information onsausgang 1Kb, a third output 24 and each have a first, second and third input 21, 22 and 23.

The character storage unit KE has a first character storage subgroup KT1 and a second character storage subset KT2; which are connected to each other in series. The first character memory subgroup KT1 has a serial input 31, a parallel input 32 and a serial output 33 and the second character memory subgroup KT2 has a serial input 41, a parallel output 42 and a serial output 43.

The parallel input 32 of the first character storage subgroup KT1 is connected via a first combination circuit K1 on the parallel in formation input IBp, the parallel output 42 of the second character memory subgroup KT2 via a second Kornbin tion circuit K2 the block storage unit BE to the parallel information output IKp.

The block storage unit BE has a block storage subgroup BT having an input 51 and an output 52. This output 52 is connected via a third combination circuit K3 with the third output 24 of the block storage unit BE in connection, the latter with the

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third input 11 of the character storage unit KE or via a fourth Kornbinationsschaltung K4 with the serial input 31 of the first Zeichenspeibheruntergruppe KTl is connected.

The output 52 of the block storage subgroup BT is also connected to the serial information output IKs of the block storage unit BE via the third combination circuit K3 and another fifth Kornbinationsschaltung K5 and fed back simultaneously via a Sese combination circuit K6 to the input Sl of the block storage subgroup BT. The series information input IBs of the character storage unit KE is via a seventh Kornbinationsschaltung K7, which is housed in the character storage unit KE, and the second output 13 of the character storage unit KEy the second input 22 of the block storage unit BE and the sixth combination circuit K6 also with the input 51 of the block storage subgroup BT connected. This is connected via the first output 12 of the character storage unit KE, the first input 21 of the block storage unit BE and the sixth Kornbinationsschaltung K6 and the serial output 43 of the second character storage subgroup KT2.

The serial input 41 of the second character memory subgroup KT2 is connected to the serial output 33 of the character memory subgroup KT1 via an eighth combination circuit K8.

The output 43 of the second character storage subgroup KT2 is fed back to its input 41 via the eighth combination circuit K8.

The control and delay unit VIE has a character storage control subgroup KTV and a block storage control and delay subset BTVI, which are interconnected with each other as well as with the subgroups and conventions

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are ion circuits of the character storage unit KE and the block storage unit BE in a known per se and therefore not described here in detail way.

Further, the character memory control unit KTV is connected to the first character memory subgroup KT1 and the second character memory subgroup KT2 via a first decoder D1 and a second decoder D2, respectively.

In three basic operating modes, the function of the information storage circuit shown by way of example is illustrated below:

1. Parallel information input - parallel information output (IBp - IKp);

2. Parallel Information Input - Serial Information Output (IBp - IKs);

3. Serial information input - parallel information output (IBs - IKp).

In operation IBp - IKp, the block storage control and delay subgroup BTVI via the character storage control subgroup KTV and this combination circuit K6 prohibits the operation of the block storage subgroup BT as well as the third, fourth, fifth and seventh combination circuits K3, K4, K5 and K7. The information (characters with a maximum length of eight bits) reaches the first character control subgroup KT1 via the parallel information input IBp and the first combining circuit K1 in a parallel manner (first clock). From the first character storage subgroup KT1, the information is passed through the character storage control

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group KTV determines via the eighth combination circuit K8 as standard in the second character control subgroup KT2 (second clock). The information output is made by the character memory control subgroup KTV via the second combination circuit K2 (third clock).

The cycle built up from bars 1 to 3 takes place again and again with each character. During the transmission of the information-containing characters, the contents of the character pairs in the first and second character memory subgroups KT1 and KT2 can be controlled via the first and second decoders D1 and D2, and accordingly, by changing the control signals during the transfer cycles. Control subgroup KTV the addition with any characters or the characters absorption possible.

In this mode of operation, the transfer cycle builds up as follows: Ißp-Kl-KTl ~ K8-KT2 ~ K2-IKp.

In the operation of ISp - IKs, the block storage control and delay subgroup BTVl prevents the operation of the second, fourth and seventh combination circuits K2, i <4 and K7 via the character storage control subgroup KTV. The first and the second clock of the transmission cycle are identical to those of the operation IBp - IKp. Then, however, the content of the second character memory subgroup KT2 (characters of up to eight bits) is fed via the sixth combining circuit K6 to the block memory subgroup BT, which enables the storage of two so-called information blocks with bits of specified number. The block lengths may be changed in the amount of capacity of the block storage group BT.

From the second character storage subset KT2, the information, i. the information bits in the block memory subgroup BT are recorded in the memory fields marked with ascending addresses designated by the block memory control and delay subgroup BTVI (e.g., the eight bits of the first character at addresses 0 to 7). After recording, the information circulates in the block storage subgroup BT at high speed in the feedback loop determined by the output 52, the combining circuit K6 and the input 52.

The reading of the bits of the following character is carried out as described above, only with the difference that the bits are now written to the following addresses of the block memory subgroup BT (for example to addresses 8 to 15). When loading the block memory subgroup BT, therefore, a double entry is made, namely the restoring of the previously read (circulating) information to the same addresses and the reading of the new information received from the second character memory subgroup KT2 to further (free) addresses.

The output of the information contained in the block memory subgroup BT is carried out bit by bit in an increasing order of the addresses, ie in the same order in which the input took place. The serial information outputs IKs are read during the circulation at the output of the. Block memory subgroup BT bits occurring via the third and the fifth combination circuits K3 and K5 supplied from the determined by the block memory control and delay subgroup BTVI addresses and in the time determined by this. The transfer of one bit to the third combination shutter i <3 occurs at a speed which coincides with the revolution speed, while the output of the fifth combination circuit K5 occurs at a much lower speed.

The information output from the block storage subgroup BT can be started immediately after the first character has been input, that is, it is unnecessary to wait for the padding of the block storage subgroup BT with blocks. The Rückspeürnerung (circulation) of the information also allows repeatedly output any block stored repeatedly. During the repeated cycle, the character input from the second character storage subgroup KT2 is surely prevented.

The content of the characters or character pairs located in the character memory subgroups KT1 and KT2 can also be monitored via the decoders D1 and D2 in this mode, and a supplementation or absorption can be carried out accordingly.

In this operation, the transmission cycle builds up as follows: IBp-Kl-KTl-K8-KT2-K6-BT-K3-K5-IKs.

In the operation IBs - IKp, the operation of the first and fifth combining circuits K1 and K5 is inhibited by the block memory control and delay subset BTVi via the character memory control subgroup KTV. The information is written bitwise via the serial information input IBs, the seventh and sixth combination circuits K7 and K6 into the block memory subgroup BT in the memory fields marked with the rising addresses determined by the block memory control and delay subgroup BTVI, until information in length of a block (fifth bar). Actuated by the control and delay signals of the block storage control and delay subgroup BTVI 'and the character storage control subgroup KTV, the information contained in the block storage subgroup BT is bit-serially and character-wise via the third and fourth combining circuits K3 and K4 into the

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first character memory subgroup KT1 loaded (sixth clock). From now on, the information is output according to the second and third clocks of the operation IBp-IKp. The transmission of the characters from the block memory subset BT to the parallel information output IKp continues until the time when the stored block is completely output.

The deletion of the block stored in the block memory subgroup BT is also possible by the instruction of the block memory control and delay subgroup BTVI.

In this operation, the contents of the characters or character pairs in the character storage subgroups KT1 and KT2 can also be monitored via the decoders D1 and D2, or additions or absorption can be made.

In this mode the transmission cycle builds up as follows: IBs-K7-K6-BT-Ks ~ K4-KTl ~ K8-KT2-K2-IKp.

Claims (10)

Eyf indun | ^ san spell; τ 1. Circuit arrangement for storing information in subscriber subscription points _? which comprises a "character storage unit, a block storage unit connected to its output, and a control and delay unit (VIE) connected to the character storage and block storage units, characterized in that the character storage unit (ICE) has a first character storage subset (KTi) and a second character storage subset (KT2) connected in series and the block storage unit (BE) has a block storage subgroup (BT) with an output coupled back to its own input. 2, circuit arrangement according to item 1, characterized in that the character memory unit (KE) and the block memory unit (VIE) are equipped with a character memory «control subgroup (KTV) and a block memory controller ™ and delay subgroup (BTVI) * - 3. The circuit according to item 2 _t, characterized in that the character storage control subgroup (KTV) having the first character storage subgroup (KT1) via a first decoder (D1) and the second character storage subgroup (KT2) via a second decoder (D2) Connection stands. 4 · Circuit arrangement according to point 1, _{characterized}} that the parallel input of the first character memory subset (CTI) via a first Kornbinationsschaltung (K1) with the parallel information input (IBP) of the character storage unit (ICE) is connected. - 13 - 225220 5 "circuit arrangement according to item 1, characterized in that the parallel output of the second character memory subgroup (KT2) is connected via a second combination circuit (K2) to the parallel information output of the block memory unit (BE), 6, circuit arrangement according to item 1, characterized in that the output of the block memory subgroup (BT) via a third combination circuit (K3) and a fourth combination circuit (K4) to the serial input of the first character storage subgroup (KT1) is connected. 7 circuit arrangement according to item 1, characterized in that the third combination circuit (K3) is connected to the series information output (IKc) of the block storage unit (BE) via a fifth combination circuit (K5) connected to an output of the third combination circuit (K3), 8, circuit arrangement according to item 1, characterized in that the input of the block memory subgroup (BT) via a sixth combination circuit (K6) and a seventh combination circuit (K7) to the series information input (IBs) of the character memory unit (KE) is connected. 9. Circuit arrangement according to item 1, characterized in that the output of the second character memory subgroup (KT2) is fed back to its own input via an eighth combination circuit (K8) « 10. Circuit arrangement according to item 1, characterized in that the first character memory subgroup (KT1) is connected to the second character memory subgroup (KT2) via an eighth combination circuit (K8).