DD152633A1 - CIRCUIT ARRANGEMENT FOR GENERATING ADJUSTABLE PULSE NUMBERS - Google Patents

Abstract

The invention relates to a circuit arrangement for generating adjustable pulse numbers, wherein a mother frequency and a default clock are switched to a programmable counting device. The aim is a circuit arrangement which allows for universal use for a particular application, a reduction of material and circuit complexity and a reduction in manufacturing costs. For this purpose, the adjustable pulse numbers from a low mother frequency, on the accuracy of which no special requirements are made, and generated from serving as a time standard preset clock and the preset clock without additional resources are provided. According to the invention, the mother frequency is connected to an input of a logic gate and the preset clock to the load input of a counting device whose Rückwärtswaertsuebertrag with the other input of the logic gate whose Rückwaertszaehleingang with the output of the logic gate and the signal input are connected to a preselector, wherein the Output of the logic gate is simultaneously the circuit output to which the adjustable pulse numbers are switched.

Description

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Title of the invention

Circuit arrangement for generating adjustable pulse numbers

Field of application of the invention

The invention relates to a circuit arrangement for generating adjustable pulse numbers, for example for generating digital setpoint pulses for desired-actual value comparators, wherein a mother frequency and serving as a time standard preset clock are switched to a programmable counter.

Characteristic of the known technical solutions

An arrangement for generating adjustable pulse numbers is already known, in which the adjustable pulse numbers serving as setpoints are produced by frequency division from a high-frequency master frequency, which is generated for this purpose in a quartz-stable pulse generator, and also a preset clock pulse obtained by frequency division of the mother frequency. The frequency division takes place in a programmable frequency divider, which is in connection with the quartz-stable pulse generator. The thus processed pulses are further supplied to a counter (Schröder, V / ·, Kramer, V., "Digital measurement of percentage deviations", radio, television, electronics 29, 1980, 2, p 113 ff). Quartz-stable pulse generators are used with high demands on the accuracy of the pulses, whereby the accuracy of quartz-stable pulse generators

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Increasing vibration frequency increases · Usually, the vibration frequency is in the range of several MHz. Purpose specific applications, it is necessary to generate adjustable pulse numbers from very low frequencies · This is not readily possible by means of the quartz-stable pulse generator · Apart from the additional effort required to quartz-stable pulse generators are expensive, a default of the programmable frequency divider used in this circuit to the each required division ratio is complicated and requires an additional computational effort. The division ratio of the process variable to be processed, which is to be represented by the adjustable pulse number, must first be calculated.

Object of the invention

The aim of the invention is a circuit arrangement for generating adjustable pulse numbers, which allows for universal use for a particular application area, a reduction of the material and circuit complexity and thus enables a reduction in manufacturing costs ·

Essence of the invention

The invention has for its object to develop a circuit arrangement for generating adjustable pulse numbers, in which the adjustable pulse numbers from a low mother frequency at the accuracy of which no special requirements are made, and are generated from serving as a time standard preset clock. In this case, the preset clock should be provided without additional funds from already existing timers.

According to the invention the object is achieved in that the mother frequency, preferably the mains frequency, to a

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Input of a logic gate and the default clock is connected to the load input of a counter whose backward sübertrag with the other input of the logic gate, backward counter input input to the output of the logic gate and whose signal inputs are connected to a preselector, wherein the output of the logic gate at the same time is the output of the circuit arrangement to which the adjustable pulse numbers are switched.

A frequency divider may be connected in front of the input of the logic gate, to which the mother frequency is applied, and between the output of the logic gate and the circuit output.

It is also possible that the preset clock is connected to an input of an additional logic gate whose other input is connected to a means for pulse generation and whose output is connected to the charging input of the counter.

embodiment

The invention will be explained in more detail with reference to an exemplary embodiment. In the accompanying drawing, a circuit arrangement for generating adjustable setpoint pulses for a Mengeriüberwachungseinrichtung is shown.

As the drawing shows, the output of a low-frequency mother frequency generating device 1, which uses the heart rate in the present example, connected via a frequency divider 2 to an input of a logic gate whose output is connected to a counter 4. The output of the logic gate 3 is connected to a further frequency divider 5 whose output is at the same time the output of the circuit arrangement at which the setpoint pulses are present. In the present example, the logic gate 3 used was a ШГО gate, on the second input of which the reverse transmission of the counting

device 4 is switched on. On the charging input of the counter 4 is a serving as a time standard preset clock a minute timer 6 and the signal inputs of the counter 4 corresponding outputs of a preselector 7 are switched ·.

The method of the solution according to the invention will be described below.

With each preset clock (e.g., minute pulse of the minute timer 6) serving as a time standard, the counter 4 is charged to the value preset by the preselector 7. As a pre-selection device 7, for example, serve a decade switch. The logic gate 3, which is connected as an AND gate, switches the pulses of the master frequency to the output of the circuit arrangement until the number thereof has reached the value preset by the preselector 7. Thereafter, the AND gate is disabled by the carry back of the counter 4 until the arrival of the next preset clock.

Claims (3)

, 5_ 223 1 75 Claim for invention 1. Circuit arrangement for generating adjustable pulse numbers, for example for generating setpoint pulses for setpoint-actual comparison devices, wherein a mother frequency and a default clock are switched to a programmable counter, characterized in that the mother frequency, preferably the mains frequency, to an input of a logic gate (3) and the default clock is connected to the load input of a counter (4), whose reverse carry over to the other input of the logic gate (3), the reverse szähleringang with the output of the logic gate (3) and their signal inputs with a preselector ( 7), the output of the logic gate (3) being at the same time the circuit output to which the adjustable pulse numbers are applied. 2. Circuit arrangement according to item 1, characterized in that in front of the input of the logic gate (3) »is switched to the mother frequency, and between the output of the logic gate (3) and the circuit output, a frequency divider (2 or 5) is. 3 · Circuit arrangement according to item 1, characterized in that the preset clock is connected to an input of an additional logic gate whose other input is connected to a means for generating pulses and whose output is connected to the charging input of the counter (4). For this 1 sheet drawings