DD151247A1 - SYNCHRONOUS RECTIFIER WITH FIELD EFFECT TRANSISTORS - Google Patents

Abstract

The invention can be used as a phase-sensitive rectifier in the news, Mesz- and control technology. It is the object of the invention to reduce the complexity of a synchronous rectifier with field effect transistors. The object is to provide a circuit arrangement which allows an increase in the output voltage without exceeding the limits of the field effect transistors and thus avoids a Nachverstaerkung necessary in many cases. According to the invention, the object of a synchronous rectifier having FETs of the same conductivity type, in which the input voltage is applied between a first input and a second input and not connected to the output potential, is achieved by connecting the bulk terminals of the field effect transistors of a bridge circuit and a respective terminal two clock voltage sources are connected to the output of an extreme value circuit.

Description

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Title of the invention;

Synchronous rectifier with field effect transistors

Field of application of the invention

The invention relates to a synchronous rectifier with field effect transistors. He comes as a phase-sensitive rectifier in communications, measurement and control technology for use, for example, as a demodulator in Gleichspannungsbzw. DC chopper amplifiers.

Characteristic of the known technical solutions

The starting point of the invention is the known FET bridge circuit, as it is used as a chopper or synchronous rectifier. Especially when used as a demodulator in chopper amplifiers of the measurement, control and Hegelungstechnik whose input and output voltages is limited so much by the allowable limits of the FEiDs that a DC amplifier must be connected downstream to the standard level of the control system (eg + 10 V). On the one hand, this increases the effort and, on the other hand, brings with it the offset voltage and the drift of the downstream amplifier as a result of deterioration of the technical characteristics of the entire measuring amplifier. In known synchronous rectifiers with FETs, the output voltage is particularly limited by the maximum permissible value of the source-bulk voltage and the requirement that the pn junction between the bulk and the channel (source, drain) not in Durchlaß-

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direction to operate; See radio-television-electronics 27 (1978) H.1 S. 765-766 "Phase-sensitive rectifier as a precision rectifier" ¹ , E, Altmann. The p-channel MOSFETs are operated here with a fixed positive Б ulk ν or voltage · If an equal level control with positive and negative voltages is required, the possible output voltage in one polarity is limited to half the allowable source-bulk voltage ·

Object of the invention

It is an object of the invention to reduce the effort in a synchronous rectifier with field effect transistors,

Explanation of the essence of the invention

It is an object of the invention to provide a circuit arrangement for a synchronous rectifier with field-effect transistors, which allows an increase in the output voltage without exceeding the limit values of the FETs and thus avoids a post-amplification which is necessary in many cases.

According to the invention, the object of a synchronous rectifier with FETs of the same conductivity type, in which the Eingangspannimg applied between a first input and a second input and is not connected to the output potential, achieved in that the BUlkanschlüsse the field effect transistors of a bridge circuit and one terminal two clock voltage sources are connected to the output of an extreme value circuit «

The second terminal of the clock voltage sources is connected to the gate terminals of the field effect transistors of the bridge circuit.

The two inputs of the extreme value circuit are connected to the two inputs of the synchronous rectifier ·

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Export example

The invention will be explained below with reference to an embodiment, Fig. 2 shows a possible implementation of the invention with I ¹ ETs of the P-channel enhancement type. The circuit arrangement has the two inputs 4 and 5, the output terminal 3 and the terminal 6 for the reference potential of the output * The input voltage is between the inputs 4; 5, but is not related to the potential of the output. Four FETs are connected together to form a demodulator bridge 1 which is controlled by two equal-frequency, but opposite-phase, clock voltage sources 10 and 12. The BUlkanschlüsse all FETs are connected via a resistor 11 to a common terminal of both clock voltage sources and to the output 17 of an extreme value circuit 2. The inputs 18, 19 of the extreme value circuit are connected to the inputs of the synchronous rectifier 4; 5 connected · The extreme value circuit here is a maximum circuit and consists in the simplest case on the input side of two diodes 7; 8 low flux voltage whose cathodes are connected on the output side and are connected via a resistor 9 to the reference potential 6 of the output. The resistor 11 limited in case of failure, the current through the Bulkanschluß and thus protects the relevant FET, the resistors 15 »16 between the clock voltage sources 10; 12 and the gate terminals of the FETs limit the current in the event of a fault via possibly existing gate protection diodes of the FSTs.

Since as a rule the rise or fall time of the output signal is substantially greater than the period of the modulation clock or the clock frequency, a capacitor 14 is connected between the output 3 and the reference potential 6 of the output, the unwanted spikes at the output when switching the demodulator (and modulator) avoids. It is further desirable to connect between the output terminal

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the extreme value circuit 2 and the reference potential of the output to connect a capacitor 13, which avoids unwanted voltage peaks at the BUlkanschlüssen by switching the modulator and the signal delay of the generally connected between the modulator and demodulator AC voltage amplifier or the transmission line.

The increased controllability of the described synchronous rectifier with FETs is achieved in that the bulk potential is not fixed, but is carried by the voltage at the inputs. The bulk potential adapts to the highest positive voltage value of both inputs and drops to zero when the input voltage is negative. By this measure, the full allowable value of the source-bulk voltage can be exploited in both polarities of the output · The possible output voltage is thus about twice the possible output voltage at a fixed bulk potential and in many cases can be dispensed with an amplification.

Further implementations, in particular with other types of FETs or with differently constructed extreme value circuits, are possible. If FETs are used without lead-out, the connection of the bulk connections with the output of the extreme-value circuit, which is then connected to the two clock voltage sources, is omitted.

Claims (1)

- 5 - 22 1500 ¹ Invention sanction Synchronous rectifier having bridge-type connectivity type field effect transistors (1), in which the input voltage is applied between a first input (4) and a second input (5) and is not connected to the output potential (3; 6), two antiphase clock sources ( 10, 12) and an extreme value circuit (2), characterized in that the bulk terminals of the field effect transistors and one terminal of the clock voltage sources (10; 12) are connected to the output (17) of the extreme value circuit (2) and the second terminal of the clock voltage sources (10; 12) is connected to the gate terminals of the field effect transistors and the inputs (18; 19) of the extreme value circuit (2) are connected to the inputs (4; 5) of the synchronous rectifier. For this 1 page drawings