CS363691A3 - Tape cassette, particularly a cassette with a magnetic tape - Google Patents

Description

JUDr.Ivan HOREČEK

Attorneys at Law Office Žitná 2511Ů04 Praha 1

Digital Transmitter Receiver Receiver.

Technical field.

BACKGROUND OF THE INVENTION The present invention relates to a receiver for a digital transmission system comprising a transmission channel having a storage depth n for processing an analog signal, the receiver comprising an analog-to-digital converter and an equalizer for digital signal processing, including a memory storage means for storing state transitions.

State of the art.

Such receivers are needed for a future pan-European mobile radio system (GSM system). In this mobile radio system, speech signals are transmitted in digitalized form, along with other digital signals of the time division multiple access sub-pattern. This datase transmits an auxiliary modulation by the transmitter of the mobile radio system as a result of the reflections and the multi-track transmission path propagation reaches the transmitter signal in various superimposed signal portions exhibiting different delays and phase shifts. This distorts the transmitter signal. These distortions cause the bits contained in the received signal to be affected by previous bits (inter-symbol interference). Between the transmitter and the receiver there is a transmission channel having a storage depth 'n, where n is an integer and denotes the number of interfering neighboring bits. Recovering the original data content in the signal requires correction of the received signal. DE-A 39 11 999 discloses a receiver for a digital transmission system of the type mentioned above. The receiver includes a equalizer for generating binary estimates based on the signal sequence value. Each sample value may be assigned in time to the transmitted bit having a binary value of "0" or "1" and depends on that bit and also on the n immediately preceding bits. The equalization correction is then carried out with the aid of a so-called Viterbi algorithm. According to this algorithm, the 2n states and the probability parameter are assigned to each transition from one state-of-the-time state to each sample value. By concatenating these states, the secel probabilistic probability parameters create paths and create a separameter for all one path. Of all the paths leading to one state, only the path having the lowest overall probability is taken into account. The transition from the state-defined bits bi_i ... bi_n at the discrete moment i with the binary value b 1 = 0 (= transition "0") to the next state determined by bits b 1 ... bi-nx at the time i + 1 determines the so-called binary paths binary the value of bx _ "= l (= transition" 1 ") of the so-called one-way track. From the total probabilistic parameters of all possible zero paths and from the total probability parameters of all possible one kites, the smallest total probability parameter is always chosen. The path defined by the bit sequence bx, ..., bx_ "for b 1" = 0 and b. bx _ "= 1a having the smallest total probability parameter of all 2" possible zero or one lanes characterizes the corresponding minimum zero or one lane. The binary number, ie, zero or one, assigned to the smaller of the two selected total probability parameters gives an estimate, whereas the reliability of this estimate is based on the two selected Reliability information is estimated in the following decoder decoder in the system: The cost of implementing the equalizer is first approximated to the number of states 2 ", ie, exponentially increasing with the storage depth n of the transmission channel.

Characteristics of the invention.

SUMMARY OF THE INVENTION It is an object of the invention to provide a receiver of the type mentioned above with reduced production costs. _ about _

This object is achieved by a receiver of the type mentioned above, in which the memory means registers comprise all 2 ' memory locations where the memory means comprises a memory path register in which at least n previous bits starting at a suitable previous location are stored at each discrete moment. bit for 2 "'states.

The signal received by the receiver has the behavior of an analog signal as a result of superimposing adjacent bits corresponding to the storage depth n of the transmission channel. As a result, the received signal is first sampled in the processing section of the analog signal. The sample values thus obtained are converted by an analog-to-digital converter and further processed by an equalizer. The receiver equalizer is then based on the reduced state model s2n 'states where l £ N £ n'. For a reduced number of equalizer, only n * bits are determined directly by the state transition. The remaining n-n 'bits appear on the memory path leading to the corresponding state, which is stored in the memory track register. This is advantageous in that only a 2 "" state must be processed at each sampling time, as opposed to an equalizer that takes into account all 2 "states. This coarse approximation results in a cost reduction of 2" / 2 "'.

A low-cost bit estimate is created by including equalization control and arithmetic logic to create probabilistic parameters for the n '+ lbit-based state transition representing this state transition and stored memory resource and n-n' bits of the memory path register, generates a corresponding minimum zero path and a minimum one path, and creates reasonable probabilistic parameters, whereby the sorting and arithmetic logic decides that the binary value assigned to the smaller of the two probability parameters considered is an estimate for bá.-r., and that control and arithmetic logic produces reliability information against the estimate on the basis of the two overall rules of consideration, which are considered to be of a kind. The arithmetic logic ensures, even v-, nzen: the creation of probability parameters and overall probabilistic parameters, as well as the correction based on the Viterbi method, as described, for example, in DE-A 39 11 999.

According to one embodiment of the receiver according to the invention, the memory track register has a storage depth M of the previous bits, where M> n, wherein at the time i the estimate bx.N is taken from the minimum path path of the memory path register for the bit bx_N, when '<N iM, if the overall probability parameter mi the non-zero zero path is less than the total probability parameter of the minimum one path, otherwise from the minimum one path, whereby the timing of the estimate of bi_N to estimate the reliability of the estimate assigned to the bitubi-n is obtained when the reliability information oN-n 'time is delayed intervals. This estimate, obtained from the memory position further back at the time of the memory path, shows greater reliability than the estimates obtained from the "shorter" memory path register. In another embodiment, the memory path register has a storage depth M of the previous bits where M * n, whereby at the moment i the reliability information for the bi_N bit is created, where n '<N <M and the reliability information is replaced by a predetermined substitute if they exist at the moment i either only zero tracks or only one tracks. This achieves that the equalizer continues to operate with an appropriate replacement value in cases where it is not possible to derive an accurate reliability information for the bx_N bit. In another embodiment of the invention, the reliability information is the ratio between the probability values of the two-selected lanes. This ratio between probability values then expresses how many times the estimate is more likely than the additional value of that estimate. In another embodiment of the invention, the square-to-point probability of transition between two states is used as a specific and specific value of the probability parameter created for the state transition is added to the overall measurement value determined to date to create an overall probability parameter. The possibility of using the so-called negative logarithm instead of the probabilistic parameter values resulting from each probability parameter is then used. This is advantageous in that the specific value only has to be summed together to calculate the total probability, while the individual probability parameters must be multiplied. In a further embodiment of the invention, the total value of the absolute zero path is subtracted from the total specific value of the minimum one path, with the difference sign indicating the estimate and the absolute difference value indicating the reliability information associated with this estimate. A positive sign indicates that "1" is more likely than an estimate than "0". In another embodiment of the invention, the curvature is corrected by a power dependent value. With such weighted information, it is possible to use the data elements of the received signal for further processing, which provide optimum safety for the erroneous estimate. In a further embodiment of the invention, the information signals to be transmitted are coded into bits by a convolutional encoder in the transmitting end, wherein the decoder working as a convolutional decoder is arranged downstream of the decoder after decoding the bits, but also the information to the reliability reliability will be the equalizer in that system, processes not only the estimated reliability assigned to these bits. In this way, the likelihood that a truly transmitted data sequence is obtained after decoding is increased because the decoder also contains information about how individual bits can be "trusted" more and less "trust". BRIEF DESCRIPTION OF THE DRAWINGS.

The invention is explained in more detail in the following description of the present invention, which shows the transmission system, the equalizer and FIG.

FIG. 2 is a block diagram of a numerical diagram of a digital system, a digital system, and a schematic of a transmission system. flow diagrams of an example example

Embodiments of the Invention.

Fig. 1 illustrates a radio transmission system in which information signals are transmitted in the form of a binary signal through a transmitter 2 between the transmitter JL and the receiver formed by the signal receiver. A transmission channel 11, formed as a radio link indicated by an arrow, is provided by the sampling and holding member 21, the analog-to-digital converter 22 and the equalizer 2. The receiver 2 is followed in the system by a sampling and holding member 21 as well as by an analog-to-digital converter 22. The signals at the digital output of the analog-to-digital converter 22 are routed to the equalizer 2. The equalizer 3 includes a digital signal processing section including a signal estimator 32, a control circuit 34. , cross filter 21. ' the memory means 33 also referred to as a memory module in the following description, as well as the control and arithmetic logic 35. The memory means 33 comprises registers 331, 332, 333 and register 334 of the memory.

W A track. The control and arithmetic logic 35 generates the estimate b as well as the reliability information 1 b for this estimate b. The transmitted signal is distorted in the radio link by the transceiver 2 and the receiver 2 as a result of the multi-threshold propagation due to the reflections and the superimposed noise signal and other interfering signals, as 1 is a dashed arrow of a radio link. As a result, bit bx of binary signal b transmitted at discrete time i is superimposed with delayed portions of previously transmitted bits b1b b2_2, ...... This superposition corresponds to signal distortion. As a result, the received bit for the transmitted bit can no longer be unambiguously assigned to a low or high level. The transmission channel 11 so that ν has a storage depth π where n is the number of interfering adjacent bits. The storage depth n may also be defined as the coefficient of the response length to the channel pulse of the transmission channel 11 and the duration of the received signal, minus 1, taking the largest integer from that result. As a result of these superpositions, the signal received from receiver 2 has an analog signal deflection that cannot be allocated to the originally transmitted bit without equalization. The signal received by the receiver 2 is first sampled by the sampling and holding member 21 at equal distances. Analog samples. thus obtained are converted to digital sample values, determined for further processing by the analog-to-digital converter.

The effect of the already transmitted bits depends on the delay of the signal portions coming from the receiver. After a certain period of time, depending on the characteristic character of the transmission channel, the effect is no longer relevant and may not be taken into account for correction (equalization). As a delay rule, it expresses as the number of bits transmitted in this time period. For Equalizer 3, each sample value zx that can be assigned to bit b + transmitted in time i depends on bit bi which can be assigned to this sample value and on bits b1_1, bi_2, · bx_n which preceded this bit.

The signal correction from the analog-to-digital converter output is based on a channel model approximately describing the diffusion transmission channel 11 of the transmission system using a linearly finalized filter. For such a channel model, the transmission property of the transmission channel is simulated by the filter coefficients ho ..... hn. Therefore, at the receiver end, efforts are made with this specific channel model to simulate the distortion occurring on the transmission path by the transverse filter 31 which are caused by memory-containing linear combinations. Transmission path simulation is achieved by adequately adjusting the filter coefficients iiCt in the radio cross arm n-3. The filter coefficients ho, ..., h3 are then derived from the sample values of the estimated transmission channel impulse response. For example, a so-called test sequence comprising a bit sequence known to both transmitter 1 and receiver 2 may be used. Each time a test result is received, the filter coefficients h0, h3 are set so that the transverse filter passage 31 simulates the transmission channel having the least errors. This is known, for example, from DE 40 Ol 592 A1. In the exemplary embodiment shown in FIG. 1, the filter coefficient generating device is not shown. The equalizer shown in FIG. 1 is based on the so-called Viterbi method as described, for example, in EP 0 294 116 A2. The Viterbi cotak method is known, for example, from Gavid Forney Jr.'s article: TheViterbi Algorithm ", Proceedings of the IEEE, vol.61, no.3, March 1973. According to this algorithm, so-called soft decision decoding requires data elements to be decoded from a sequence of encoded data, the reliability information for the data sequence to be decoded. The reliability information is a probabilistic parameter with which probability the data to be decoded corresponds to the transmitted data elements. As a rule, the ~ ~ parameter can be used to represent a diagram as shown in FIGS

Viterbi method state. Instead of probability, so-called specific values, which can be calculated from a negative logarithm of each probability parameter. This is advantageous, for example, in that the specific values need only be added together to calculate the overall probability, while the individual probability parameters need to be multiplied.

To calculate the probability of transition from one state to another, the individual binary values of the bits are used as input parameters for the transverse filter 31. The output value of the transverse filter 31 forms a first approximated value, whereby interference or noise signals are eliminated. contained in what input signal the sample should assume when used as an input parameter is a value, the bit is transmitted or received over a radio link. By comparing the output value of the drop filter 31 to the actual sample value, it is possible to find the most likely transmitted sequence.

The high probability of switching from one state to another does not yet provide sufficient assurance for this transition, as the most probable transition is a random state transition that has not taken place, due to short disturbances or signal noise. More accurate estimates of state transitions are made by taking into account all signal transgressions so far, by probabilistic investigation of all state transitions that lead to one 2 "states at a given time. i.e they rise exponentially with the storage depth of the transfer channel.

J3 shown in Figure 1, where 1 <η '<η. IN

Alternatively, the equalizer is based on the 2 '' state model of the exemplary embodiment shown in FIG. 1 is n = 3 and n '= 2. It constitutes a reduction of the number of states 2 "' = 4, to the equalizer with the full number of states 2" = 8. Difference from Equalizer with the full number of states2 &quot; is that only n * bits bA ......, bA_n are determined in the equalizer with reduced number of states 2 &quot; The remaining n-b 'b1_n_1, ... appears from the memory path leading to the SA state, which is stored in register 334 of the memory path memory path 33. as opposed to a full-number equalizer, the memory path register 334 is used for the soft-decision equalizer with a reduced number of states. In this register 334, it is necessary to store at least 334 n. the preceding bits bA-1, ..., b-n ', bA' ', x, ... bi-n' ... must be stored at each time i from the bit bA_x for all 2 n 'states SA. Bitybi_i, ..., bA_ ". they do not necessarily have to be stored in register 334 1 by the memory path bits because they are identical to the respective state S ^, ..

To produce a specific value in the exemplary embodiment shown in FIG. the transverse filter 31 subtracted from the digital sample value from the x signal estimators 32 and squared. This way, a quadruple distance is created. The probability that the received signal value is derived from the bit sequence used as the input parameter is greater the smaller the raised distance. However, due to the linear combination of n last digits, the optimum cannot be achieved until n bits are received. Λ

Odhad bi. assigned to the sample value z * is assigned at one time to the state transitions from one s-flux Ss. to states S1Tl in i + 1.

To carry out the method, the memory module 33 shown in the exemplary embodiment shown in FIG. 1 comprises registers 331,332,333 of measurement values as well as the memory track register 334. Each register contains 2 "'memory positions, with three bits ax ... a3 being used for addressing the columns as described below. Each memory position of the registers is then assigned a single address ai ..... a3. The total specific value assigned to one state is stored in the first register 331. A new total specific value is stored in the second register 332 at the address ax ... a3, which was created by the transition "O", the so-called "O" -drags ( zero paths), while the third register 333 stores the total specific value created by the transition "1", ie, the so-called "1" -paths (one-way paths). With state transition from S *. determined by the bits at time i with the bit b 1 "= 0 (= transition" 0 ") to the next state

The so-called null paths are determined at the point i + 1, and so-called one-way paths with the number bi1 = 1 (= transition " 1 ") are determined. In addition, at least n of the previous bits are stored in the memory path register 334 for all 2 &quot;, ie, four states in the exemplary embodiment of FIG. 1. When the memory position is excited, the current address is at the same time; transverse filter 31 is an input parameter '. For each available first input parameter v

the control circuit as the first binary number, for example "0". FROM

And this value from the transverse filter 31, thus determined and the sample value z, is made in the estimator 32 to form a square distance (z-z) 2. From the square of the distance and the total specific value stored in the first register 331 of the specific value at the appropriate address, a new total specific value is created, which is stored in the second register 332 of the specific value at a suitable address. In a similar manner, a second binary number, for example, "1", is available for the first input parameter, and the total specific value obtained in that way is stored in the third register of the specific value. Once the control circuit 34 has passed through all the address combinations and all the contents of the second and third track registers 332,333 have been recalculated, the smallest values of all the new total measurement values of the second and third register 332,333 are measured, these two values are subtracted from each other. Finally, the sign of the difference indicates the estimate and the absolute difference value of the desired information

And the reliability of P (b) for bit b ^ - ^. Once determined

And estimate b, the update is performed, i.e. the content of the registers of the first path to the third path 331, ... 333 and the measurement values stored in the memory path register 334 are updated.

For this operation, the control and arithmetic logic 35 also provides the equalization or correction logic, the overall control, the generation of the overall measurement values, and the implementation of the Viterbi algorithm. This is done in a known manner, for example from DE-A 39 11 999. Subsequently, the arrival of a new sample value is expected and an associated new estimate and associated reliability information is generated in the manner described above. In the exemplary embodiment shown in Fig. 1, the following steps are performed: 1. Call LiCbi-i, ...., bi-".) = Li (Si) of register 331 2. Call (bi-^ ... .., bi_ ") from register 334 for path 12- (b.-χ,

L1Tl (With Where

A Z;

2-vaO -v (+ 1, -1 • · * 1 1 i - n '), S 3. r X) Lj_ ^ x (foj., Bji__ X, xhv-, káe

(t-M

If b ^ -n-O, save Ladrese (bx, bx_x, ..... b ± _

If bx_n. = L, store L,, SiTl ·) in register 332 on, Sirl.) In register 333 on

x (S.x) x (S address (bx, .bx_i, ..... b ^ - ^. ^ x)

Find the minimum for the LiTl zero paths from register 332

Look for the minimum "1" L1Tl measurement values from register 333

A A

Specify P (bx_n.) And bx_n. for minima (6. and 7.) 6. 7. 8. 9. Update registers 331 and 334.

Here, the symbol L represents the total specific values characterized by individual state transitions.

2 is a diagram having columns of 2n nodes. each node re-represents one of the combinations that can be made of n bits. Each column is assigned to a sampling time i-3, i-2, i-1, i, i + 1. The individual binary values 000 ... 111 that can be assigned to a node are node states. The condition always corresponds to the fact that n the last sample values received in the time i can be assigned to the bit sequence that could be transmitted. If a null sample value is received, then both zero and one bit can be assigned. The bit-bit sequence 0010, when it was last assigned to the binary value "0. Because it does not affect the correction because a new sample value is received, this binary value is omitted. The embedded diagram shown in FIG. it reaches the node y to which the state Sx ^ x = 00l is assigned at the moment i + 1, through the transition "1" the node z is assigned to the state Sx = 10l in the moment i + 1. This path has the same meaning as the reconstructed bit sequence bx, ......, bi_n. A 39 11 999 shows that the production cost of a correction equalizer based on a set of states 2n is high.

Fig. 3 shows a state diagram for the equalizer shown in Fig. 1, which is based on a state model with only 2 &quot; states where 2 " = 4. When comparing the state diagram shown in FIG. 2 with the state diagram shown in FIG. 3, the cost of production relative to the state model with 2 &quot; states will be understood. In addition, all possible paths are shown in FIG. 3 (state grid) in the state diagram. the so-called zero paths are determined by a state transition from the SA state determined by the bx-i ..... bi. bits at the time jL having the bit bx_n. = 0 (= "0" - transition) to a time-consecutive state of SiTi determined by bits bi bx_n. ^ x at the time i + 1, and likewise the so-called one-way with bitembe_n. = 1 (= "1" - transition). In the state grid shown in Figure 3, we used in accordance with the examples used for the description.r nl = 2. In the state grid shown in Fig. 3, the state transition is δχ., Δχ ^ χ. marked with bits b ^ b ^ -χ, bi_2. The bitbx_3 indicating the state of Network1 may be called from the memory path register at time i from position i-3.

Fig. 4 shows a state diagram in which only paths for which all transitions from instant i-2 to i-1 were transitions "O", i.e. for which the binary number "O" has been assigned to bit bx_2, are shown. This corresponds to the zero thresholds for the state transition δχ., Δχ ^ χ. Probability parameters 11, 10, Ol, 00 are calculated on the basis of the states 2n '= 4 for the values of the exemplary embodiment n3, n' = 2. Only n '+ l = 3 bits bi, bi_i, bi_2 are then determined by the state transition δχ., Δ ^ χ, while the remaining n-n '= l bit bx_3 results from the memory path leading to the δχ state. For this reason, contrary to the so-called soft decision equalizer with full number of states, the register of the memory path in which it is stored at for each state and for all 2 '' states, the memory path bi-x, ....., bi. "', bt-1, ._i, ... rbi_n ,. ... along the length of at least n bits counted from bit bx_x, bitybi-i, ...., bx_n may also be omitted for this purpose. -1- state S, ... because they are actually identical to the bits

Fig. 7 shows a state grid in which only all one paths are shown for the state of the network, the network. Here, the binary number "1" is assigned to each bit bx_j. Establishing the estimate and reliability information is a minimum total specific value of all total resolutions of the states resulting from the " 0 " transition and of all the overall values resulting from the " 1 " the path having the smallest overall value is selected from the state diagrams shown in FIGS. 4 and 5. These paths form the corresponding minimum zero path and the minimum one path. Each of the two selected minimum total values expresses the probability with which the selected path can ideally be assigned to the estimate = n or the estimate of bi._n. = 1. These probabilistic values can be calculated from the total specific values. In the last step, both the overall probability parameters available for each state of Sx ^ i are mutually aligned and the smaller overall probability parameter is assigned to each SiTi state as a new probability parameter. It is also possible to create maxima instead of minima using inverse measurement values.

Fig. 6 shows another exemplary embodiment of a digital transmission system. The information signal x to be transmitted is first fed to the convolutional encoder 54. The convolutional encoder 5 produces a binary signal b, which is transmitted through the scattering transmission channel 1. The receiving end is a receiver 2 which generates a sampling signal z. This sampling signal z is fed to the equalizer 2. The equalizer produces estimates 1 as well as the corresponding reliability information P (b). Estimates as well as reliability information are routed to the decoder (5 which decodes the x sequence). The Viterbi process decoder is used for this decoding.

For Viterbi decoding, the received coded signal sequence is compared to any valid code sequence that the encoder would use the number-coded 5 could generate. For Viterbihc, decode in which individual code elements of stored codes are corrected.

When the specific value obtained by this method of reliability information is multiplied, an estimate of the data sequence to be decoded is obtained. In this way, the likelihood that the originally transmitted data sequence is indeed then used for encoding but is obtained after decoding is supported. The signal redundancy decoder 6 may be " trusted " less or " trusted " less for the purpose of indicating which individual bits of the data to be decoded. not only the sequence,

Claims (10)

REPRESENTATIVE J-16- PATENT REQUIREMENTS OF THE PRODUCT (33) l <n '<n, A receiver for a digital transmission system comprising a transmission channel having a storage depth n with an analog signal processing section, the receiver comprising an analogue-to-digital converter and an equalizer having a digital signal processing section including a memory transient storage means, characterized in that the registers (331,332,333) of the memory comprise all 2 &quot; memory locations, the spam means (33) having a memory path register (334) in which at least n previous bits (bA_i, ....., bA_) are stored at each discrete moment (i). "........................), Beginning with the appropriate previous bit (bi_i) for 2" states. 2. A receiver as claimed in claim 1, wherein the equalizer (3) comprises control and arithmetic logic (35) that make the probability parameters for the state transition (Si., Siri) based on n '+ 1 bits (bA, .... bA_). "...") representing the state transition and stored in the memory means (33) and based on the nn * bits (bA_n._A, ... bA_ ") of the memory path register (334), the control and arithmetic logic generating a corresponding minimum zero the path and minimum one-way path based on bit sequences (bA, bA → A, ... bA_n ·, bA_ · ·) of all possible zero paths and one-way paths, and generates overall probability parameters, with the control arithmetic logic deciding that the binary value assigned to the smaller of the two total probability parameters considered is the estimate (ί) ± .η) for the bA_n bit, and the control and arithmetic logic generate A osti reliability information (P [bA _ ”. ) for this estimate (bA_ ".) based on the two total probability parameters considered. Receiver according to claim 1 or 2, characterized in that the memory path register (334) has a storage depth of M previous bits, where M> n, wherein at time i. The estimate (b ^ -K ^ is taken from the minimum '1 zero path of the register ( 334) a memory path 17 for the bit bi-j, s n '<N <M, if the total probability parameter of the minimum zero path is less than the total probability parameter of the minimum one path, otherwise from the minimum one path, with the time assignment estimate Íbi_N) the reliability of the assigned bit estimate (bi._n-) is obtained when the N-n 'time interval reliability information is delayed, Receiver according to any one of claims 1 to 3, characterized in that the memory path register (334) has a storage depth M of the previous bits, where Min, at the moment i, the information (P [bi_N]) of the reliability for the bit (ύ ^ Where n '<N £ M and reliability information (P [bi_N]) is replaced by a predetermined substitute value if there are only zero paths with bx_N = O or just one paths with bi._N = l. A receiver according to any one of claims 1 to 4, characterized in that the reliability information is generated in proportion to the probability values of the two selected doubles. A receiver as claimed in any one of claims 1 to 5, characterized in that a square of probability of transition between two states is used as a measure of the probability parameter and a specific value generated by the transition is added to the total specific value determined up to now to form the overall probability parameter. Receiver according to any one of claims 1 to 6, characterized in that the total minimum zero-path value is subtracted from the total minimum one-way value and the difference sign indicates the estimate and the absolute difference value indicates the reliability information assigned to the tom-point. A receiver according to any one of claims 1 to 7, wherein the reliability information is corrected by a value independent of the determined noise power. Receiver according to any one of claims 1 to 7, wherein the information signals (x) to be transmitted are coded into (b) bits by a convolutional encoder (S) by the sending end, characterized in that the decoder (6) working as convolutionary the decoder (6) is arranged downstream of the equalizer (3) in the system, wherein the decoder, after decoding, processes not only the estimated bits (b) but also the reliability information (P [b1] assigned to these bits). A digital transmission system comprising a receiver according to any one of claims 1 to 9.