CS268501B2 - Device for control of frequency static converter - Google Patents

Abstract

A rectifier feeds an inverter having main thyristors T1-T4 in a bridge circuit. Two trains of pulses gate bursts of oscillation from an oscillator to five pairs of thyristors in opposite arms of the bridge alternately. Each arm of the bridge is connected to a pair of anti-parallel connected quenching thyristors Ta connected to a quenching capacitor Cs. The quenching thyristors are turned on respectively by pulses derived by a differentiating circuit and a monostable circuit from the leading and trailing edges of the pulses which turn on the main thyristors in a pattern such that each main thyristor is quenched at the correct time. A protective circuit is provided to short out the d.c. voltage between the rectifier and the inverter when a short circuit is sensed (Figure 1 not shown). <IMAGE>

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for controlling a static frequency converter with a rectifier, an inverter and an induction coil with a middle tap comprising a control genorator, a pulse splitter, a control pulse generator, main thyristor pulse amplifiers. and a static frequency converter start and stop circuit.

The device is intended for the control of static frequency converters with an intermediate DC circuit which converts the electric power of the variable frequency of the primary source into the electric power of the desired frequency for supplying the heating circuits of railway passenger cars, as well as to provide electric power for some auxiliary devices such as battery chargers and engines for propulsion of air-conditioning equipment forming part of electric train heating equipment,

There are known static frequency converters used for electric heating of trains, provided with electrical protection of the inverter, but they have the disadvantages that they are very complex in construction, which also entails relatively high production costs.

These disadvantages are eliminated by the static frequency converter control device according to the invention, since the first input is connected to the internal short-circuit protection unit in the central protection unit, the second input is to the input of the protection unit when the voltage deviates from the permissible values, external short-circuit protection unit output, fourth input with DC component input and output with first pulse splitter input, power cut-off circuit and protective short circuit connected between the inductor intermediate tap and the common rectifier output point and inverter input, input the static frequency converter start and stop circuit is connected to the first pulse splitter output, the static frequency converter start and stop circuit output is connected to the static converter load switch, and the second the third input being coupled to the control pulse generator and the fourth input coupled to the control generator output, and the other pulse distributors being coupled to the first to fourth pulse amplifiers of the first to fourth quenching thyristors, to the first to fourth pulse amplifiers of the first to fourth pulse amplifiers. main thyristors and blocking outputs of the first to fourth pulse amplifiers of the first to fourth main thyristors.

The static frequency converter provided with the device for its control according to the invention is highly reliable due to the existence of different protection units for each individual case, the device being easy to manufacture and requiring low production costs. *

1 shows a block diagram of a static frequency converter with an intermediate DC circuit, FIG. 2 a schematic diagram of an inverter, FIG. 3 a block diagram of a control for controlling a static frequency converter, and FIG. 4 shows a pulse diagram.

The static frequency converter according to FIG. 1 with an intermediate DC circuit consists of a two-way three-phase bridge diode rectifier 1, a forced commutation thyristor 2, a power supply switch 3, a load disconnector 4, a measuring current transformer 5, a protective current transformer 6, a voltage transformer 6 automation and control block 8, intermediate tap filter coil 9, filter capacitor 10, short circuit 11, load current inductance L2, fifth control diode 13, limiting resistor 14, damping capacitor 15, and intermediate voltage detection block 16 circuit.

The static frequency converter is supplied from a synchronous generator of the heating device, which delivers a three-phase voltage at a variable frequency depending on the speed of the diesel engine driving the generator, stabilizing the voltage at a given level. The voltage is supplied via the power supply switch 3.

The DC output voltage in the rectifier 1 has a constant value independent of the generator voltage kmiCS 268501 82.

The filter consisting of the induction coil 9 and the filter capacitor 10 ensures, in addition to continuous regulation, the disconnection of the inverter 2 in the event of a fault.

To avoid overvoltages when charging the filter capacitor 10, a protective block consisting of a fifth regenerating diode 13 and a series RC member consisting of a limiting resistor 14 and a damping capacitor 10 is provided. In the event of a fault in the load disconnector 4 or load, within 4 ms, it disconnects the supply voltage at the terminals of the inverter 2, commands the generator to be de-energized and the static frequency converter to disconnect.

The inverter 2 is supplied with DC voltage and provides a single-phase AC voltage of rectangular shape of constant magnitude and constant frequency at its output.

The automation and control block provides, by means of its electrical control apaimpulses, for the operation of the inverter 2 at the selected frequency. It receives information from the voltage transformer 7 and information about the output current from the protective transformer 6 for voltage protection and protection against external short-circuits, automation and control also receives information about the change in the polarity of the voltage in the intermediate r t

r

The DC block 0 of block 16 detects a change in the polarity of the voltage of the intermediate circuit to protect against internal short circuits in alternation 2 and ensures that both the power supply switch 6 and the frequency converter disconnector 4 operate by having the power on or off to system failure. The output current of the inverter is changed by means of a measuring current transformer 5.

made in a variant with forced (artificial) commutation, which is provided by a quenching thyristor Tal, Ta2, Ta3,

Inverter 2 is the first to fourth condensers Cs1, Cs2, Cs3 and Cg4. Quenching of the first to fourth main thyristor T1,

T3, T 4 (Fig. 2), which are currently in a conductive state, are achieved by removing the current passing through the first to fourth main thyristors T1, T2, T3, i

T4.

Ta4 and the first to fourth quenchers

T2.

with blocking voltage applied to their terminals. The load on the inverter 2 is connected

T4 at the same time to the middle The first 8 load of the bridge circuits formed by the first to fourth main thyristors T1, T2, T3, the fourth main thyristor T1, T4 are unlocked simultaneously, which determines the current flow during this half-period.

When the first and fourth main thyristors T1, T4 are unlocked, the first to fourth quenching capacitors Cs1, Cs2, Cs3, Cs4 are also charged via the first to fourth quenching thyristors Tal, Ta2, where the control pulse is received from the first sky of the second logic. The charging of the first to fourth quenching capacitors Cs1, Cs2, Cs3, Cs4 is carried out in oscillating circuits consisting of the first main thyristor T1, the first quenching thyristor Ta1, the first quenching choke Lsl and the first quenching capacitor Cs1 and the fourth main thyristor. thyristor T4, second quenching thyristor. Ta2, the second quench choke Ls2 and the fourth quench capacitor Cs4.

The first and fourth arc quenching capacitors Cs1, Cs4 are ready to quench the first and fourth main thyristors T1, T4a at the moment of the command opening, the third and fourth thyristors Ta3, T_a4. Due to the charging of the first and fourth arc quenchers, the capacitor Cs4 starts to interrupt the conductivity of the first and fourth heads T4. The discharge currents of the first and fourth arc quenching capacitors Cs1 are provided by the recharging T4, the discharge current tip being closed by the first and second thyristors T1, the quencher Cs1, the thyristor T1 *.

Cs4 are closed in the above circuits. Supply current flow during commutation of the oscillating circuit.

diodes 01, 02 connected in parallel with the first and fourth main direct voltage drops on them will be shown as the reverse voltage on the terminals of the first and fourth Ta4.

the main thyristor T1, T4. Upon completion of the commutation period, the opening of the second and third main thyristors T2, T3 and simultaneously the third and fourth quenching thyristors Ta3,

The reactive load is extinguished when the first and fourth main thyristors T1, T4, respectively the second and third main thyristor T2 go out. T3, the reactive load current is taken up by the first and second recovery diodes D1, 02, respectively three and the fourth recovery diode 03, 04, which transmit electric current over time in proportion to the magnitude of the load factor.

In the static frequency converter control device of FIG. 3, in the central protection unit 59, the first input connected to the intermediate circuit voltage detection block 16 is connected to the internal short-circuit protection unit 58, the second input connected to the voltage transformer 7 is the third input connected to the protective current transformer 6 is connected to the input of the external short-circuit protection unit 63. The fourth input connected to the inverter 2 is connected to the input of the DC protection unit 62. The outputs of the internal short-circuit protection unit 58, the DC component 62, the voltage-offset protection unit 59, the output of the stop button 61 and the control generator 17 of the connected frequency switch 66, also found in the central protection unit 69, are connected. with the inputs of the logical-sum circuit 55 in the central protection unit 69. Further, in the central protection unit 69, the short-circuit protection circuit 64 and its first input are connected by a signaling circuit 65 which is connected to the output of the short-circuit protection unit 63. . The second input of the protective short circuit control circuit 64 is coupled to the output of the internal short-circuit protection unit 58.

The protective short circuit control output c-bvcdu 64 forms the first output of the central protection unit 69 and is coupled to the protective short circuit 11, which is connected between the central tap of the inductor 9 and the common point of the rectifier output and the inverter input 2,

The second output of the central protection unit 69, extending from the logic sum circuit 55, is coupled to the first input of the pulse distributor 67, i.e., the first input of its binary flip-flop 54 connected to the input of the power disconnect circuit 60 whose output is coupled with power supply switch 3. '.

The input of the static frequency converter start / stop circuit 68, i.e., the first input of the fifth logic circuit 57, is associated with the first output of the pulse distributor 67, i.e. the output of the comparator; 21, wherein the second input of the fifth logic circuit 57 is connected to the output of the delay circuit 56 located in the start and stop circuit of the static frequency converter.

The output of the static frequency converter start and stop circuit 68 is coupled to the static frequency converter load switch 70 and to the second pulse distributor input 67, i.e., the second input of the bistable flip-flop 54. The third pulse distributor input 67 is coupled to the first inputs of the third and fourth logic circuit 43, 44 is connected to a control pulse generator 45, the second input of the third logic circuit 43 being connected to the output of the first logic circuit 23 and the second input of the fourth logic circuit 44 to the output of the first logic circuit 23. formed by the input of the first frequency divider 18 is coupled to the output of the control generator 17. The other outputs of the pulse distributor 67, i.e. the outputs of the first to fourth monostable circuits 31, 32, 33, 34, are coupled to the first to fourth pulse amplifiers 35, 36, 37. , 38 first to fourth fire The outputs of the third and fourth logic circuits 43, 44 are coupled to the first to fourth pulse amplifiers 46, 47, 48, 49 of the first to fourth main thyristors T1, T2, ТЗ, T4 and to the blocking thyristors. inputs of the first to fourth main thyristors T1, T2, ТЗ, T4.

In the pulse distributor 67, the common point of the first and second frequency dividers 18, 19 is coupled to the input of the integration circuit 20, the output of which is coupled to the first input of the comparator 21, the second input of which is connected to the runner of the potentiometer 22.

CS 269501 B2

The outputs of the comparator 21 formed by the Schmitt flip-flop and the second frequency divider 19 are connected to the inputs of the first and second logic circuits 23, 24, formed by the logic product circuits, the outputs of which are connected 27, and, in the second logic circuit 24, the inputs of the second derivative circuit 26 and the second negation circuit 29. The outputs of the first and second negation circuits 27, 29 are connected via the third and fourth derivative circuits 29, 30 to the third and fourth monostable flip-flops 33, 34. The first and second derivative circuits 25, 26 are connected to the first and second monostable flip-flops 31, 32. The outputs of the first to fourth monostable flip-flops 31, 32, 33, 34 are the second output of the pulse distributor 67 and are coupled to the inputs of the first to fourth pulse amplifiers 35, 36, 37, 39 of the first to fourth arc thyristors Tal, Ta2, ТаЗ, Ta 4, wherein the outputs of the first to fourth pulse amplifiers 35, 36, 37, 39 are coupled to the primary windings of the first to fourth pulse isolation transformers 39, 40, 41, 42 of the first to fourth arc thyristors Tal, Ta2, ТаЗ, Ta4.

The third and fourth logic circuits 43, 44 of the pulse distributor 67, formed by the logic product circuits, have outputs coupled through the first to fourth pulse amplifiers 46, 47, 48, 49 of the first to fourth main thyristors T1, T2, T3, T4 to the primary windings of the fifth The first to fourth main thyristors T1, T2, T3, TA are connected to the eighth decoupling pulse transformer 50, 51, 52, 53.

The bistable flip-flop 54 in the pulse distributor 67 has an output coupled to the blocking outputs of the first to fourth pulse amplifiers 45, 47, 48, 49 of the first to fourth main thyristors T1, T2, T3, T4 and this output is the fourth output of the pulse distributor 67.

The operating frequency of the inverter 2 is indicated by the control generator 17 generating the rectangular pulses of the forced frequency, see diagram 4a ns of FIG. 4. The first frequency divider 18 divides the two pulse frequencies of the control generator 17 and reaches a constant fill factor 1/2 see diagram 4b in FIG. The second frequency divider 19 divides again by the two frequency generated by the first frequency divider 19, see diagram 4c in Fig. 4. The rectangular pulses at the output of the first frequency divider 19 are integrated with an integrating circuit 20 which generates a triangular-shaped voltage with peak protection pulses. 4d, supplied to a comparator 21 formed as a Schmitt flip-flop, together with an altered voltage signal from the potentiometer 22. The comparator 21 outputs receive pulses divided by pauses, the length of which is determined by the DC voltage level of the po. These pulses come at the input of the first and second logic circuits 23, 24 simultaneously with the signal from the second frequency divider 19. At the output of the first and second logic circuits 23, 24, the pulses shown in Figures 4 and 6 in Fig. 4 are obtained having a length equal to half a period and a frequency equal to the frequency of the inverter 2. These half-period pulses are differentiated by the first and second differentiation circuits. 25, 26 and as a result, short derivative pulses are obtained, phased at the beginning of the half-period pulses, see diagrams h and i in Fig. 4. Inverting these pulses is performed by the first and second negation circuits 27, 29. Their output signal is differentiated by the third and fourth differentiation circuits 29, 30. At the output of the third and fourth differentiation circuits 29, 30, short pulses phased with the end of the half-period pulses are obtained, see diagrams Д and 1 <in Fig. 4.

The derived derivative pulses are fed to the first to fourth monostable circuits 31, 32, 33, 34, which produce pulses of constant length amplified thereafter by the first to fourth pulse amplifiers 35, 36, УЛ, 39 arc thyristors Ta 1, Ta2, ТаЗ, Тэ4, which they supply the primary windings of the first to fourth separating pulse transformers 39, 40, 41, 42. In their secondary windings, control pulses for quenching thyristors Taj., Ta2, ТаЗ, Ta4 are obtained. The inputs of the third and fourth logic circuits 43, 44 are received by 500 Hz pulses, generated by the control pulse generator 45, which transmit the third λ of the λ rst circuit n 44 only during the oxintnneo half-cycle of the riod signal. diagrams am and m in Fig. 4.

The pulses at the output of the third and fourth logic circuits 43 and 44 have opposite phases and are applied to the input of the first to fourth pulse amplifiers 46, 47, 48, 49 of the main thyristors T1, T2, ТЗ, T4. 53. The secondary windings of the fifth and sixth decoupling pulse transformers 50 and 51 are coupled in two and are designed to control the first and fourth main thyristors T1, T4 in the first diagonal of the drive with pulse length equal to the conductivity duration of the first and fourth main thyristors T1, T4. . The secondary windings of the seventh and eighth decoupling pulse transformers 52, 53 are connected in pairs and are designed to control the second and third main thyristors T2, T3 in the second diagonal of the drive with pulse length equal to the conductivity duration of the second and third main thyristors T2, T3.

All control pulses of the first to fourth thyristors T1, T2, ТЗ, T4 may be blocked by a DC voltage signal of appropriate polarity supplied by the bistable flip-flop 54 controlled by the logic sum circuit 55.

The logic sum circuit 55 is controlled at the input, thereby blocking control pulses from the first to fourth main thyristors T1, T2, ТЗ, T4 by protective circuits, which are:

The start-up delay circuit J56, which controls the fifth logic circuit 57 and thereby blocks the pulses, from the moment the power supply of the electronic circuits is connected up to a predetermined time after the delay time given by the onset of the pulse current pulses. This ensures the coexistence of control pulses of the first to fourth main thyristors T1, T2, ТЗ, T4, see diagram 4 in Fig. 4, and the charging pulse of the first to fourth quenching densities. For example, see Figure h for Figure C with 1, Cs2, Cs3, Cs4

The internal short-circuit protection unit 56 is inputted with a voltage signal from a resistive divider 16 (FIG. 1). At the moment the drive supply voltage polarity changes when an internal short circuit occurs, this unit generates a pulse to control the logic sum circuit 55.

The protection circuit 59 in the event of a voltage deviation from the permissible values, the input of which receives a voltage signal from the voltage transformer 7 (FIG. 1), determining whether the magnitude of the voltage at the inverter output is within the specified limits.

If the limit values are exceeded, the voltage deviation unit 59 controls the logic sum circuit 55 and blocks the pulses of the first to fourth thyristors T1, T2, ТЗ, T4 and disconnects the power supply switch 3 over the time interval via the power cut circuit 60. about 3 seconds. The stop knob 61 operates when the drive shutdown sequence is determined, which consists of blocking the main pulses through the logic sum circuit 55 and the bistable flip-flop 54 and controlling the power cut-off circuit 60 to open the power switch 3. DC component 62 in the output voltage of the inverter 2 to which the inverter output voltage 2r is input If there is a difference between the positive and negative half-per-phase output voltage in excess of the specified accuracy, then the DC component 62 in the output voltage of the inverter 2 generates a voltage signal after a specified time interval and commands to block the main pulses and also to disconnect the drive. The external short-circuit protection of the inverter is achieved by the external short-circuit protection unit 63, which is controlled by the protective current transformer 6.

If the supply current exceeds a specified maximum value, the external short-circuit protection unit 63 generates a voltage signal that controls the control circuit 64 of the protective short circuit control 11 and the signaling circuit 65.

The incremental frequency of the inverter frequency is changed by the switch with the frequency switch 84 from the frequency 16 2/3 Hz to the frequency 22 Hz, then it means that it moves through the position ^M 0 ^H , the pulses are blocked by the logic sum circuit 55. The operating frequency changes. The load of the frequency converter is connected by closing the disconnector 4 with the load switch 70 of the static frequency converter.

frequency. If the inverter is inactive while the inverter is operating and the inverter is disconnected, it is

Claims (2)

Static Frequency Converter Controller with Rectifier, Inverter and Medium Tap Induction Coil, Incorporating a Control Generator, Pulse Distributor, Control Pulse Generator, Main Thyristor Pulse Amplifiers and Arc Thyristor Pulse Amplifiers with Separate Pulse Transformers at Output, Central Protection Unit and a static frequency converter start and stop circuit, characterized in that the first input is connected to the internal short-circuit protection unit (58) in the central protection unit, the second input is to the input of the protection unit (59) when the voltage deviates from the permissible values, input with output of short-circuit protection unit (63), fourth input with input of DC protection unit (62) and output with first input of pulse splitter (67), with power cut-off circuit (60) and protective short-circuit (11) , which is connected between the intermediate tap of the inductor (9) and the common point of the rectifier output (1) and the inverter input (2), the static frequency converter start and stop circuit input (68) is connected to the first pulse distributor output (67) ) starting and washing the static frequency converter is connected to a static frequency converter load switch (70) and a second input of the pulse distributor (67), the third input of which is connected to the control pulse generator (45) and the fourth input of which is connected to the control generator output ( 17) _e e other outlet of the manifold (67) pulses are connected to the first to fourth pulse-amplifier (35, 36, 37, 38) prvnihc to fourth quenching thyristor (Tal, Ta2, TA3, TA4), the first to fourth pulsed amplifier (46, 47, 48, 49) of the first to fourth main thyristors (T1, T2, T3, T4) and the blocking outputs of the first to fourth pulse amplifiers but (46, 47, 48, 49) of the first to fourth thyristors (T1, T2, ТЗ, T4). Device according to Claim 1, characterized in that the pulse distributor (67) comprises first and second frequency dividers (18, 19), the common point of which is connected to the first input of the integration circuit (20), the output of which is connected to the comparator input. (21), the second input of which is coupled to the pctentiometer (22), and the outputs of the comparator (21) and the second frequency divider (19) are coupled to the inputs of the first and second logic circuits (23, 24), the outputs of which are coupled to the inputs of the first and a second derivative circuit (25, 26) and with inputs of the first and second negation circuits (27, 28), the outputs of which are coupled to the inputs of the third and fourth derivative circuits (29, 30), the outputs of the first to fourth derivative circuits (25, 26) 29, 30) are connected to the inputs of the first to fourth monostable flip-flops (31, 32, 33, 34), the outputs of which are the second output of the pulse distributor (67), and are connected to the inputs of the first to fourth pulses. amplifiers (35, 36, 37, 38) of the first to fourth quenching thyristors (Tal, Ta2, Ta3, Ta4), the outputs of which are connected to the primary winding of the first to fourth decoupling pulse transformers (39, 40, 41, 42); to fourth quenching thyristors (Tal, Ta2, Ta3, Ta4), also comprises third and fourth logic circuits (43, 44), the outputs of which form the third output of the pulse distributor (67), the inputs of third and fourth logic circuits (43, 44) are coupled to the outputs of the first and second logic circuits (23, 24) and the outputs of the third and fourth logic circuits (43, 44) are coupled through the first to fourth pulse amplifiers (46, 47, 46, 49) of the first to fourth main thyristors (T1). , T2, ТЗ, T4) with the head physician vin vin vin ul ul ml ml ml ul «In <4 th of the thyristor thyristor (50, 51, 52, 5Λ) of the first to fourth main thyristor (Ti, T2, ТЗ, T4), and further comprising a bist2bile flip-flop (54) whose first input It is connected to the output of the static frequency converter start (68), the second input of which is connected to the output of the central protection unit (69) and whose output is connected to the blocking outputs of the first to fourth pulse amplifiers (46, 47, 48, 49). the first to fourth main thyristor (T1, T2, T3, T4) and is the fourth output of the pulse distributor (67).