CS255207B1 - Electronic circuit for controlling the selected system object - Google Patents

Abstract

A microelectronic sequential circuit implementing three states, i.e. the on and off state of the object of interest to the central members using one bus and a shift state enabling the implementation of these states sequentially on all objects of the interconnected system. The connection of memory flip-flops of the D type and logical operators of the NAND type implements functions that can be used to control objects of the interconnected system via a single serial-parallel path for transmitting control pulses. The number of pulses sent to the transmission path is then the address for initializing the object connected in sequence to the path. It is used for switching and controlling a selected object in an interconnected system, which is controlled by one central member for the entire system. It can be used for periodic checking of the parameters of stored material in many places, for example in grain silos or the implementation of a busbar system, which saves inputs and outputs of higher control systems equipped with programmable automata or computers and saves distribution lines, mostly copper, in large systems.

Description

(54) Electronic circuit for controlling the selected system object

Microelectronic sequential circuit realizing three states, ie the state of switching on and off of the object of interest to the central members by means of one bus and the state of displacement enabling realization of these states gradually on all objects of the interconnected system. The connection of D-type memory flip-flops and NAND-type logic operators implements functions that can be used to control the objects of the interconnected system in a single series-parallel path of control pulse transmission. The number of pulses sent to the path is then the address for initializing the object involved in the path order. It is used for switching and controlling the selected object in the interconnected system, which is controlled by one central member for the whole system. It can be periodic checking of the parameters of stored material in many places, for example in grain silos or implementation of a busbar system, which saves inputs and outputs of higher control systems fitted with programmable controllers or computers and saves distribution, mostly copper wiring in large systems.

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BACKGROUND OF THE INVENTION The present invention relates to an electronic circuit for controlling a selected object of the system, composed of the basic operators of logic functions and steam elements, which in the function of a controller by impulsing pulses to a single transmission path connecting these controllers of the interconnected system. It allows the selected object to be connected to a common transmission line of information, power, control signals and the like by means of an appropriate gate controlled by the proposed controller.

In practice, systems are implemented where only one object can be connected from a large number of objects connected in the system to a central evaluation, control, power, regulation or other member. This is achieved by connecting lines from individual objects to the central member where manual or automatic switching of the lines by means of gates to the central member. Other solutions are that remote-controlled gates, pinning the entrance or exit of the object to a common conduit connecting the objects to the central member, are connected by the gates directly at the object.

To reduce the number of control wires of these gates, the gates are equipped with various address decoding devices transmitted by the control member. During automatic switching, various interlocking devices are implemented in the control panels to ensure that only one system object is connected to the bus or directly to the central member. All systems used so far require> a number of wires to control the controllers or gates of the objects. Although the number of conductors towards the object is considerably reduced by the code controllers, they require setting up and assigning the object to the addressed gate during assembly. In large systems, setting up decoders and assigning controllers and gates to objects is a demanding external assembly operation.

The elimination of the above mentioned deficiencies is solved by the electronic circuit according to the invention in connection with the connection of the system for remote connection of the selected object to the control station by a common transmission path, which solves MS. AO No. 215 504. The principle of the invention is that the transmission input of the first D-type memory flip-flop of the controller is connected either to the positive power terminal or to the second output of the preceding controller.

The clock pulse input of the first D-type memory flip-flop is connected to the first control terminal. The setting input of the first D-type memory flip-flop is connected to the positive power terminal. The reset input of the first D-type memory flip-flop is connected to the second control terminal. The output of the first D-type memory flip-flop is connected to the input of the third NAND-type logic circuit. The negated output of the first D-type memory flip-flop is connected to both inputs of the first NAND-type logic circuit whose output is connected to the transfer input of the second D-type memory flip-flop.

The inputs of the second NAND type logic circuit are connected to the first control terminal and its output is connected to the clock pulse input of the second D type memory flip-flop. The setting input of the second D type memory flip-flop is connected to the positive power terminal. The zero input of the same circuit is connected to the second control terminal. The negated output of the second D-type memory flip-flop is connected to the second input of the third NAND-type logic circuit. The output of the third NAND logic circuit, which simultaneously forms the first output of the controller, is connected to the input of the controlled object.

A novel effect is that the electronic circuit according to the invention allows serial production for all controllers in an identical construction, while controlling a predetermined object via a single transmission path interconnecting the serial inputs and outputs of the controllers. System in conjunction>.

with the invention AO 215 504 minimizes the need for distribution lines to control objects, saves the inputs and outputs of automated control systems, and reduces the workload of external assemblies.

The attached drawings show in Fig. 1 wired systems, which allow only one monitored object to be connected to the bus. FIG. 2 shows an electronic circuit for controlling a selected object of the system according to the invention.

According to FIG. 1, the controllers 1.1, ..., 1.1, 1.1 + 1.1 are connected in series so that the second output B of the preceding controller is connected to the transmission input D of the subsequent controller. The clock inputs are connected in parallel to the first control terminal X. The reset inputs of the controllers 1.1, ..., 1.1, 1.1 + 1, ..., 1, N are connected in parallel to the second control terminal Y. The power inputs are connected to the power terminals +, -. First output A of controllers 1.1, ···, 1.1. 1.1 + 1, l.N is connected to the input of objects 4.1, ..., 4.1, 4.1 + 1, ...,

4.N. The outputs of these objects are connected to a common bus!>.

According to FIG. 2, the transmission input D of the first memory type D flip-flop 2 of the controller is connected to the positive power terminal + or to the second output B of the preceding controller.

The clock pulse input C of the first type D memory flip-flop 2 is connected to the first control terminal X. The setting input 2 of the first type D memory flip-flop is connected to the positive power terminal + and the reset input R of this type D memory flip-flop is connected. The output 2 of the first type D memory flip-flop 2 is connected to the first input of the third NAND type logic circuit B.

The negated output 2 of the first D type memory flip-flop 2 is connected to both inputs of the first NAND type logic circuit 2. The output of the NAND type logic circuit 2 is connected to the transmission input D of the second type D memory flip-flop 2. The inputs of the second NAND type logic circuit 2 are connected to the first control terminal X and the output of this NAND type T_ is connected to the clock input C of the second memory Type D flip-flop 2 The setting input S of the second type D memory flip-flop is connected to the positive + power terminal. The reset input R of the flip-flop 2 is connected to the second control terminal Y. The negated output 2 of the second type D memory flip-flop 2 is connected to the second input of the third NAND type logic 2. The output of the third NAND logic circuit 2, which simultaneously forms the first output A of the controller, is connected to the input of the corresponding controlled object 4.1, ..., 4.1, 4.1 + 1, ..., 4N.

FIG. 1 illustrates a system connection that allows only one of the objects 4.1, ..., 4.N to be connected to the common bus 2. Before the system initialization, the logic level X and Y are applied to the logic level. The system initialization is accomplished by applying logic 1 to the second control terminal Y. Each of the controllers implements three states. These are the disconnect, wiring and displacement states.

The first disconnect state is realized by the controller +.1 for the first 1-1 pulses sent from the first control terminal X.After this time, the logic 0 value remains on the transmission input D. The disconnect state corresponds to the first output A logical 1 and the second output B logical 0.

With the falling edge 1-1 of the pulse, the second output of the controller preceding the initialized controller I is set to logic 1, which is connected to the transfer input D of controller 1.I, where logic 1 is set. on the controller outputs 1.I to change. On the first output A there is logic level 0, by means of which the object 4.1 is connected to the common bus 5 and on the second output B the logical level 0 remains. Object 4.I remains connected to bus 2 for the duration of the I-th pulse at the first control terminal X.

The third state that controller 1.I realizes is the feed state. After the I-th pulse has disappeared, the first output A of the controller 1.1 is logical 1 and the second output B is also logical 1. This state remains for the duration of all other pulses applied to the first control terminal X. the second control terminal Y, since the second control terminal Y is connected to the reset inputs of all controllers. At logic level 0 on the second control terminal Y, all controllers are set to the disconnect state.

The combination of 0 on the first output A and logic 1 on the second output B of the controller is undesirable and cannot be realized by any combination of logic levels on the controller inputs.

Fig. 2 shows the wiring of an electronic controller. Prior to system initialization, logic 0 is on the inputs of the first type D flip-flop 2, except for setting input S, where the logic level is always 1. At output g of the first type D flip-flop 2 is logic 0 and its negated output 2 is logic 1. which is also fed to both inputs of the logical operator 2 of the NAND type. This logical operator acts as an inverter here.

Therefore, at its output, logic 0 is applied to the transmission input D of the second D type 2 flip-flop. The clock input C of the second D type 2 flip-flop is connected via a NAND type logic operator 7 which serves as the control signal inverter. Therefore, it has logic 1 at logic 0 at the first control terminal X. The values at the other two inputs are the same as for the first type D memory flip-flop. At the output g of the second type D memory flip-flop, logic 0 and on its negated output g is logic 1. Logic 0 is supplied to the first input of NAND logic circuit 2 and logic 1 to its second input. Therefore, logic 1 is output on its output, which is also the first output A of the controller.

The controller enters the disconnect state by applying logic 0 to the second control terminal Y.

Changing the logical level from logical 0 on the second terminal Y to logical 1 does not change the proper logical level in the circuit, but prepares the controller to control using the level on the first control terminal X.

At logic level 0 on the second control terminal Y, any change in the logic level on the first control terminal X does not affect the change in the logic levels g in the circuit.

Controller 11 realizes the on state for the entire duration of the I-th pulse applied to the input C of the clock pulses. When the 1-1 pulse is terminated, the preceding driver switches to the shift state, causing logic 1 to be applied to the transmission input D of the first D-type memory flip-flop 2 of controller 1I. at the output Q of the first D-type memory flip-flop 2 logic 1 and at its negated input g logic 0.

On the transmission input D of the second type D memory flip-flop 2, which is connected to the output g of the first type D memory flip-flop 2 via the NAND type logic circuit 2 serving as the inverter, is logic 1. its negated output g is logical 1 because it is logical 0 at the clock pulse input C. The NAND type logic circuit 2 inputs are logical 1 and therefore logical 0 at the output. This output is also the first output A of controller +.1 and the logic 0 on it connects the object 4.I to the common bus 2 · Logic 0 on the second output B of the controller 1.1 prevents the connected 1.1 + 1 controllers from being switched on until the 1 + 1 pulse arrives at the control terminal X.

When the I-th pulse is lost, the 1.1 controller realizes the feed state. The inputs of the first D-type memory flip-flop 2 are supplied with logical 1, except for the clock input C, and the logic 0 is input to the clock pulse input C. Changing the clock pulses from logic 1 to logic 0 does not change the output values of the first memory flip The D input and setting input S and the reset input R of the second D type 2 flip-flop 2 are supplied with logic 1. Changing the logical level from logic 0 to logic 1 at the clock input C of the second D type 2 flip-flop change the logical level on its outputs. The output g is logical 1 and the negated output g is logical 0.

On the first input of logical operator 2 of NAND type is logical 1 on its second input is logical 0. On its output, which is also the first output A of controller + .I is logical 1, which ensures disconnection of object 4.I from common bus 2 · The second output B of the controller 11, which is identical to the output g of the second memory circuit 2 of the NAND type, is logic 1, which is transmitted to the transmission input D of the subsequent controller 1.1 + 1.

Designed circuit can be used for switching and control of selected object in interconnected system, where control or evaluation is done by one central member for whole system. It can be periodic checking of the parameters of stored material in many places, for example in grain silos tanks or implementation of busbar system, which saves inputs and outputs of higher control systems fitted with programmable controllers or computers. In large systems, they save power lines, mostly copper.

Claims (1)

SUBJECT OF THE INVENTION An electronic circuit for controlling a selected system object, characterized in that the transmission input (D) of the first D-type memory flip-flop (2) is connected either to the positive power terminal (+) or to the second output (B) of the preceding controller, input (C) ) the clock pulses of the first D-type memory flip-flop (2) are connected to the first control terminal (X), the setting input (S) of the first D-type memory flip-flop (2) is connected to the positive power terminal (+), ) of the first type D memory flip-flop (2) is connected to the second control terminal (Y), the output (Q) of the first type D flip-flop (2) is connected to the first input of the third NAND type logic circuit (8), Q) the first type D memory flip-flop (2) is connected to both inputs of the first NAND type logic circuit (6), the output of which is connected to the transmission input (D) of the second flip-flop the D type circuit (3), the second NAND type logic circuit (7) inputs are connected to the first control terminal (X), the second NAND type logic circuit (7) output is connected to the clock pulse input (C) of the second memory circuit (3) type D, the second D flip-flop setting input (S) is connected to the positive (+) power terminal, the second D flip-flop reset input (R) is connected to the second control terminal (Y) , the negated output (Q) of the second D-type memory flip-flop (3) is connected to the second input of the third NAND-type logic circuit (8), the output of the third NAND-type logic circuit (8) which is simultaneously the first controller output (A) connected to the input of the corresponding controlled object (4.1, ..., 4.1, 4.1 + 1, ..., 4.N).