CS242140B1 - Circuit for creating control signals in case of microcomputer power failure - Google Patents

Abstract

The solution concerns the connection of a circuit for - generating control signals in the event of a power failure of a microcomputer. It uses a memory capacitor to memorize the state. The state is determined by three voltage levels. During operation, the capacitor is fully charged, and the microcomputer is in operation. After detecting a power failure, this information is captured in a flip-flop circuit, which causes the memory capacitor to be discharged by the discharge circuit below the most suitable voltage level. The middle level determines the moment when the microcomputer memory is blocked. After the voltage starts up, the memory is unlocked only after reaching the highest level. The difference between the highest and middle levels ensures a delay between the failure notification and the memory blocking. The lower level ensures complete discharge of the capacitor in the event that another power failure occurs before full start-up. The invention will be used in microprocessor systems for controlling machine tools and robots.

Description

The invention solves a circuit for generating control signals in the event of a power failure of the microcomputer.

If the computer is supposed to continue operating before the outage after a power failure, it is necessary to add the power supply to the control circuits, which are detected before the power outage that the power supply) accumulated in the capacitors is approaching the minimum. Maintaining power failure issues instructions for the microcomputer · The microcomputer must, after detecting a power outage, store all data that will still be needed) to store in non-destructive memory · After the time interval reserved for this storage) the control circuit must give a signal blocking access to non-destructive memory it is undefined at reduced supply voltage and could overwrite stored data with incorrect data · After start-up, the control circuit must give a signal to reset the computer to its initial state and release the lock memoirs·

Connections are known to use battery-powered flip-flops to remember the state of the computer. · This is to keep the memory access signal at a proper value even when the computer is not powered. The disadvantage of this arrangement is that the flip-flop draws considerable current from the battery and thus shortens the time during which the non-destructive memory is able to store data. In the event of a battery discharge, the data is not only lost from memory in the event of a mains failure, but the computer's reset function after start-up is also compromised and thus its proper operation ·

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These weaknesses are eliminated by the control circuit for a power failure control circuit where the interrupt * output of the snap-on flip-flop is connected to the output by the interrupted wiring clamp · The input bias voltage terminal is connected to the setting input of the snap-flip-flop. · The charge output of the charge circuit is connected to the discharge output of the discharge circuit, to the control terminal of the memory capacitor, and to the input terminal of the hysteresis flip-flop whose blocking output is is connected to the output blocking terminal of the wiring · The output setting terminal of the wiring is connected to the setting output of the hysteresis flip-flop · The essence of the invention is that m, the memory terminal of the memory capacitor is connected to the input terminal of the threshold circuit, whose reference terminal is connected to the memory terminal of the memory capacitor · The output terminal of the threshold circuit is connected to the reset input of the flip-flop circuit ·

An advantage of the arrangement according to the invention is that it uses a capacitor as a storage element. The capacitor is discharged in the event of a mains failure. The wiring does not require battery power and emits all control signals correctly, regardless of whether the non-destructive memory and battery are connected or not.

This will allow the computer to self-test the status of non-destructive memory and notify the operator when the batteries are flat * This ensures more reliable system operation even when battery maintenance and inspection are neglected ·

An example of an arrangement according to the invention is shown in the block diagram of the attached drawing.

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- 2 »Individual blocks and wiring elements can be characterized as follows * The catch flip-flop i is made of transistors and resistors / and serves to detect power failure from control circuits at the input undervoltage terminal 01 of wiring * Discharge circuit 2 is made of transistor and resistor discharge capacitor £ after power-on * Charging circuit 2 consists of a resistor and serves to charge the memory capacitor £ P ° of power-on * Memory capacitor £ consists of * a fixed dielectric capacitor and serves to memorize the state of the control circuit * Threshold circuit 2 transistors and resistors and serve together with the flip - flop in

circuit also almost complete discharge of the capacitor of the memory £ after detecting power failure * hysteresis flip-flop 6 consists jo transistors and resistors _{and used for issuing control signals for adjusting and locking the memory depending on the state of the memory capacitor £. The individual blocks and elements are connected as follows * Interrupt output 14 of the snap flip-flop 1 is connected to the output break terminal 02 of the wiring * Input bias input terminal 01 is connected to the setting input 11 of the snap flip-flop X * discharge circuit control input 21 " discharge circuit reference 23 ' is coupled to memory capacitor reference terminal 42, and charge circuit 2 reference 32 < Desc / Clms Page number 3 > The blocking output 63 of the hysteresis flip-flop 6 is coupled to the output blocking terminal 03 of the circuit. The wiring output setting terminal 04 is coupled to the hysteresis flip-flop 6 setting output 64.

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the capacitor 8 is connected to the input terminal 51 of the threshold circuit% tottTwaifad, the terminal 52 of the threshold circuit% is connected to the reference terminal 42 of the memory capacitor 8. The output terminal 53 of the threshold circuit 6 is connected to the zero input 12 of the catch flip-flop 10.

The wiring works as follows: • If a power failure is detected, the control circuits not shown in the drawing give a signal to the input undervoltage terminal 01 of the wiring. • This signal sets the intercepting flip-flop i. interruption terminal 02 wiring signal requesting interruption of microcomputer operation The microcomputer based on this signal starts to store the data in non-destructive memory. when the discharging circuit 8 begins to discharge the memory capacitor 8, after the data retention time has elapsed, the voltage at the memory capacitor 8 reaches the lower limit voltage of the hysteresis flip-flop ·. outputs a blocking signal for non-destructive memory blocking via its blocking output 63 to the blocking output terminal 03 · At the same time, the hysteresis flip-flop 6 from its setting output 64 sends a setting signal to the output setting terminal 04 wiring. a storage capacitor £ continues until it reaches the level of the threshold voltage of the threshold circuit £ · After discharging the storage capacitor £ on the threshold transmits the threshold circuit £ through its output terminal 53 zeroing signal to the zeroing input 12 of the receiving flip-flop L _(and thus allow its overturn · This state occurs only when the control circuits report on the input undervoltage terminal

242 140 circuitry, that the voltage of the sources is OK and the supply of power supply is sufficient. Simultaneously, the signal from its output 13 to the control input 21 of the discharge circuit 2 closes the discharge circuit 2 * The memory capacitor χ starts to charge via the charging circuit 2 · The threshold circuit 2 restores the latching circuit 1 so that · Only when the voltage at the memory condensate χ reaches the upper limit of the hysteresis flip-flop X, the blocking of the nondestructive memory at the output blocking terminal 03 is canceled and the setting signal stops acting. • The difference between the upper and lower limit levels of the hysteresis flip-flop £ ensures that after the start-up of the computer, when the blocking signal on the output blocking terminal 03 stops operating, it is always terminated. the time required to store non-destructive memory data, even if the power outage came just after the computer started, so that even after a brief outage, the entire circuit will execute the entire sequence of control signals regardless of how long the outage lasted and when

The invention is particularly applicable to microprocessor systems for the control of machine tools, robots and other machines and equipment, where it is necessary to maintain the location of the interrupted operation in the event of a power failure.

Claims (1)

OBJECT OF VYuXliEZ 242 140 Circuit for generating control signals in the event of a power failure, in which the interruption output of the catch flip-flop is connected to the output interruption terminal of the circuit, the input undervoltage terminal of which is connected to the adjusting input of the intercept flip-flop. whose reference output is coupled to the memory capacitor reference terminal and the charge circuit reference output, whose charge output is coupled to the discharge circuit discharge output, the memory capacitor control terminal, and the hysteresis flip-flop input terminal, whose lockout output is coupled to the wiring block output terminal whose output setting terminal is connected to the setting output of the hysteresis flip-flop, characterized in that the control terminal (41) of the memory capacitor (4) is connected to the input terminal ou (51) of the threshold circuit (5) whose reference terminal (52) is connected to the reference terminal (42) of the memory capacitor (4) and the output terminal (53) of the threshold circuit (5) is connected to the reset input (12) circuit (1).