CS241809B1 - Semiconductor component with reduced lead inductance - Google Patents

Abstract

The essence of a semiconductor component with reduced lead inductance, consisting of a semiconductor package, a chip and lead electrodes, where the chip is provided with contact pads and the bottom side is attached to the base of the chip and the contact pads of the chip are connected to the lead electrodes of the housing of the invention, consists in the fact that the base of the housing is provided with a protrusion next to the chip and of the same height as the chip, while the chip is provided with a continuous contact area along the entire section adjacent to the protrusion of the socket, in the case of a rectangular shape of the chip along its longer side, the contact area of the chip being electrically conductively connected with the protrusion of the base of the housing by an electrically conductive sealant in a continuous area. The semiconductor component according to the invention has a significantly lower lead or lead electrode inductance.

Description

The invention relates to a semiconductor component with reduced lead inductance.

Current types of microwave semiconductor components are designed for operation in frequency bands higher than 1 GHz. One of the basic requirements for the geometric design of the horizontal chip structure and the structural design of the chip-and-case assembly of these components is to achieve the lowest possible inductance of their lead electrodes.

This issue is very important and fundamental, especially for transistors. Theoretical analyses and practical results show that each inductance in the emitter L _s of microwave transistors has a fundamental effect on the amplification capabilities of transistors, especially in frequency bands higher than 3 GHz.

In general, it can be said that the higher the operating frequency of the transistor, the greater the power the transistor amplifies, the greater the power gain, the smaller the inductance in the emitter of the transistor must be, when connected with a common emitter. ¹ In a large part of the literature, a theoretical formula is given for the maximum achievable power gain of a MAG in the form:

where represents:

g _DS collector conductivity

R _g series resistance compensated

Ri resistance, channel .mieizi emitterim and gate

R _with emitter series resistance

C _DG collector-gate capacity

L _is the emitter lead inductance.

From the above formula, it is clear that a significant

Table I

The increase in the emitter lead inductance to the value L _s (nH) ___ ¹ d.__ f[Ls) 4π ÍtCog (2R _g -j- Rí Rs 4- 2π ÍtLs) the influence of the emitter lead inductance L _s on the magnitude of the maximum achievable power gain MAG. The formula, for example, shows that in the case of a microwave power transistor MESFET with a gate width of 3 mm and a gate length of 1.5 μΐη, at the emitter lead inductance L _s = OH, the value MAG = 16.3 dB can be achieved at a frequency of f = 4 GHz. Now the emitter lead inductance increases, the original power gain MAG decreases as follows, according to the formula. I.

(Gain decrease by G _x (dB) from the original MAG time " 16.3 dB

0.016 1

0.036 2

0.063 3

0.096 4

0.137 6

0.443 9

It is clear that an increase in the emitter inductance by 0.1 inH reduces the MAG power loss here by approximately 4 dB. These theoretically derived dependences are in very good agreement with the experimentally verified results.

The assembly of MESFET transistor chips is now

Table II is usually performed with gold wire or gold tape. If a wire or tape with the dimensions given in the following Table II is used to connect the emitter of the transistor, then the inductance of the emitter lead L _s reaches the values:

Belt

thickness (μηι) 5 width (,umj 50 50 50 75 75 75 100 100 100 length (mmj 0.2 0.5 •1.0 0.2 0.5 1.0 0.2 0.5 1.0 inductance L _s (nH) 0.1 0.34 0.82 0.09 0.31 0.75 0.08 0.28 0,,,69 Wire average (μΐιη] 20 30 length (mim) 0.2 0.5 (1.0 0.2 0.5 1.0 inductance L _s (nH) 0.15 0.318 0.85 0.12 0.43 0.77

The effect of mounting the chip into the package or circuit is therefore significant. Manufacturers of high-end MESFET transistor types today solve this problem in three ways:

a) by the method of reverse assembly, so-called flipchip;

b) by means of through holes in the emitter, the so-called 'transistor-to-transistor connections';

c) by multiple connection of individual emitter strips to the base of the housing with gold wire, the so-called plated heat sink configuration.

All of these methods are technically of considerable benefit, but they are relatively very complex, demanding in terms of precision, time-consuming and pose a certain risk in chip processing.

In order to at least partially eliminate the effect of assembly and to substantially reduce the inductance in the emitter of the transistor and at the same time eliminate the mentioned difficulties of the other mentioned methods, a so-called induction-free embodiment of assembly of transistor chips was designed and implemented, which consists in the complete removal of lead wires or strips in the emitter circuit, as in the semiconductor component with reduced lead inductance according to the invention, the essence of which lies in the fact that the base of the case is provided with a protrusion next to the chip of the same height as the chip, while the chip is provided with a continuous contact area along the entire length adjacent to the protrusion of the base, in the case of a rectangular chip shape along its longer side, while the contact area of the chip is electrically conductively connected to the protrusion of the base of the case by an electrically conductive sealant in a continuous area.

The superior effect of the semiconductor component according to the invention lies in the substantial reduction of the inductance of the lead or lead of the electrode made in this way.

The essence of the invention is explained in more detail in the following text with reference to the attached drawing.

The semiconductor component with reduced lead inductance consists of a socket 1 of the housing, which is provided with a projection 1.1 next to the chip 2 of the same height as the chip 2, while the chip 2 is provided with a continuous contact area 6 along the entire length adjacent to the output 1.1 of the socket 1, in the case of a rectangular chip shape along its longer side, while the contact area 6 of the chip 2 is electrically conductively connected to the projection 1.1 of the socket 1 of the housing by an electrically conductive sealant 5 in a continuous area. _

The chip 2 of the semiconductor component is attached to the part 1 of the housing with its contact area 6 closely abutting the projection 1.1 of the housing. The electrically conductive sealant 5 is used to connect the contact area S of the chip 2 with the projection 1.1 of the housing along the entire length of the chip. The connection of the co-actuated surfaces of the remaining electrodes 7 and 8 of the semiconductor chip is carried out by a classical thermocompression or ultrasonic process with a suitable wire or tape.

Claims (1)

A semiconductor component with a reduced lead-in inductance consisting of a socket base, a chip and lead electrodes, wherein the chip is provided with conical tabs and a lower edge attached to the socket foot and the chip contact pads are connected to the lead electrodes of the case; The housing is provided with a protrusion (1.1) next to the chip (2) of the same height as the chip (2), while the chip (2) is provided with a continuous contact area along the entire length of the adjoining protrusion (1.1). (6), 'in the case of a rectangular' chip shape along its longer side, the contact area (6) of the chip (2) being electrically conductively connected to the projection (1.1) of the housing base (1) by an electrically conductive sealant (5) in continuous desktop.