CS240378B1 - Pulse counting device with square root characteristic and reversible counter - Google Patents

Abstract

The device is intended for processing input statistical impulse information and compressing this information in such a way that the quantization error resulting from the compression of the information is proportional to the statistical error of the input signal, especially for use in space physics. The essence of the device lies in the fact that the outputs of the first group (1) of flip-flops are connected to one group of inputs of the control logic circuit (4), the outputs of the second group (2) of flip-flops are connected to the second group of inputs of the control logic circuit (4), the group of outputs So, Si... SM of the control logic circuit (4) is connected to the setting inputs (set) of the flip-flops of the first group (1) and the output (X) of the control logic circuit (4) is connected to the input of the complementary reduction circuit (5), the output of which is connected to the input of the second group (2) of flip-flops.

Description

The apparatus is intended to process input statistical pulse information and compress this information in such a way that the quantization error resulting from the compression of the information is proportional to the statistical error of the input signal, particularly for use in space physics.

The principle of the device consists in that the outputs of the first flip-flop group (1) are connected with one input group of control logic circuit (4), outputs of the second flip-flop group (2) with a second input group of control logic circuit (4), output group So , Si ... S _{M of the} control logic circuit (4) is connected to the set inputs (set) of the flip-flops of the first group (1) and the output (X) of the control logic circuit (4) is connected to the input of the auxiliary reduction circuit (5) the output of which is connected to the input of the second flip-flop group (2).

SUMMARY OF THE INVENTION The present invention provides a pulse counter with a square root characteristic and a reversing counter, consisting of two groups of flip-flops, pre- and post-reduction circuits, and a control circuit for processing input statistical pulse information and compressing such information to produce a quantization error. the compression of the information was proportional to the statistical error of the input signal.

Known devices for processing pulse information achieve its compression by modulating the logarithmic characteristic. In this case, the quantization error is proportional to the counted pulse N. When monitoring the statistical process, its statistical error is proportional to the square root of the counted pulse VN. Obviously, for small N, the quantization error will be considerably smaller than the statistical error, and on the other hand, for large N, the quantization error will determine the accuracy of the measurement because it will be considerably larger than the statistical error. In conventional devices, compression is achieved by a wiring comprising two groups of flip-flops connected in a linear reading chain and a multiplexer. The input of the first group of flip-flops is then the input of the device and the outputs of the flip-flops of this group are connected to the multiplexer working inputs. The output of the multiplexer is connected to the input of the second group of flip-flops and the outputs of this group are connected to the control inputs of the multiplexer and represent the output word of the device. In the devices, a pre-reduction circuit is also used to increase the compression coefficient.

The invention consists in the fact that the outputs of the first group of flip-flops are connected to one group of input control logic · circuit outputs the second group of latches with a second group of input control logic, a group of outputs So, Si, ... S _M control logic circuit connected to the setting inputs of the flip-flops of the first group and the output of the control logic circuit is connected to the input of the auxiliary reduction circuit, the output of which is connected to the input of the second flip-flop; replacement of the multiplexer with control logic circuit, which will both transcribe the contents of the flip-flops of the second group into the flip-flops of the first group at the moment when the content of the first group is equal to zero; An additional reduction circuit connected between the output of the control logic circuit and the input of the second flip-flop circuit.

The novel effect of the invention is manifested in particular in that the dependence between the number on the output of the device m and the number of input pulses N is roughly in the form m = 1 · VN = C. VN where m - number at the device output

N - number of input pulses k - number of flip-flops of preliminary reduction number of flip-flops of additional reduction

C - constant given by the particular device design.

dN

The quantization error of such a device is then roughly equal to and proportional to the statistical error. This advantage increases the accuracy of the measurement over the conventional arrangement while maintaining the output word length and hence the reduction coefficient.

The attached drawing shows a schematic diagram of a device consisting of the first 1 and second 2 groups of flip-flops, the pre-reduction circuit 3, the control logic circuit 4, and the additional reduction circuit 5. The flip-flops within the first group 1 are connected to a linear downward counting chain; they must be equipped with adjustment inputs. The flip-flops of the second group 2 are connected to a conventional linear counting chain counting upwards. The input of the pre-reduction circuit 3 forms the input of the device, the output of this circuit being connected to the input of the first flip-flop group 1. The outputs of the flip-flop circuits of the first group 1 are connected to the inputs (A _o , Ai ... ... Am-J of the control logic circuit 4. The output (X) of the control logic circuit 4 is connected to the input of the auxiliary reduction circuit 5. reduction 5 is connected with the second group of two flip-flops. the outputs of the flip-flops of this group are associated with the second group of inputs of the control logic 4 (B _o, B ... B _m _i) and simultaneously forms the output device. the outputs _(O, Si ... s _M -i) control logic 4 are connected to the control (set) inputs of the flip-flops of the first group constitute the first output device outputs the second group of flip-flop 2, the output state is thus identical to that _of input B, B _T ... B _m _i control logic fourth

Using the device, each pulse at the pre-reduction circuit 3 output decreases the A number at the inputs of the control logic circuit 4 by one

M-1

A = Σ Ai2 ‘s-o

At the moment when the number A = 0, the logic control circuit 4 provides the transcript of the number B via the outputs S _o , Si ... S _M -i

M-1

B = Σ Bi2 ⁱ = = 0 from the output of the second group 2 flip-flops to the first group 1 flip-flops to hold A ± B. At the same time, the logic control circuit 4 generates a pulse on its output X, which is counted by the additional reduction circuit 5. the device could start its function, the logic control circuit 4 must ensure that at the beginning of the counting cycle the number 1 is written to the first flip-flop of the first group so that A = 1 applies as well to the first flip-flop of the second group 2; B = 1. By default, the output of the first flip-flop of the first group 1 is set to one, the output of the first flip-flop of the first group 1 is set to one, the output of the first flip-flop of the second group 2 is set to one. the second groups are reset and the flip-flops of the pre-reduction 3 and additional reduction 5 circuits are also reset. From the point of view of control logic 4, the default state is A = i, B = 1. For simplicity, we assume that the coefficient of both the pre- and post-reduction is one, that is, these circuits do not reduce the number of pulses. Then, the first pulse at the device input generates A = 0, B = 1 at the control logic input, and since the condition A = 0 is met, the control logic 4 first causes the number B to be increased by one and then the group 2 the first 1, the resulting state will be A = 2, B = 2. The next impulse at the device input will cause the state A = 1, B = 2. The third impulse will bring the device to the state A = 0, B = 2 and - because A = 0, the control logic 4 operates, increments the number B to B = 3 and overwrites the contents of the second group of tilting circuits of the first group so that the state A = 3, B1 = 3 is established. flip-flops, ie to the state

B = 2 ^M -1

In this way, the device models the square root characteristic, which can be written approximately in the form n = 1/2. VN

If we assume that a pre-reduction circuit with a coefficient of 2 ^{k a} is connected between the comparator output and the input of the second group of flip-flops, a coefficient of auxiliary reduction with a coefficient of 2 is obtained.

The device is advantageous for use in cosmic physics, where the dynamics of the observed processes are often several orders of magnitude and the compression of information is desirable without the help of computer technology, because the memory circuits are the components most damaged by cosmic radiation.

Claims (1)

Pulse counter with square root and return counter, comprising a pre-reduction circuit and two groups of flip-flops connected to linear counter chains, the input of the first group via a 2 ^k pre-reduction circuit connected to the pulse source and the outputs of the second group representing the output word A device characterized in that the outputs of the first flip-flop group (1) are connected to one of the inventive inputs of the control logic circuit (4), the outputs of the second flip-flop group (2) are connected to the second group of inputs of the control logic circuit (4). outputs So, Si. . . . The _M control logic circuit (4) is coupled to the flip-flop input set (1) of the first group (1) and the output (X) of the control logic circuit (4J is coupled to the auxiliary reduction circuit input (5) whose output is connected to the input of the second flip-flop group (2).