CS232197B1 - Reconstructive connection with comparators - Google Patents

Abstract

The invention solves the implementation of autonomous diagnostics of multiprocessor and multicomputer systems by the comparison method. The solution is achieved by connecting comparators and switches between the terminals of identical microcomputer subsystems. The switches can then be used to reconfigure the comparators, thereby ensuring autonomous diagnosability of the entire system.

Description

The subject of the invention is a reconfiguration circuit with comparators that solves the implementation of autonomous diagnostics of multiprocessor and multicomputer systems using the comparison method.

For the implementation of autonomous diagnostics of multiprocessor and multicomputer systems, two basic strategies can be used, namely the strategy of mutual tests between individual microcomputer subsystems or the strategy of comparison of responses in pairs of identical microcomputer subsystems. As for the comparison method, it is possible to perform comparisons either in the microcomputers themselves or in comparators built into the system. Here the question arises of how to incorporate these comparators into the process of autonomous diagnostics of the entire system. The connections considered so far either implement comparisons with very reliable elements, so that this part of the system falls into the area of the so-called hard core, or the comparators are tested from individual microcomputers without a fault. In the first case, the disadvantage lies in the need to ensure fault-free operation of the comparators, in the second case, with a certain probability of occurrence of a fault in the comparators, the maximum number of localizable faults in the microcomputer subsystems is reduced.

These disadvantages are eliminated by the reconfiguration connection with comparators according to the invention, the essence of which lies in the fact that the terminal of the first microcomputer subsystem is connected to the first terminal of the first comparator, to the first terminal of the second switch and to the first terminal of the fourth switch, the terminal of the second microcomputer subsystem is connected to the second terminal of the first comparator, to the first terminal of the second comparator, to the first terminal of the first switch and to the first terminal of the third switch, the terminal of the third microcomputer subsystem is connected to the second terminal of the second comparator, to the second terminal of the first switch, to the second terminal of the second switch and

- 2 232 197 with the second terminal of the third comparator and the terminal of the fourth microcomputer subsystem is connected to the second terminal of the third switch, to the second terminal of the fourth switch and to the first terminal of the third comparator.

The advantage of the above connection is the possibility of reconfiguring the connection of the comparators using switches, thereby ensuring the localization of up to three faults, which means that in the event of one fault in the comparators, the localizability of two faults in the microcomputer subsystems is maintained as in the same connection with the tested comparators, but provided that no fault has occurred in the comparators,

The attached drawing shows an example of a reconfiguration circuit and comparators according to the invention, which can be diagnosed in the event of up to three faults occurring simultaneously. Terminal 10 of the first microcomputer subsystem 1 is connected to the first terminal 50 of the first comparator, to the first terminal 90 of the second switch 9, and to the first terminal 120 of the fourth switch 12. Terminal 20 of the second microcomputer subsystem 2 is connected to the second terminal 51 of the first comparator 2, to the first terminal 60 of the second comparator 6, to the first terminal 80 of the first switch 8, and to the first terminal 110 of the third switch 11. Terminal 30 of the third microcomputer subsystem 3 is connected to the second terminal 61 of the second comparator 6, to the second terminal 81 of the first switch 8, to the second terminal <?1 of the second switch 9, and to the second terminal 71 of the third comparator 7. Terminal 40 of the fourth microcomputer subsystem 4 is connected to the second terminal 111 of the third switch 11, to the second terminal 121 of the fourth switch 12 and with the first terminal 2P of the third comparator 7

The diagnostics of the entire system takes place in six configurations, which are created by cyclic shifting of comparators 5, 6 and 7 between the terminals of microcomputer subsystems 1, 2, 3 and 4, in sixteen cycles.**A cycle is a time interval in which simultaneously realizable comparisons take place. In the basic configuration, switches 8, 9, 11, 12 are in the open state with inactive signals on control inputs 82, 92, 112 and 122. During the comparisons realized by comparators 5, 6 and 7, the equivalence function is switched to non-equivalence by active signals on control inputs J2, 62 and 72, and the negation function is switched to one of the comparator inputs by active signals on control inputs J4, 64 and 74. In this way, the comparators from the microcomputer subsystems are fully stimulated. After the first reconfiguration, the first comparator 5 is connected between the second microcomputer subsystem 2 and the third microcomputer subsystem 3 by closing the second switch 9 with an active signal on the control input 92. The second comparator 6 is connected between the third microcomputer subsystem 3 and the fourth microcomputer subsystem 4 by closing the third switch 11 with an active signal on the control input 112. The procedure is similar for other cyclic reconfigurations. In the basic configuration, one cycle takes place, i.e., all comparisons are carried out synchronously. In other configurations, three cycles always take place. The results of the comparisons appear in binary form on the outputs 53, 63 and 73 and are sent for evaluation to the status decoder /not shown/, which determines the module or modules with a fault at its output.

The above system can be modeled by two graphs, namely the connection graph P/ U _M , Ug, R, B/ and the comparison graph M/ U _M , C/. In the graph P, U^ is the set of nodes representing identical microcomputer subsystems / macromodules/, Ug is the set of nodes ujg, representing identical comparators / comparison modules/, R is the set of edges -----r. j representing switches between the terminals of macromodules u.^ ^and / reconfiguration connections/ and B is the set of edges -b. . repre—

Ji® 1,J of the connecting links between the macromodule u^ and the comparison module u

JG / permanent connection/. In the graph M, U^ is the set of nodes representing identical macromodules and c is the set of edges representing the comparison of macromodules and the comparison realized by the module u-^g. Each configuration is represented by a different graph M

The weight vectors / ,kk ' i,J* ^z i,j ^z are assigned to the individual edges of the graphs M for the comparison of macromodules u^ _M , the comparator u^gs by the equivalence function, the second coordinate is the binary result of one step of the comparison of macromodules u^, u^ _M when the information on the terminals of the comparator u^gs matches the nonequivalence function and the third coordinate is the final binary result of the remaining sequence,J' ^z 7 ,/» where the first coordinate is the binary result of one step of the comparison of macromodules U£ _M , u^ _M when the information on the terminals of the comparator u^gs matches the nonequivalence function and when the information on the terminals of the comparator u^gs matches the equivalence function. The result has the value 0 if there is no detection of a mismatch, the result has the value 1 in the opposite case, i.e. when one or both of the compared macromodules have a fault. When the comparator and at least one of the compared macromodules have a fault, is the result of the co-comparison unreliable denoted by x /0.1/ A faulty comparator that compares two macromodules without a fault generates the result zý - =1. It is assumed that during the diagnostics j J .

no fault will occur. Furthermore, we consider only faults of a permanent nature and the communication paths together with the synchronization circuits are considered as the hard core. The connection according to the invention can be illustrated by the following graphs P and M.

P -

M-charts

1/ basic configuration

(*3,k /

2/ after the first reconfiguration

X ( ^Χ 3/Ψ ( y _{3 ¥}

(Xy-Í&i

4/ after the third reconfiguration

.6/ fifth reconfiguration * *

232,197

In the above model, it is possible to prove that to ensure the diagnosability of the system with the same probability of occurrence of all faults, in the case of simultaneous occurrence of a maximum of t faults /in macromodules or in comparison modules/ it is necessary to ensure at least 'n» _r =t+2 macromodules and n-=t comparison modules. The number of comparisons performed by each comparator is at least ( J -1, or there are (V) -1 comparators and each performs one comparison in the basic configuration and one comparison of a pair of macromodules for which no fault was detected in the basic configuration. However, it is realistic to assume an unequal probability of occurrence of faults in macromodules and in comparator modules. Then we define the diagnosability of the system for t faults with the distribution t^/tg, where t^ is the maximum number of localizable faults simultaneously occurring in macromodules and t^ is the maximum number of localizable faults simultaneously occurring in comparator modules, it is possible to prove that the above-mentioned circuit is autonomously diagnosable in one step / without intermediate repair phases / for t=3 with the distribution 2/1. In general, it is therefore necessary to perform -1 reconfigurations, _min> . t„ ₊ 2, n _{c nin} .=t= t _w ,+t„ the number of comparisons performed by one comparator q·, _ ( /¾ ' ó ρ° ^δβ * ^s P ^{ínaiSa S} 1 min. = bl ⁺² > ^{poiíet oyklfl C} 1 min. = ť x í (utf ) -l] +1. The number of cycles can be reduced at the cost of using more switches/ ^ο^ο^θΔθβ ¹ in jJaž^^^oá^guration to perform the test application in one cycle ac^= 2 ² ) . The reconfiguration method at the level of macromodules and comparison modules can be further combined with the method of detecting the direction of information transfer on the bus to increase the degree of diagnostic resolution. Each macromodule is then modeled as a subset of functional modules u·*, / microprocessor, memory, peripheral device/. The comparison of macromodules u^, is then divided into the comparison of address and control lines of the bus marked by the edge — and the comparison of data lines of the bus marked by the edge —

And— and

-d* i, J

The mutual stimulation of the functional modules u^p, u^p within the macromodules is represented in the graph by the edge weight w. - having the value 0 when the functional module is stimulated by the functional module u^p and the value 1 otherwise. The value of the weight j refers to the moment of the first detection of a mismatch on the bus data lines. The above connection in the basic configuration is then represented by the following graph F /Up, U^, A, D, S/, where the symbols denote the set of the relevant nodes and edges.

Here u _gF , u _12F , ^u i _5F > u _17F represent microprocessors, u _gp , u _11F , ^U 16F' ^U 19F ^represent memories and ulop, u-j_4F ^U 13F» Uj8F represent peripheral devices, to individual edges a. · and d. . are assigned to K * ^x > v -*-,ΰ binary weights . and which have the value 0, when there is no detection ·*· ř v -*- > d mismatch and the value 1 otherwise. Since the localization of defective comparator modules is performed within the framework of the reconfigurations already performed, the comparators do not have to be completely stimulated / according to the assumptions they are now without a fault / and one reconfiguration is enough for the localization of functional modules. The system becomes sequentially diagnosable because it is necessary to carry out any repair of the faulty comparator or functional module during the diagnostics.

The possibility of using the above connection is when implementing autonomous diagnostics of all multiprocessor and multicomputer systems when applying the comparative testing method using built-in comparators.

Claims (1)

SUBJECT OF THE INVENTION 232 197 Reconfiguring wiring with comparators and microcomputer subsystems composed of microcomputer, memory and peripheral devices, characterized in that the terminal (10) of the first microcomputer subsystem (1) is connected to the first terminal (50) of the first comparator (5), to the first terminal (90). the second switch (9) and the first terminal (120) of the fourth switch (12), the terminal (20) of the second microcomputer subsystem (2) is connected to the second terminal (52) of the first comparator (5), to the first terminal (60) of the second comparator (6), with the first terminal (80) of the first switch (8) and with the first terminal (110) of the third switch (11), the terminal (30) of the third microcomputer subsystem (3) is connected to the second terminal (61) of the second comparator (6) , with the second terminal (81) of the first switch (8), with the second terminal (91) of the second switch (9) and with the second terminal (71) of the third comparator (7) and the terminal (40) of the fourth microcomputer subsystem (4). connected to the second terminal (111) of the third switch (11), the second terminal (121) of the fourth switch (12) and the first terminal (70) of the third comparator (7).