CS229371B1 - Circuit of continuous product of two frequencies - Google Patents

Abstract

The invention relates to circuits for digital counting and a circuit for calculating the continuous product of two frequencies. The circuit consists of a programmable frequency divider, to whose preselection is connected a circuit for evaluating the period length of one of the two multiplied frequencies. Output circuits are connected to the programmable frequency divider for blocking the output when the entire circuit operates in an undesirable range of multiplied frequencies.

Description

(54) continuous product of two frequencies

This invention relates to circuits for digital O- _t and solves counting circuit kontinálního product of two frequencies. The circuit is made up of a program.

movatelným frequency divider to whose ί preset circuit is connected to evaluated _t financing period length multiplied by one of the two frequencies. Output H connectors are connected from the programmable frequency divider to block output when the entire circuit is operating in an undesired range of multiplied frequencies. ; ; ;

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228 371

- 2 229 371

The invention solves a circuit of a continuous product of two frequencies.

The known circuits for performing the product of two quantities are either analogue, for example pulse multipliers, or analogue-digital, i.e. frequency-controlled integrators, or digital, so-called calculators, using different types of codes for their operation.

A disadvantage of analogue and analogue-digital circuits is the unreliability associated with the stability of the parameters of components, especially their thermal stability and the like. A disadvantage of known digital code multiplication circuits is that these circuits do not give a constant frequency result.

These drawbacks are tracated by solving a continuous product circuit of two frequencies. It consists of a programmable frequency divider with a first frequency input, write inputs, decade inputs and set outputs, a first shaping circuit with a second frequency input delay circuit, a clock generator pulses, a blocking circuit, a series of interconnected decimal counters, a second shaping circuit and a limiter with a frequency output that are connected to each other so that the first shaping circuit is connected to the delay circuit input and the programmable frequency splitter input inputs to the second input of the interlock circuit, the first input of which is connected to the output of the clock pulse generator and whose output is connected to the input of the first decadocal citation and the output of the delay circuit is connected to the third input of the interlock on the one hand to the zero inputs of a series of decimal counters whose BCD outputs are connected to the decade inputs of a programmable frequency divider whose setting outputs are connected to the input of the second shaping circuit, the output of which is connected to the first limiter input; the penultimate decimal counter from the series of decimal counters.

The advantage of this circuit is that it allows to digitally produce the product of two variables expressed in frequencies, with the result being provided continuously in the form of the resulting output frequency, so that the result (product) can be varied continuously over time according to time changes of both input factors. Such a feature of the designed circuit is advantageously usable, for example, for the evaluation apparatus of belt weighers for conveyors.

An exemplary embodiment of the invention is shown in the accompanying drawing.

The continuous product circuit includes a programmable frequency divider 22 with a first frequency input 221, a write input 222, a 223, 224 ' 225 < 226 > The programmable divider 22 is composed in a known manner of a series of interconnected reversible decimal counters 01, 02, 04, 05 in an exemplary embodiment for five decades, and a series of 3CD digital memories of code 06, 07, 08, 09.

also for the first to fifth decades. The continuous product circuit further comprises a series of interconnected decadic counters 11, 12, 13, 14, for five decades whose BOD outputs 114, 124, 134, 144. 154 are connected to inputs 223. 224,

225. 226. 227 decades of the programmable divider 22. Further, the continuous product circuit includes a first shaping circuit 16 with a second frequency input 161, the output 162 of which is connected to the input 171 of the delay circuit 17 and the input 222 of the programmable frequency divider 22. on the other hand, to the second input 182 of the blocking circuit 48, to whose first input 181 a clock pulse generator 21 is connected through the output 211. Blocking circuit output 164 is connected to input 111 of first decimal counter 11 from a series of decimal counters

The output 172 of the delay circuit 17 is connected both to the third input 122 of the blocking circuit 18 and to the reset inputs 113, 123, 133. 143. The 153 series of decimal counters 11, 12, 12, 11, 11, 12 The outputs 228 of the programmable frequency divider 22 setting are connected to input 191 of the second forming circuit 12, whose output 192 is connected to the first input 201 of the limiter 20 equipped with the output of the resulting

The second input 202 of the limiter 20 is coupled to the output 142 of the last but one of the series of decimal counters 11. 12, 13. 11. 12 - in the exemplary embodiment of the Fourth Decimal Counter 14.

Upon the introduction of the first frequency f · at the input 221 of the programmable frequency divider 22, the resulting frequency 228 appears at its output 228, the magnitude of which is given by the formula -j - where N - is the number entered in the series of memories 06, 07, 08.

BOD codes that represent the preset of the programmable frequency divider 22. After the introduction of the second frequency f2 inlet 161 into the first forming circuit 16, the pulses of the second frequency f ₂ is narrowed to the width of the order of ^ sec and the thus treated pulses via the output 162 in the two first, second inlet 182 to the interlock circuit 28, second input 171 to the delay circuit

17 ,. on the other hand, to the inputs 222 of the programmable frequency splitter 22 *. At the same time, the normal frequency fn of the clock pulse generator 21 is routed through the first input 181 and the output 184 of the blocking circuit 18 to the input 111 of the first decimal counter 11 of the series of decimal counters 21, 12, 12 »14. in the form of a decimal number in the BGD code by its BCD outputs Hl. 12, 12, 11, 11, 154 provide inputs 223, 224. 225. 226, 227 decades of the programmable frequency divider 22. Rewriting to digital memories 06, 07. 08. C9. 10 performs pulse BCD second frequency f ₂ inputted to the write input 222 of the programmable divider 22 frequency. This pulse simultaneously blocks the passage of the normal frequency fy in the blocking circuit 18. The time delay pulse generated by the passage of the delay circuit 17 is first applied to the reset inputs 113. 1 23. 133. 143. 153 series of decimal counters 22 »12» 12 »11» 12 »which resets but is connected to the third input 182 of the 2θ blocking circuit. ^{»v η} θ®ζ simultaneously blocks the passage of the normal frequency FJJ · This is evaluated by using the normal frequency f j length of period the second frequency f2, and the period length is in the form of a decimal number is written to the programmable divider 22 frequency. The length of the period is the inverse of the frequency. The resulting frequency fj is discharged from the continuous product circuit from the outputs 228 of the programmable divider 22 through a second shaping circuit 12 in which the pulses are extended to a width of the order of msec and through a limiter 20 formed as a filter and gate,

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5 229 371 in which the output frequency fj is blocked in the range of 0 to 1.25% of the desired operating range of the entire circuit. Generally speaking, the circuit of a continuous product of two frequencies performs

- the product of the first frequency fj with the second frequency fg such that the first frequency f ~ | divide by the inverse of the second frequency fg, which value is written in the form of a number into the preset of the programmable frequency divider 22 with the arrival of each subsequent pulse of the second frequency fg. In the exemplary embodiment, the values of the first frequency f1 have proved to be effective of the order of hundreds of kHz, the second frequency fg is of the order of kHz, a normal frequency of fH »100 kHz, the resulting transfer function of the whole continuous product circuit being fj ** 1 ^x ? 2 _t

Claims (1)

SUBJECT OF THE INVENTION 229 371 Continuous product of two frequencies ₍ characterized in that it comprises a programmable frequency divider (22) with input (221) of first frequency, inputs (222) of write inputs, inputs (223, (224, 225, 226, 227) and decades) 228 / setting, first shaping circuit (16) with input (161) of second frequency, delay circuit (17), clock generator (21), blocking circuit (18), series of connected decimal counters (11, 12, 13, 14) 15, the second shaping circuit (19) and the limiter (20) with output of the resulting frequency, whereby the first shaping circuit (16) is connected with its output (162) to the input (171) of the delay circuit (17) and input (222) of the programmable frequency divider (22) writer inputs, second to the second input (182) of the interlock circuit (18), to which the first input (181) is connected by the output (211) of the clock pulse generator and / is connected to the input (111) of the first decimal reference (11) and the output (172) of the delay circuit (17) is connected to the third input (183) of the blocking circuit (18) and to the zero inputs (113, 123, 133, 143, 153) of the decimal counter series. , 12, 13, 14, 15 / whose BCD outputs (114, 124, 134, 144, 154) are connected to inputs (223, 224, 225, 226, 227) of the programmable frequency divider (22) are the outputs The settings are connected to an input (191) of the second forming circuit (19) whose output (192) is connected to the first input (201) of the limiter (20), the second input (202) of which is connected to the output (142) of the penultimate. a decimal counter (14) from a series of decimal counters (11, 12, 13, 14, 15).