CS213613B1 - Connection for obtaining the bit tact by record on the movable magnetic memory means - Google Patents

Abstract

A circuit which is used to recover the bit rhythm when recording in a moving magnetic medium. It is an extension to OA 7603667 concerning the demodulation of split phase signals in series on a magnetic tape. The signals are produced by scanning the symbol of the reproduction signal in the presence of a bit rhythm with a suitable phase position. A transmission stage is incorporated in the circuit which is controlled by the output signal of a preceding two-stage counter and the zero pulse. The control is such that the transmission stage is brought into a predetermined state if the counter overruns during the period of the zero pulse. This condition is maintained during the zero pulse and analogue voltages derived in accordance with a predetermined table. A control voltage is generated which is linear within a given period depending on the phase shift between the reproduction signal and the bit rhythm.

Description

(54) Assistance for obtaining a bit rate when recording on moving mgy memory devices. . ‘'

BACKGROUND OF THE INVENTION The present invention relates to a circuit for obtaining a bit rate when recording on moving magnetic means, such as a rajginti tape, a magantic disk and consisting of. serial - connection of the oime circuit, the bull - through detector, the pulse extension, the digital - query circuit, the voltage - controlled oscillator, the filter connected in parallel. to the query circuit - and the oscillator, - the phase delay Sien and the sign comparator.

A process is known dem> duuace record and phase доЛ ' «Affairs, in which the bits zaznamennávjí -maganeioký series on tape and involvement to implement this způsobu.- substantial čáet- co - CIVA in getting the bit clock using such IOV ^{é é} Hzeného Osci oru ^{acrylate, the} esters of KMI NA2 ^ ⁿ = ^the frequency of the bit clock signal. Consequently použlií- interrogate digital circuit - to obtain pile ^- řídioí oCaroakeeiitik order t ^ ^y t ^{o -} t Hdicí nature ^ysics yls ^b '' - CO-ODS ncjjeraiěěi tupňovány ^{and -} end mel ^y Stamm drop must be in ²ⁿ zvoltt. ι.a ^t IAEE in the ^{YH NATURAL й} j ^e 2 ¹ 16. As ýři each zero crossing of the reproduced signal zero-forming inpulsy whose duration fibrillation 2 ° - th piece of bit lengths, given at very high frequencies bits (short zero A further disadvantage is that the control characteristics of the voltage-controlled oscillator at the occurrence of the L-pulse train have twice as high a stmoot as the control-ohaaikteistics when the O-pulse train is detected. ^ é pulses which ae ^ cihiáej outside ^{- - Z} desired ^{Pa for} AM0, with enhanced degree к ^ OVEM control voltage. Such zero pulses výskej her if for oaarι and lowering the upins

213 613

213813 will use certain special signals whose structure deviates from the code used in the information or if there are any interfering pulses · In addition, it requires a four-level analogue converter, required for & - 16. slight resistance tolerance / NDR -patent no.124 408 /.

It is an object of the present invention to provide a query circuit that causes a reduction in the frequency of errors in the demodulation of the encoded digital signals.

It is an object of the present invention to provide a digital interrogation brazing device that provides control characteristics of the same slope for a further connected voltage-controlled oscillator.

According to the invention, this problem is solved by providing a quadruple frequency of the bit rate in the digital interrogation circuit by means of an input bus which is connected to the output of a voltage-controlled oscillator to a two-stage counter. a logic circuit input, the second logic circuit input being coupled to the first output of the two-stage counter, and the third logic circuit input being coupled to the bistable multivibrator input for resetting and to the zero pulse input bus connected to the pulse extension member output; the fourth input of the logic circuit is connected to the negative output of the bistable multivibrator and the output of the logic circuit is connected to the output bus, whose output voltage through the filter forms the control voltage for a papermodulated oscillator.

An impulse is generated each time the signal is transmitted through zero. During the zero pulse duration, the bistable multivibrator returns to a certain state in which it is for the entire duration of the zero pulse if the counter is shifted during that time. ; In conjunction with a logic circuit that assigns zero pulse logic states, both counter stages and a bistable multivibrator, to the analog voltages according to the table below, a control voltage is generated which, depending on the phase offset of the reproduced signal and bit rate within the band equally steep slope for eled O-pulses or L-pulses.

This digital interrogation circuit is used in a circuit to obtain a bit rate and demodulate a phase-modulated magnetic record. Furthermore, the voltage controlled oscillator is oscillated to 2 ⁿ times the frequency of the bit rate. The use of this digital query circuit allows to select 2 ⁿ »4 and increase the duration of the zero pulse occurring in this circuit to 1/4 of the bit length.

In the digital interrogation circuit, the output signal of the voltage-controlled oscillator is initially applied to a counter having n · 2 computer steps to which a bistable multivibrator is connected, which performs the following function: If no zero pulse N / Й and 0 / is present a bistable multivibrator maintained at 0; If there is a zero pulse (N «L) and if during this time there is a shift of the counter, that is, if both stages of the counter go from state L to state during this time, then the state of the bistable multivibrator is the condition lasts for the duration of the pulse.

Zero pulses, outputs of both counter and bistable multivibrator stages are applied to the logic circuit. This logic circuit assigns a zero pulse logic state,

213 »13 of both the counter stages and the state of the stable multivibrator analog voltage U _M as the output voltage below. analog voltage Uq or Ůj according to the table below. N represents a logical state. zero impixus, A 1 state counter 1, Ag 1 state counter 2, and U state bistable mutitibiate · U _M is. the mean 'value of the output voltage' that is. . always represents for N = 0. 'represents the sum of the mean value of U ^ and the minimum deviation' aU of the control and Uq is the difference of these values, while X is a logical variable whose state does not affect the result.

The time mean value of the output voltage of the logic circuit represents the control voltage for the voltage-controlled oscillator. Within a phase shift between the reproduced signal and a bit rate of size has. the control voltage of the linear waveform and the same slope of the 0 or L-imds sequence. The table below shows. The formation of the output voltage ^ and U ^ is given. logic circuit for occurring logical states.

N - A ¹ * A ² AT 0 X X X Um 1 0 0 0 no L L 0 0 o _o L 0 L 0 ° M L L L . 0 ° L L x X L ^HIVE 01 . Uf +. AU ^ϋ 0 ^{- U} _M · AU Especially í přednc The invention consists in: that even at high bit rates se

create technically feasible zero lengths. u ^ iaů. Furthermore, there is an accurate linear control characteristic that has the same large steepness in the sequence. 0-pulses or Limpulses ©

The invention will be explained in more detail below. in the example shown in FIG. of the accompanying drawings, in which: FIG. a record without a return to zero of the NRZ and a phase record is shown. Fig. 2 shows a bit rate acquisition and phase-modifier demodulation. FIG. shown in two stages. counter. behind him. a bistable muutivibrator for generating the signal for FIG. Fig. 3b shows a logic circuit for generating a logic voltage, and Fig. 4 shows an output logic circuit in the presence of a sequence of L-pulses and different phase signals between the bounded reproduction signal and the bit clock; the output ia voltage is shown. 6a) 6b) shows the course of the control voltage as a function of the phase shift between the reproduced signal and the bitdVjfa clock, when the occurrence of the 0-pulse sequence and the different phase shifts between the bounded reproduced signal the sequence of O-pulses or L-pulses and in FIG. 7 is. schematic diagram of a two-stage counter, bisectile mutlivibiate and logic circuit.

Giant. . 1. record without returning to. zero LDZ and two records. with phase prayer.

U - record --- - without. return - to - zero LDZ - do not have - two - for -. -the next-. bits of the same '. of the type Z1-bit. none - transitions.- .. Records- 1p ,. '- -1p-. With at least one phase transition, at least one transition for. one - - hitting '' - and - - are - '- hence - .. better - - fit' -. - for - - recording - on - moving - have jgetiokýoh - memories, - resp. paoOťwých - means. - - Ig Record. .s - phase - ooo.duáGÍ. - has'. each - at each - boundary of the - transition bit - and - at --Lb ^^ itu - has an - additional - transition - in - the - center - - - bit. - 'Record' - - with - phase - modulation - has - - always - in - center - - bit: - transition. - - with '-defined - direction. - - - - By - - se - '. they receive - with - - successive - - successive - 'identical - -bits - -additional - transitions - to - - boundary' - - bits.

. Giant. -. 2 shows the wiring -to-get-bit-clock-a. demoodulation - records -. with - phase - modulation. - This - wiring; -sestává-. from the series connection of the limiting circuit 4 to the zero crossing detector 5 ^; '- Sienu -, 6 -' impulses, -. of the digital - query circuit - the voltage - controlled - oscillator - 2 - and - filter - - -. - connected - in parallel - to the query circuit J and the oscillator J, further consists of a series-connected. - - delay - Sien - 10 'phase - and' comparator - circuit 11 - ^ паЮпек · - - - - Z - reproduced - - signal - W - '- record - in- - phase - moodulation - is - created - bounded - - loudspeaker - signal; W>. At the transitions of this - bounded, reproduced - signal - WS. . -that Odpooida.jí -. zero. - passing the --reprddlkovaeéhd - signal. - W - se. they obtain in the zero-detector 5 narrow passages. - Extension. Sien - pulses. generates - of - these - pulses. zero - - pulses ¢, -. which - drawbar - Width 1Ζ4. bit, digital. ' the query circuit 8 transmits and generates from the output voltage via the filter 8. control voltage for voltage - controlled oscillator. 2, - from which the - is obtained. bit rate BT. Zpoďáóvací. member - 10 phase. . performs - required assignment - - bit phase -. beats - BT - phase of reproduced - signal - - W. comparative circuit .. 11 -. signs. 'se. from the reproduced boundary. - - WS signal - retrieves - information as - record Ij. without return · - .. ·· / to zero - -NRZ.

; Fig. 3 - - shows -. two-stage - counter .-. se - .za - z · · - - - ^ - ^ηΟ - 0 ^ 1 ^ 11) ^ 10 ^ 0 £ ·

On ^- ga u ^p. two ^of USTU ^PN ovéhd. ^ tane ^{- -} -is ^- - 4 ^b nabo ^{- -} . Frequency of Fog - - Strokes ^- 4g. This _ ^- frequency two-stage -čítač děěí ..- 1 ..- has outputs Ap - ^Ag - X ^ Tartovaoí. output 'T per. it - engage it ^from en ^{Star - -} bistab ⁱ ^^ l: h ^ o £ ^-. mu ^ lv ^^ lo ™ is ^- associated ^- with. - ^- negated by ⁰ output. . í ^g . ' .Na ^- . vstu ^p u ^{- £ -} - is-. ^- le logic ^TA - - -1 signal. - On - input - R for. - back - flip -. they are brought back to their original state. zero ^- pulses N. ^- Bistabiiní ^- тШ ^ ЬгЙ ^ г ^- 2 - has two outputs ϋ. and If it is at the input R for ^{- - introducing} - livllivlihydrate from Z to. of the original. signal state - 0, - then - at - output u - is. state - 0, - while with L-signal this output can radiate to. -1bStayl. Stav-state - will… be impressed. - So - just. when - se - at - clock input T ilstailleíhd. muHi-vibrator - - changes - state - - and. at the input - R resetting - are zero -. pulses N,

Fig. 3b shows a logic circuit 2 for generating a control voltage, whose three inputs are connected - - s - echo, a = φ: i: outputs ϋ, Ig: and -χ v - fig. fourth input - there are zero pulses .Д. logical. circuit 2 'eeetava of three negators 2 - of which two negators are - in a--. connection with a common collector. The outputs of these stages are. connected -se. with two equally large resistors Rp and. Rg, taking on resistance. Rp is the operating voltage; U. -. Without zero-pulses, the output voltage is still --- when zero-pulses occur. - output ^P EEI - on - depending on the counter status, or -υθ BU3 - products for pets předcOhίázjící - tabulknA '

In order to demodulate the function, FIG. 4 shows the generation of the output voltage. In case of a sequence of L-impUls for different - phase - displacements,

213 613 produced by the WS signal and the bit rate BT, the duration of which is θθ. Here, the phase input refers to. per bit rate BT (uppermost line of the picture), wherein the positive phase offset of the bounded reproduction signal corresponds to the left offset of that signal.

Figure 5 shows the output voltage waveform U U when a sequence of O-pulses occurs. The dashed curves in both figures, i.e. Fig. 4 of 5, show the waveform of the output voltage that would be set if the bistable mu tator 2 was not available.

Fig. 6 shows the control voltage curve as a function of the phase between the reproduced signal and the bit rate, with 1 bit being considered. In conjunction with the fact that the phase error area used is the permissible phase error area for the phase-noise records used, this waveform may be considered ideal since, to the extent permitted, the O-pulse sequence (upper part of Figure 6a) or the L-pulse sequence occurs. lower part of figure .6b /, there is exactly linear control characteristic with the same pitch. In addition, in the sequence of O-pulses, the influence of disturbing signals, undesirable passage of the zero reproduced signal at the occurrence of amplitude and special signals, etc., is reduced due to the control voltage outside this range. The control voltage thus obtained is used to control a voltage-controlled oscillator, the in-line filter being used to smooth out for the period of the bit and to achieve the desired dynamic behavior.

Fig. 7 shows a block diagram of a circuit that consists of a two-stage counter

2, bistable 2 and logic circuit 2, whose function has already been described. A 4-fold bit rate is applied to the input bus SI. 4f, and zero pulses N are applied to the input bus S2.

Claims (1)

OBJECT OF THE INVENTION A latch for obtaining a bit rate when recording on moving magnetic storage means, consisting of a series connection of a limiting circuit, a zero crossing detector, a pulse extension, a number of the query circuit, a voltage controlled oscillator. a filter connected of ^a raletit to dotazovému circuit and oscillator ZPO ^ pink compounding ^ him member asks a comparator marks, vyznnaující is tm that čísicovvém interrogation circuit / 7 / is brought UtařnásobnV frequency / 4f / bit clock signal through input a bus (31) which is connected to the output of the voltage-controlled oscillator (9) to a two-stage counter (1) whose second negated output (ÁgZ) is coupled to the clock input of the bistable mautivibrator (2) and to the first input of the logic circuit (3); the second input of the logic circuit (3) is coupled to the first output (Aj) of the two-stage counter (1) and the third input of the logic circuit (3) is coupled to the bistable input (2) to bring it to its initial state and the input bus (S2) of zero pulses (I), which is connected to the output of the impulsion extension member (6), the fourth. the input of the logic circuit (3) is connected to the negative output (0) of the bistable muttivibrvvru (2) and the output of the logic circuit (3) is connected to the output bus · / S3 / whose output (U ^) iathe voltage in the voltage controlled oscillator / 9 /.