CS212450B1 - Connection of the generator of symbols for the image forming unit - Google Patents

Description

(54) Display character generator wiring

The invention relates to a wiring of a character generator for a display unit, which consists of two registers with input signals for selecting a character, load resistors, inverters and gates with signals corresponding to the display line and eight fast memories organized into 256 four-bit words.

Most of the hitherto known connections relate to a character generator implemented by reprogrammable MOSs and an appropriate combination network. In particular, these memories do not meet the new speed requirements due to their long releasing time. Given the choice of control signals and the circuit functions of the addressing and selection circuits, a very complex combination network results. This will result in increased material and production costs, more difficult recovery and servicing of mounted inserts. A larger number of circuits also leads to an overall lower reliability of the whole device.

These disadvantages are overcome by the connection of a character generator for the display unit according to the invention, which consists of two registers with input signals for selecting the symbol, load resistors, inverters and gates with signals corresponding to the display line and eight fast memories organized into 256 four-bit units.

The first register outputs are connected to the fourth to seventh addressing inputs of all eight memories and the first output of the second register is connected to the eighth addressing memory inputs, while the third output of the second register is connected to the first inverter input and simultaneously to the first input the second, fourth, and ninth gates and the fourth output of the second register are connected to the second inverter input and simultaneously to the second fourth gate input, the first inverter output is connected to the first first gate input and the second inverter output is connected to the second gate first input and the second entrance of the second gate. The display line selection terminals are connected to the inputs of the third to sixth inverters, the third inverter input being connected to the first addressing input of the first six memories, and the third inverter output being connected to the first addressing inputs of the seventh and eighth memories. The input of the fourth inverter is connected to the first input of the fifth gate and simultaneously to the first input of the thirteenth gate, the output of the fourth inverter is connected to the second addressing input of the first six memories and simultaneously to the first input of the tenth gate and the fourteenth gate. The input of the fifth inverter is connected to the second input of the fifth gate and at the same time to the first input of the twelfth gate, the output of the fifth inverter is connected to the third input of the eleventh gate and also to the third input of the fourteenth gate. The input of the sixth inverter is connected to the second input of the fourteenth gate, the output of the sixth inverter is connected to the second inputs of the twelfth gate and the thirteenth gate, and to the first input of the sixth gate. the addressing input of the first six memories, while the second addressing input of the seventh and eighth memories is connected via the eighth inverter to the eighth gate output, to the first input of which the third gate is connected and to the second input connected to the second inputs of the ninth and tenth the tenth inverter connected the diacritical indication terminal. The output of the ninth gate is connected to the third addressing input of the seventh and eighth memories via the ninth inverter. The first input to select the memories of the first six memories is connected to the output of the seventh gate, to the first input connected to the first input of the eleventh gate is connected through the seventh inverter the display ban terminal and to the second input is connected the output of the fifteenth gate. The output of the 15th gate is connected to the first memory selection input of the seventh and eighth memories. The second input for selecting the memories of the first and second memories is connected to the output of the first gate together with the first input of the third gate. A second gate output is connected to the second input for selecting memories of the third and fourth memories. A fourth gate output is coupled to the second memory selection input of the fifth and sixth memories together with a second third gate input, and a second output of the eleventh gate is connected to the second memory selection input of the seventh and eighth memories, the second input of which is connected to the tenth gate output. The first four character generator outputs are coupled to the odd memory outputs together with the first four resistors, while the other three character generator outputs are coupled to the even memory outputs along with the other three resistors and the opposite ends of all seven resistors are connected to a positive voltage source together with the eighth resistor. whose second terminal is connected to the mode selection inputs of both registers. The clock inputs of both registers are connected to the source of clock pulses, and terminals for selecting a character are connected to the inputs of both registers.

The advantage of the circuit according to the invention is that the desired function is achieved by TTL memories. By selecting new circuit functions and reorganizing the input control signals, the number of integrated circuits in the logic combination network has been reduced, which in addition to reducing material and manufacturing costs also means increasing reliability and simplifying service.

The connection of the character generator for the display unit will be described in more detail below with reference to the attached drawing.

The character generator is based on fast memories, such as SN 74 S 387, indicated in the diagrams KQM1 to R0M8. These memories are organized into 256 four-bit words. Displayed plsmé has a grid of 7x9 points, the distance between letters is 2 points. The addressing and selection circuits perform the following functions: a) addressing the first three address bits of the memories according to the display line; b) addressing the remaining bits according to the selected character; c) selecting a pair of memories by character type and display line; (d) prohibition of display in certain special cases.

The input connection signals are four signals L1 to L4 giving information about the display line and eight signals P1 to P8 for calling the symbol. The eight character selection input signals £, P až to Pg are applied to input terminals g, £, 2 of the first and second registers RG1.

R02. At the time of the rising edge of the clock pulse from the source g, the input signals JJ. to P8 overrides the g, g, g, g outputs of both RQ1 registers at the same time. RG2. The first five signals P1 to P5 are used for direct addressing of all oami memories R0M1 to R0M8. the sixth input signal P6 is case sensitive, the seventh and eighth input signals P7, P8 determine whether it is a digit, a Latin alphabet or a Russian alphabet.

The outputs 1 to 1 of all memories ROMs to R0M8 are connected in parallel to a common load resistor R1 to R4, whereby a logical sum of the corresponding outputs is realized. Selection of individual memories R0M1 to RQM8 is made by inputs CS1, CS2. To be selected for a particular patch, the logical sum of the inputs CS1 CS2 must be. to select memories equal to zero. If this condition is not met for any of the memories, then all of its outputs are logical ones.

In the first and second memory, R0M1. R0M2 stores the first eight lines of digit characters in the third and fourth memories of R0M3. R0M4 stores the first eight lines of characters of the Latin alphabet, in the fifth and sixth R0M5 memories. ROM6 stores the first eight lines of characters of the Russian alphabet, in the seventh and eighth memory R0M7. R0M8 are the last ninth lines of all characters and diacritical marks.

For signals applied to the first and second inputs CS1. CS2 functions for memory selection:

CS1 = L2.LT + L2.L? + E5.I3.L4 + ZK for the first to sixth memory R0M1 to R0M6. (1) CS2 = P7 + P8 for the first two ROMs. ROM2 (2) CS2 = P7 + P8 for two more R0M3 memories. RQM4 (3) CS2 = P + P8 for the fifth and sixth R0M5 memories. R0M6 (4) CS1 = L3.L4 + L2.L4 + E5.L3.L4 for the seventh and eighth memories of R0M7. R0M8 (5) CS2 = L2.DZ + L3 + ZK for seventh and eighth memory R0M7. R0M8. (6)

The ZK prohibition signal disables the display and when it occurs, all memories R0M1 to R0M8 are in logic 1, the DZ signal indicates the presence of a diacritical mark.

Function (1) is normalized by the seventh gate ffi, the twelfth to fifteenth gate H12 to H15, and the seventh inverter 17. wherein the negated values of the input signals L1 to L4 corresponding to the display line are taken at the outputs of the third to sixth inverters 13-6. The second function (2) is realized by the first gate H). a third function (3) by a second gate H2 and a function (4) by a fourth gate H4. The fifth function (5) is realized by the twelfth to fifteenth gate H12 to H15 and the function (6) by the tenth gate H10. the eleventh gate of H11. the seventh inverter 17 and the tenth inverter IIP.

The input signals L1 to L6 corresponding to the display line serve longer to address the first three addressing bits of the first to the sixth memory R0M1 to ROM6. To transform the extension number to the appropriate address, the following relations apply:

A0 = LI

A1 »L2

A2 »L2.L3 + L4 (9), the relation (9) being realized by the fifth gate H5 and the sixth gate H6

For addressing the first three address bits of the seventh and eighth memories R0M7. The following applies to R0M8:

AO »LT

AI = P7.P8.E4 + P7.P8.E4 (11)

A2 = P7.E5 (12) wherein the relation (II) is realized by the first gate III, the third and fourth gate H3. H4. the eighth gate H8. the inverter Ig, the tenth inverter IIP, and the relationship (12) is realized by the ninth gate H9 and the tenth inverter 19.

The signals from the outputs of the character generator H through to the EDC are then routed to registers where the sequence of points is converted. These circuits are no longer the subject of the invention and are therefore not drawn. Also, the longer circuits that are loaded by the outputs R, G, R, D of both RG1 registers are not plotted. BQ2.

Claims (1)

OF THE INVENTION Wiring of a character generator for a display unit, consisting of two registers with input signals for character enable, load resistors, inverters and gates with signals corresponding to the display line and a fast money line organized into 256 four-bit words, characterized in that the outputs (A, B, C, D) of the first register (RG1) are connected to the fourth to seventh addressing inputs (A3, AM, A5, A6) of all eight memories (RON1 to R018) and the first output (A) of the second register (RQ2) is connected to the eighth addressing memory inputs (A7) (ROMs to R0M8), while the third output (C) of the second register is connected only to the input of inverters (II) and simultaneously to the first input of the second, fourth and ninth gates (H2, H4, H9) and fourth output ( D) the second register (RG2) is connected to the input of the second inverters (12) and simultaneously to the second input of the fourth gate (H4) and the output of the first inverters (II) is connected to the first input of the first o the gate (H1) and the output of the second inverter (12) are connected to the second input of the first gate (H1) and simultaneously to the second input of the second gate (H2), the display line selection terminals are connected to the inputs of the third to sixth inverters (13 to 16) ), the input of the third inverters (13) being connected to the first addressing input (A0) of the first six memories (ROMs to ROH6) and the output; the third inverters (13) are connected to the first address input (A0) of the seventh and eighth memories (R0M7, R0M8), the input of the fourth inverters (14) is connected to the first input of the fifth gate (H5) and the first input of the thirteenth gate (H13) , the output of the fourth inverters (14) is connected to the second addressing input (A1) of the first six memories (R0M1 to R0M6) and simultaneously to the first input of the tenth gate (H10) and the fourteenth gate (H14); the second input of the fifth gate (H5) and the first input of the twelfth gate (H12), the output of the fifth inverter (15) is connected to the third input of the eleventh gate (H11) and the third input of the fourteenth gate (H14) ) is connected to the second input of the fourteenth gate (H14), the output of the sixth inverter (16) is connected to the second inputs of the twelfth gate (H12) and the thirteenth gate (1113) and to the first input of the sixth gate (H6), the second input of which is connected to the output of the fifth gate (H5), the output of the sixth gate (H6) being connected to the third addressing input (A2) of the first six memories (R0M1 to ROM6), the seventh and eighth memories (R0M7, R0M8) are connected via the eighth inverter (18) of the eighth gate output (H8), to the first input of which the third gate output (H3) is connected and to the second input connected to the second inputs of the ninth and tenth The H9, H10) is connected via the tenth inverter (110) to the diacritical indication terminal, the third addressing input (A2) of the seventh and eighth memories (R0M7, R0M8) is connected through the ninth inverter (19) to the output of the ninth gate (H9). the memory selector input (CS1) of the first six memories (R0M1 to R0M6) is connected to the output of the seventh gate (H7), to which the first input connected to the first input of the eleventh gate (H11) is connected via the seventh inverter (17) display and whose second input is connected to the output of the 15th gate (H15), whose inputs are connected to the outputs of the 12th to 14th gate (H12, H13, H14), while the output of the 15th gate (H15) is connected to the first memory selection input (CS1) the seventh and eighth memories (ROM7, R0M8), to the second memory selection input (CS2) of the first and second memory (ROMs, ROM2) is connected the output of the first gate (H1) together with the first input of the third gate (H3), memory selection (CS2) of the third and fourth memory (ROM3, R0M4) is connected to the output of the second gate (H2), the second input for memory selection (CS2) of the fifth and sixth memory (ROM5, R0M6) is connected to the output of the fourth gate (H4) with the second input of the third gate (H3) and the second input for memory selection (CS2) of the seventh and eighth memories (R0M7, R0M8) connected to the output of the eleventh gate (H11), to the second input the output of the tenth gate (H10) wherein the first four outputs (VI-V4) of the character generator are associated with the odd-memory outputs (1-4): (R0M1, R0M3, ROM5, ROM7) together with the first four resistors (R1-R4), while the other three outputs (V5, V6, V7) of the character generator are coupled to the outputs (1, 2, 3) of the even memories (R0M2, R014, R0M6, R0M8) together with the other three resistors (R5, R6, R7) and opposite ends of all seven resistors (R1 to R7) ) are connected to the positive voltage source together with the eighth resistor (R8), whose second output is connected to the mode selection inputs (MC) of both registers (RG1, RG2), the clock inputs (C1, C2) of both registers (RG1, RG2) are connected to the clock source (H) and to the inputs (A, B, C, D) Both registers (RG1, RG2) have terminals for character selection.