CS200904B1 - Connection of the dividers with the contact switches - Google Patents

Description

The invention relates to a circuit breaker with contact switches for cooperation and logic circuits, which is equipped with a single common noise immunity circuit for all contact switches.

When entering data from contact switches into logic circuits, it is necessary to protect the contact switches against undesirable parasitic flickering, which prevents clear and accurate data entry.

The hitherto known circuits use two-pole or three-pole connection of contact switches. Each contact switch is provided with either a gate forming circuit or an RC filter. The divider function can only be reliably realized with contact switches provided with gate gate shaping circuits. This means that for each contact switch a shaping or noise-immune element must be connected. With a large number of contact switches, this modification is circumferentially complex. Wiring is expensive and unreliable.

These disadvantages are eliminated by the connection of the dividers 8 by contact switches, consisting of two timing circuits, a delay circuit, a gating circuit, two flip-flops, a product circuit, a summation circuit, a divider and a contact switch, according to the invention. the gating circuit is connected to the direct entry of the beer flip-flop. The direct output of the first flip-flop is coupled to the input 200 904

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- 2 by my second flip-flop · The output of the second flip-flop is connected β by the first input of the product circuit · The output of the flip-flop is connected to the blocking input of each divider. The output of each divider is connected to the corresponding wiring output. Each wiring set-up input is connected to an external outlet corresponding to the first to last divider. The functional input of each divider is connected to the output of the associated contact switch and to the corresponding input of the addition circuit. The output of the adding circuit is coupled to the input of the first timing circuit, the input of the second timing circuit, and the input of the delay circuit. The delay circuit output is coupled to the third gate of the gate circuit. The second input of the gating circuit is connected to the output of the second timing circuit. The first input of the gating circuit is coupled to the output of the first timing circuit. The inverting output of the gating circuit is coupled to the inverting input of the first flip-flop. The inverse output of the first flip-flop is connected to the second input of the product circuit and to the inverse input of the second flip-flop. The timing input of the second flip-flop is coupled to the timing input of the first flip-flop and the wiring timing input.

The advantage of the circuitry according to the invention is that it enables a single-pole connection of the contact switches to the logic circuits and at the same time ensures a safe function of the dividing function. The wiring is provided with a single common immune circuit for all contact switches. This significantly reduces the number of gates in the wiring and connections from the contact switches to the logic circuits. Noise immunity is ensured by the time constant of monostable flip-flops, which is the same for all contact switches. By changing this time constant, it is easy to adapt the wiring for different types of contact switches with different contact stabilization times.

An example of an arrangement according to the invention is shown in the block diagram of the attached drawing.

The direct output 21 of the gate circuit 6 formed of the gates is connected to the direct input 26 of the first flip-flop circuit 6. The direct output 26 of the first flip-flop 6 is connected to the direct input 28 of the second flip-flop 6. The flip-flops 6, 6 are of the same type JK. The outlet 31 of the second flip-flop circuit 6 is connected to the first input 32 of the product circuit 2, which is constructed of gates. The output 34 of the power circuit is connected to the blocking input 40. 40 «. up to 40 _{n of} each divider £, £ ₂ , 2 ^. Each of them is composed of two flip-flops, a corrector and a gate. The output 41 až to _{nn of} each divider £ _n is connected and the corresponding wiring output 43 až to _{n n n} . Each adjustment input 42 ₁ £ 2 & wiring is connected and an external input 39 to 39 _with the associated divider £ ^ and £ ^ Function input 38-38 _n first to last divider £ ^ and £ is connected both to the output 37 ^ to 37 ^ associated contact switches 10 ₁ to 10 _n and with the corresponding inputs 36 to ££ ^ _Q sčítaoího circuit 8. All contact switches 10 ^ J0 and _Q are of the same type and each of which is implemented as a button equipped with a single-pole normally open contact. The number of switches (contact contacts) 10 to 10 _fl is

200 904 equal to the number of dividers 2 ^and j · 5η Sčítaoí circuit 8 is composed of throats. The output 35 of the addition circuit 8 is connected to the input 12 of the first timing circuit 2, se. by the input 14 of the second timing circuit 2 and with the input 16 of the delay circuit 2 * 06a, the timing circuits are of the same type and are composed of monostable flip-flops. The delay circuit 2 consists of gates and an RC cell. The output 17 of the delay circuit 2 3 ^e sp ° 3®n with the third input 20 of the gating circuit 4 · The second input 19 of the gating circuit 4 is connected to the output 15 of the second timing circuit 2. The inverse output 22 of the first flip-flop 2 is connected to the inverse input 24 of the first flip-flop 5 ^{and the} inverse input 29 of the second flip-flop 6. The timing input 30 of the second flip-flop 6 is connected to the timing input 25 of the first flip-flop 5 and the wiring timing input 11.

The circuit also operates from the outputs 37 ^, 37n to 37 ^ of the contact switches 10 ^ 10g to 10 _u , the signals are applied to the inputs 36 ^. 36 ^ ^to 36 sčítaoího circuit 8, which are summed. These signals are simultaneously applied to the functional inputs 38 '. 38 ^ to 38 ^ splitter 2 p to 2 _n · Sčítaoí circuit 8 through its output 35 controls both timing circuits 1, 2 and delay circuit J. When the signal change at the output 37 ^ »37o to any one of the contact switches 10 ^. JOg up to 10 _u . at the same time, the signal at the output 35 of the adding circuit becomes grainy

8. By changing the signal at the output 35 sčítaoího circuit 8 not only in the case that has a signal at the output 2Z-) »37o to 37 _&-contact switch 10, 10 ₂ to 10 _n was active. If the signal changes to the active state at the output 35 of the counting circuit 8, the first timing circuit 2 is tilted. If the signal at the output 35 of the counting circuit 8 changes from the active to the passive state, then the second timing circuit 2 _t The delay circuit 2 delays the passage of the signal from its input 16 to its output 17. The function of the gating circuit 23 is such that during the tilting of any timing circuit 2, the signals are present at both the direct output 21 and the inverse output 22 of this gating circuit 2. passive state. If neither of the two timing circuits 2 »2» P®h is tilted, the direct output 21 of the gating circuit 2 monitors the signal at its third input 20. The signal at the inverting output 22 of the gating circuit 2 3® negates the signal at the third input 20 of the gating circuit. 2 · The first and second flip-flops 2, 6 are connected as a shift register. The product circuit 2 evaluates the condition of the two flip-flops 2 ^and 6. If these flip-flops 2 »6 are mismatched, a transient pulse is generated at the output 34 of the flip-flop 2 to change the state of the divider 2-)» and ₂ to 2. _n , which at this time has an active signal at its functional input 38 ^ 38-38 _n . Adjustment inputs 42, 42o to _42f1 are fed with data from downstream logic circuits not shown in the drawing. Clock pulses are supplied to the wiring input 11, which serves to shift a register made up of both flip-flops 2 ^and 6. Data to the subsequent logic circuits are fed from outputs 22 → 12 I ^to wiring.

The invention is used in numerical control of machine tools.

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Claims (1)

SUBJECT OF THE INVENTION Connection of splitters with contact switches consisting of two timing circuits, delay circuit, gating circuit, two flip-flops, product circuit, adding circuit, dividers and contact switches, characterized in that the direct output (21) of the gating circuit (4) is connected with a direct input (23) of the first flip-flop (5) whose direct output (26) is connected to the direct input (28) of the second flip-flop (6), the output (31) of which is connected to the first output (32) 7) whose output (34) is connected to a locking input (40p 40 _2, 40 &) of each divider (9 & 9 g, 9 _n), the outlet (41 .μ 41 g »41 _n) is connected with the corresponding output (43p 43 ₂ »43 _fi ) wiring whose first to last adjustment input (42p 42g, 42 _n ) is connected to the external input (39p 39 ₂ » 39%) of the corresponding first to last divider (9p 9g, 9 _β ), whose functional input (38p 38 ₂ , 38 _n ) is connected to the output (37p 37 _2, 37 _n) associated with the contact switch (10p 10 _2, 10 _n) and the corresponding inputs (36th ,, 36 g, _n-6) sčítaoího circuit (8) whose outlet (35) is connected with an input (12) of the first timing circuit (1), an input (14) of the second timing circuit (2) and an input (16) of the delay circuit (3) whose output (17) is connected to the third input (20) of the gating circuit ( 4), whose second input (19) is connected to the output (15) of the second timing circuit (2), the output (13) of the first timing circuit (1) is connected to the first input (18) of the gating circuit (4), the output (22) is connected to the inverse input (24) of the first flip-flop (5) whose inverse output (27) is connected to the second input (33) of the product circuit (7) and to the invert input (29) of the second flip-flop (6) whose timing input (30) is coupled to the timing input (25) of the first flip-flop (5) and the wiring timing input (11) .