CN86100527A - Polishing u-groove isolation technique - Google Patents
Polishing u-groove isolation technique Download PDFInfo
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- CN86100527A CN86100527A CN 86100527 CN86100527A CN86100527A CN 86100527 A CN86100527 A CN 86100527A CN 86100527 CN86100527 CN 86100527 CN 86100527 A CN86100527 A CN 86100527A CN 86100527 A CN86100527 A CN 86100527A
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- isolation
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Abstract
The present invention is a polishing U-groove isolation technique, belongs to the improvement of separator manufacturing technology between integrated circuit component.It adopts reactive ion etching corrosion isolation channel, fills out groove with polysilicon then.The present invention polishes with chemistry or the ion etching of chemical mechanical polishing method surrogate response and scabbles surperficial polysilicon.Make isolation technology simple, be convenient to control, cost is low, and the isolated area size is little and surface smoothness is good, be suitable for large-scale production, is particularly suitable for the present working condition of China.
Description
The present invention is a polishing U-groove isolation technique, belongs to the improvement of element spacing absciss layer manufacturing technology in the integrated circuit.
Interelement isolation once generally adopted the P-N knot to isolate in the integrated circuit.Must stay very big spacing between the base of this method and the isolation channel, the area of element can not be dwindled, integrated level is difficult to improve.Fa Zhan planar isolated technology such as selective oxidation adopted dielectric isolation afterwards, and base and emitter region can reduce component size near isolation channel, have improved the integrated level and the switching speed of integrated circuit.But the selective oxidation partition method have " bird chews " (birds beak), and insulation voltage is not high, has placed restrictions on further reducing of component size.Along with integrated circuit at a high speed and ultra-large direction develops and the use of new technology means (for example ion injection and dry etching), the partition method of multiple replacement selective oxidation occurs in succession.For example, the Japan in August nineteen eighty-three and September " electronic material " magazine " special permission case in " hurdle (see Japan's " electronic material ", 1983, № 8, pp 106-107 and № 9 pp 114-115) introduced about 33 of the Japan Patents of isolation technology totally.These patented technologies or employing means of different are improved the selective oxidation method, or adopt V-arrangement or U-lag to isolate the method for filling silicon dioxide or polysilicon and selective epitaxy growing method etc.But these methods are because complex process is all met some difficulties aspect practicability.In practicality success the U-lag isolation technology arranged.In the 13 the international solid state device meeting that 1981 hold in Tokyo, people such as Yoichi Tamaki have proposed this technology and (have seen Jap J.A.P, V21, Supp 21-1, pp 37-40,1982; Jaurnal of Elec Eng, V19 № 188, pp 36-39,1982).This technology is the isolation channel that adopts reactive ion etching to carve, and fills out groove with silicon dioxide or polysilicon, scabbles the surface with reactive ion etching at last.This technology adopts the reactive ion cutting, and the isolation channel size can be less than 2 μ m, owing to there is not lateral encroaching, isolation channel can be done suddenly, and passes epitaxial loayer and buried layer, through substrate, thereby isolation performance is good, the puncture voltage height.Whole isolated technology is all finished under less than 1000 ℃, and buried regions upwards spreads little, has reduced by a photoetching.In addition, adopt dielectric isolation, isolation junction electric capacity is little.But this technology is scabbled the surface with reactive ion etching, the difficult control of technological requirement height, grinding speed and surface smoothness, and surfacing is very important in integrated circuit fabrication process.And the reactive ion etching equipment complexity, production cost is higher.
The objective of the invention is in the U-lag isolation technology, scabble the surface with machinery or cmp method substitution reaction ion etching process.Machinery or cmp method grinding skin, polishing process is controlled easily, and cost is low, is fit to large-scale production.
Under same polishing condition, the polishing speed of polysilicon is faster more than 50 times than silicon dioxide or silicon nitride.The present invention is based on this principle and designs.Technical process of the present invention is:
1. in integrated circuit isolation process, isolation channel is corroded at first photoetching.The isolation channel corrosion depth should be passed epitaxial loayer and buried layer, through substrate.
2. be silicon dioxide or the silicon nitride of 0.2-1.2 μ m at isolation channel and surface with chemical vapor deposition (CVD) or low-pressure chemical vapor deposition (LPCVD) method growth thickness.Also can growthing silica and silicon nitride film system.
3. fill isolation channel with CVD or LPCVD method growing polycrystalline silicon.
4. with machinery or cmp method polished surface.It is different and change that polishing condition is looked polishing micro mist or polishing fluid.Obtain Type B (Tetramethylammonium hydroxide) polishing fluid of national invention third prize in 1984 as employing, then pH value is 8-10, and polish pressure is 1-2.5 kilogram/cm
2, be 0.1-2 μ m/ branch to the polysilicon polishing speed.Also can obtain satisfied result with other silicon chip glossing commonly used.
The invention is characterized in the silicon chip surface behind machinery or the chemico-mechanical polishing polysilicon filling isolation channel.When polishing, the polysilicon on the surface of at first skimming, after exposing silicon dioxide or silicon nitride, polishing speed obviously slows down, the then very fast polished removal of residual polysilicon, thus make polishing process be convenient to control, surface smoothness is easy to guarantee.
U-lag isolation technology of the present invention uses the vertical processing of reactive ion etching method to carve isolation channel and finishing method scabbles the surface, needn't form taper with corrosive liquid earlier before reactive ion etching is driven deep trouth, and then carve deep trouth and (see Jap J.A.P, V21, Supp 21-1, pp37-40,1982; Jaurnd of Elec Eny, V19 № 188, pp36-39,1982) thereby be easy to make isolation channel less than 2 μ m, the surface of polished irregularity degree is less than 2700
, the best can be no more than 500
The present invention is owing to adopt finishing method, and technology is simple, is convenient to control, and is with low cost, is fit to large-scale production, is specially adapted to the existing working condition of China.Can be widely used in the large scale integrated circuit production technology, be used for cmos circuit and also can avoid controlled silicon effect.
Accompanying drawing 1-3 has illustrated three embodiments of the present invention respectively.(1) is substrate among the figure, is generally p
-Type, (2) are n
+Buried layer, (3) are n type epitaxial loayers, and (4) are thin layer of silicon dioxide, and (5) are silicon nitrides; (6) be silicon dioxide layer, (7) are polysilicons, and (8) are aluminium, as the reactive ion etching protective layer; (9) be photoresist, as the protective layer of corrosion aluminium, (10) are p
+The injection region.
The technological process of accompanying drawing 1 expression is:
1.p
-Substrate (1) is gone up diffusion earlier or is injected n
+Buried regions (2), grown epitaxial layer (3), thermal oxidation obtains silicon dioxide layer (4), silicon dioxide bed thickness 800-1500
, evaporation 5000-7000
Aluminium (8), resist coating (9), photoetching is isolated slotted eye and (is seen Fig. 1 a).
2. use reactive ion etching aluminium, corrode silicon with reactive ion etching again, corrosion depth obtains precipitous isolation channel district up to substrate, at isolation channel district boron ion implantation (10), to cut off the isolation channel electric leakage, sees Fig. 1 b.Reactive ion etching is gases used to be the sulphur hexafluoride oxygen.
3. removal aluminium, the cell wall thermal oxidation gets silicon dioxide layer 800-1500
(4), CVD or LPCVD method deposit 0.1-0.3 μ m thick silicon nitride (5) in succession, 0.2-1 μ m thick silicon dioxide (6) and polysilicon (7), and the thickness of polysilicon should fill up isolation channel, (seeing Fig. 1 c).
4. with the polysilicon on machinery or the chemical mechanical polishing method polishing oxide layer,, use HF: HNO up to exposing silicon dioxide layer (6)
30.5-1 μ m polysilicon in=1: the 99 corrosive liquid etching tanks is removed silicon oxide layer (6), makes mask to the oxidation that elects of polysilicon in the isolation channel with silicon nitride (5), and surfaces nitrided silicon (5) is removed in final etching, (seeing Fig. 1 d).
The flow process of second embodiment of accompanying drawing 2 expressions is:
1.p
-Substrate (1) is gone up preparation n
+Buried regions (2), n type epitaxial loayer (3), grow thick 800-1500
Thermal oxide layer (4), the deposition 0.1-0.2mm silicon nitride (5), 0.2-1 μ m silicon dioxide (6), the evaporation 5000-7000
Aluminium (8), resist coating (9), slotted eye is isolated in photoetching, and (Fig. 2 is a).
2. corroding aluminium with reactive ion etching, is that mask corrodes silicon with reactive ion etching again with aluminium, and corrosion depth obtains the isolation channel district up to substrate, at isolation channel district boron ion implantation (10), to cut off isolation channel electric leakage (Fig. 2 b).
3. removal aluminium, cell wall thermal oxidation, oxidation bed thickness 2000-5000
, fill polysilicon (7) with CVD or LPCVD method, up to filling up isolation channel, (Fig. 2 c).
4. polished surface polysilicon (7) is used HF: HNO up to exposing silicon dioxide layer (6)
30.5-1 μ m polysilicon in=1: 99 etching tanks is removed oxide layer (6), makes mask with silicon nitride (5), to the oxidation that elects of polysilicon in the groove, removes silicon nitride (5) at last, (Fig. 2 d).
The 3rd embodiment of accompanying drawing 3 expression, when isolation channel is very narrow as less than 2 μ m the time as long as do the barrier layer of polishing with silica or silicon nitride.Its technological process is:
1. behind preparation buried regions and epitaxial loayer, thermal oxidation-thin layer again, thickness is 800-1500
, evaporation of aluminum 5000-7000
, the photoetching isolation channel in the through substrate groove of dry etching aluminium and silicon, is annotated boron, and (Fig. 3 is a) to cut off the isolation channel electric leakage
2. remove aluminium (8), thermal oxidation 800-2500
, deposition of silica 5000-9000
(6) or deposit 1000
-3000
Si
3N
4, deposit spathic silicon (7) is up to filling up isolation channel (Fig. 3 b).
3. polished surface polysilicon (7) up to exposing silicon dioxide layer (6), is used HF: HNO
30.5-1 μ m polysilicon in=1: 99 etching tanks,
To the oxidation (Fig. 3 c) that elects of polysilicon in the groove
In the above embodiment, all should carry out necessary cleaning between each technical process certainly.
Claims (2)
1, the present invention is the U-lag isolation technology, belongs to the improvement of element spacing absciss layer manufacturing technology in the integrated circuit.It comprises reactive ion etching corrosion isolation channel, fills out groove with polysilicon, scabbles groove outer surface polysilicon.Feature of the present invention is with machinery or cmp method polishing trough outer surface polysilicon.
2, U-lag isolation technology according to claim 1 is characterized in that the polishing fluid that chemico-mechanical polishing is used is the Type B polishing fluid: Tetramethylammonium hydroxide, PH8-10, pressure 1-2.5 kilogram/cm during polishing
2, be 0.1-2 μ m/ branch to the polishing speed of polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 86100527 CN86100527A (en) | 1986-03-14 | 1986-03-14 | Polishing u-groove isolation technique |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 86100527 CN86100527A (en) | 1986-03-14 | 1986-03-14 | Polishing u-groove isolation technique |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN86100527A true CN86100527A (en) | 1987-09-23 |
Family
ID=4801061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 86100527 Pending CN86100527A (en) | 1986-03-14 | 1986-03-14 | Polishing u-groove isolation technique |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6559027B2 (en) | 1997-02-18 | 2003-05-06 | Hitachi, Ltd. | Semiconductor device and process for producing the sme |
| CN1112727C (en) * | 1997-02-18 | 2003-06-25 | 株式会社日立制作所 | Semiconductor device and process for producing the same |
-
1986
- 1986-03-14 CN CN 86100527 patent/CN86100527A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6559027B2 (en) | 1997-02-18 | 2003-05-06 | Hitachi, Ltd. | Semiconductor device and process for producing the sme |
| CN1112727C (en) * | 1997-02-18 | 2003-06-25 | 株式会社日立制作所 | Semiconductor device and process for producing the same |
| US7402473B2 (en) | 1997-02-18 | 2008-07-22 | Renesas Technology Corp. | Semiconductor device and process for producing the same |
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