CN85202661U - Phaselocked loop model frequency synthesizer of high speed and low-phase noise - Google Patents
Phaselocked loop model frequency synthesizer of high speed and low-phase noise Download PDFInfo
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- CN85202661U CN85202661U CN 85202661 CN85202661U CN85202661U CN 85202661 U CN85202661 U CN 85202661U CN 85202661 CN85202661 CN 85202661 CN 85202661 U CN85202661 U CN 85202661U CN 85202661 U CN85202661 U CN 85202661U
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- 230000010355 oscillation Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
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Abstract
The utility model discloses a phase locked loop model frequency synthesizer of the high speed and the low-phase noise, belongs to the technical field of the electronic technology, and is suitable for a radar and a microwave communication system. The utility model uses a super high frequency (UHF) phase-locked loop as core and is used with a frequency multiplier to obtain each usual microwave frequency band (L, S, C, X). The phase locked loop model frequency synthesizer has the frequency switching speed of 50 microseconds, and also has the phase noise performance when the carrier wave of a single sideband phase noise density is 90 dbc/hz at the position of the I K H Z offset frequency. The utility model is used as the signal source and the stable local oscillator of a coherent radar in order to cause the radar not only to confront passive jamming, but also to confront active jamming. The phase locked loop model frequency synthesizers can be used for various microwave communication systems.
Description
The utility model belongs to electronic technology field, is applicable to radar and microwave telecommunication system.
Very general at the frequency synthesizer that high frequency and very high frequency (VHF) is communication aspects are used (VHF); Technology maturation; Type of merchandize is a lot.The Microwave Frequency Synthesizer of using as instrument also has the merchant to sell.But the frequency switch speed of these synthesizers is all very slow; Usually in millisecond magnitude or slower.The frequency synthesizer of using in modern radar and the microwave telecommunication system requires to have the switch speed of tens microseconds; Requires to have high frequency stability simultaneously (in other words; Extremely low phase noise) .The paper and the works of external existing this quefrency synthesizer. for example International Telephone and Telegraph Corporation (ITT) very fly the sub-phaselocked loop that the L that mentions in the paper of orchid (GILFILLAN) branch (U.S.) in the 34th FREQUENCY CONTROL annual meeting in 1980 (Proc.34th Annual Freguency Control Symposium May 1980) " adopt prompt step-down make an uproar mutually L and the S-band radar driver of pll synthesizer " (AnL-and S-band RADAR exciter using agile low noise phase lorked loop Synthesigers) and S-band PLL frequency synthesizer adopt L-band master phaselocked loop and be operated in 300～409MHz, and the S-band phaselocked loop that is consisted of by upconverter and sampling discrimination device. The performance of making an uproar mutually of the monolateral band phase noise density carrier wave ratio (1KHz deviation frequency place) of switch speed with 60 microseconds and-110dBC/Hz.Hewlett-Packard (Hewlett-Packard Corporation) instrument in 1984 " microwave synthesized signal generator " (Synthesized Signal Generator) HP8662A for another example, its performance of making an uproar mutually reaches-130dBC/Hz (1KHz deviation frequency place), but its frequency switch speed is in the millisecond magnitude.See Hewlett-Packard Corporation's handbook in 1984. (1984 HEWLETT PACKARD Measurement, Computation, Systems)
The utility model is exactly core---the main phase-locked loop of a kind of Microwave Frequency Synthesizer of design at requiring frequency switch speed height to require this class application of high frequency stability simultaneously.Adopt this phase-locked loop and be equipped with frequency multiplier, just can obtain the frequency synthesizer on each microwave frequency band commonly used (L, S, C, X frequency range).
Circuit block diagram of the present utility model as shown in Figure 1.Wherein derived reference signal is the quartz oscillator of high frequency stability, and phase-locked loop is digital, and frequency divider is the high-speed programmable digital frequency divider, and phase detector is digital.Reference frequency is through suitably being added to phase detector behind the frequency division, and the part output of voltage controlled oscillator (VCO) is added to another input of phase detector later on through variable division.The output of phase detector is through low-pass filtering and amplify voltage controlled oscillator (VCO) removed to control in the back as the error signal of loop frequency of oscillation.VCO is operated in hyperfrequency (UHF) frequency range, and the phase demodulation frequency of its frequency and phase detector differs N doubly, and N is the variable division ratio.Control N just can change the frequency of VCO.Output frequency is the frequency of VCO, and therefore changing frequency dividing ratio N just can change output frequency.When loop-locking, VCO is pinned by the quartz oscillator of high stable, thereby obtains the very high output signal of frequency stability.The input instruction signal of control circuit is the binary number coded signal of Transistor-Transistor Logic level.
Adopted microstrip transmission line in the voltage controlled oscillator (VCO), its scheme circuit such as accompanying drawing 2.The terminal of quarter-wave transmission line meets two varactor D
1And D
2, frequency of oscillation is added to varactor D
1And D
2On voltage V
1And V
2Control.There is not the lumped inductance device in the oscillating circuit.Vibration output is given load after buffering is amplified.Class buffer amplifier and oscillator stage directly are coupled, and its output circuit is common microstrip circuit, load 50 Ω.Entire circuit is produced on the printed circuit board (PCB), has good seismic resistance.The power circuit of voltage controlled oscillator has stable-pressure device in the box, and it is functional to guarantee to make an uproar mutually.
The block diagram of high-speed programmable frequency-divider such as accompanying drawing 3.All adopt the merchant to sell integrated circuit MC12009(12013), MC10137, E10109, E10131, its maximum operating frequency can reach 600MHz, and frequency dividing ratio N from 20 to 600 can continuously change.If additional integrated circuit SP8619 as preposition frequency division after, maximum operating frequency can surpass 1000MHZ.
Phase-locked loop described in the utility model can realize that frequency interval is the frequency synthesis of several megahertzes.Adopt this hyperfrequency (UHF) phase-locked loop, be equipped with the frequency synthesizer that frequency multiplier or frequency mixer make and have highly versatile, circuit unit is few, and equipment volume weight is little, and cost is low.
The utility model reaches following index:
1. in hyperfrequency (UHF) frequency range, monolateral band phase noise density Carrier at 1KHz deviation frequency place, reaches-90dBC/Hz.
2. the frequency switch speed is less than 50 microseconds.
The utility model is suitable for as the signal source of radar and high stable local oscillator, and like this, radar can access very high (moving target relative fixed target) improvement factor, and simultaneously fast frequency conversion to resist positive interference.It also is applicable to microwave telecommunication system.After inserting the littler additional phase-locked loop of frequency interval, can also obtain the little frequency synthesizer to tens kilo hertzs of frequency interval.
Description of drawings
The low at a high speed phase-locked ring type frequency synthesizer block diagram of making an uproar mutually of Fig. 1
Fig. 2 voltage controlled oscillator schematic circuit
Fig. 3 high-speed programmable frequency-divider block diagram
Claims (1)
1, a kind of microwave frequency agility rate synthesizer that adopts digital phase-locked loop, the operating frequency that it is characterized in that phase-locked loop is at 300～900MHz; The low voltage-controlled oscillator circuit of making an uproar mutually is to constitute resonator with λ/4 transmission lines, constitutes oscillator stage with differential pair, and oscillator stage and class buffer amplifier directly are coupled; High-speed programmable frequency-divider is made of MC12009 (12013), E10109, E10131, MC10137 integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 85202661 CN85202661U (en) | 1985-07-04 | 1985-07-04 | Phaselocked loop model frequency synthesizer of high speed and low-phase noise |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 85202661 CN85202661U (en) | 1985-07-04 | 1985-07-04 | Phaselocked loop model frequency synthesizer of high speed and low-phase noise |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN85202661U true CN85202661U (en) | 1986-04-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 85202661 Ceased CN85202661U (en) | 1985-07-04 | 1985-07-04 | Phaselocked loop model frequency synthesizer of high speed and low-phase noise |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN85202661U (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100392413C (en) * | 2004-01-21 | 2008-06-04 | 发那科株式会社 | Noise detection device |
| CN101540606B (en) * | 2009-02-20 | 2011-10-26 | 中国科学院微电子研究所 | Frequency synthesizer and frequency synthesis method based on multi-path sampling |
| CN102739205A (en) * | 2011-04-13 | 2012-10-17 | 西门子公司 | A clock generation system |
| CN104467831A (en) * | 2014-12-10 | 2015-03-25 | 中国电子科技集团公司第二十六研究所 | Low-phase noise frequency synthesis system and method based on HBAR |
| CN107727928A (en) * | 2017-09-20 | 2018-02-23 | 戴承萍 | A kind of data signal frequency discriminator and its application method |
-
1985
- 1985-07-04 CN CN 85202661 patent/CN85202661U/en not_active Ceased
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100392413C (en) * | 2004-01-21 | 2008-06-04 | 发那科株式会社 | Noise detection device |
| CN101540606B (en) * | 2009-02-20 | 2011-10-26 | 中国科学院微电子研究所 | Frequency synthesizer and frequency synthesis method based on multi-path sampling |
| CN102739205A (en) * | 2011-04-13 | 2012-10-17 | 西门子公司 | A clock generation system |
| CN102739205B (en) * | 2011-04-13 | 2015-09-16 | 西门子公司 | Clock generation system |
| CN104467831A (en) * | 2014-12-10 | 2015-03-25 | 中国电子科技集团公司第二十六研究所 | Low-phase noise frequency synthesis system and method based on HBAR |
| CN104467831B (en) * | 2014-12-10 | 2017-08-04 | 中国电子科技集团公司第二十六研究所 | A kind of low phase noise frequency synthesizer system and method based on HBAR |
| CN107727928A (en) * | 2017-09-20 | 2018-02-23 | 戴承萍 | A kind of data signal frequency discriminator and its application method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CE01 | Termination of patent right | ||
| C17 | Cessation of patent right |