CN85200721U

CN85200721U - Digital phase tester on condition of heavy current

Info

Publication number: CN85200721U
Application number: CN 85200721
Authority: CN
Inventors: 卢银全; 方鸿发; 钟旭高; 康知敏; 陈堂敏; 杨剑非
Original assignee: GREAT WALL PRECISION ELECTRIC METER FACTORY
Current assignee: GREAT WALL PRECISION ELECTRIC METER FACTORY
Priority date: 1985-10-10
Filing date: 1985-10-10
Publication date: 1987-06-10

Abstract

The utility model is based on the preceding frequency pushing rate following principle of phase place, adopt measures such as accessory channel, 3600 frequency multiplication phaselocked loops, low-pass filter, floating ground of secondary shield technology, DC power supply, dual anti-interference rejector, get rid of various exceedingly odious electromagnetic interference (EMI) and electrical network and impact and disturb and obtain phasing degree test between quick, accurate electric current and voltage under the heavy current break-make condition, be suitable for industries such as motor, electric power, electrical equipment.Overall block-diagram is as above:

Description

Digital phase tester on condition of heavy current

The utility model belongs to test class.

Phasing degree tester under the generally popular for a long time steady state conditions can't solve the phasing degree test under the heavy current break-make condition at all.Electrical apparatus industry is to take pictures by light oscillograph to the classic method of phasing degree test under the heavy current break-make condition, carries out phase place by calculating then and demarcates.This method measuring speed is slow, and error big (± 3～4 °) is not directly perceived.

" electrical apparatus technology " in 1982 fourth phase literary composition of the master of Shanghai electrical apparatus technology research institute periodical: " precision measurement of phase place in the test of electrical equipment heavy current break-make " (author: Fang Hongfa), introduced the test philosophy and the basic scheme at operating frequency phase angle under the heavy current break-make condition, emphasized to push away principle before the phase place.But the electrical network actual operating frequency is not single fixed frequency (50HZ or 60HZ).But the frequency that is changing.Particularly under the heavy current break-make condition, extremely strong interference usually can cause the failure of above-mentioned ultimate principle, and instrument can't operate as normal.

The utility model pushes away principle before with above-mentioned phase place and changes frequency pushing rate following principle before the phase place into, gets rid of various electric and magnetic interferences influences, for phasing degree between the transient test electric current and voltage provides quick, accurate means of testing.

Ultimate principle of the present utility model is such:

Referring to principle waveform synoptic diagram 1 and main block diagram 2.Voltage U before the call through test electric current ₁From bearing the zero passage moment that half-wave changes to positive half-wave, the counting door is opened, and through seven cycles, its DC component has decayed substantially, the voltage U that test current is produced at the instrument input end after test current is connected ₂From bearing the zero passage moment that half-wave changes to positive half-wave, the counting door is closed.Be opened to from counting door that the clock number by the counting door is in the time of closing:

N＝3600×7＋ΔN （1）

And Δ N=△ tf ₀

∵ (φ)/(360°) ＝ (△t)/(T) ＝△t·f

∴△N＝N－3600×7＝ (φ)/(360°f) ·f ₀（2）

φ＝ (360°f)/(f ₀) ·△N （3）

In the formula, f is a voltage U ₁, U ₂Frequency, f ₀Be the clock frequency, the two can be considered constant.Because the function that 3600 system counters have automatic return-to-zero, count automatically is so the numerical value that counter output is shown is △ N.Know that from formula (3) tested angle phi is proportional to △ N.

Problem, i.e. a f appear here ₀Is value what are just suitable? to f is 50HZ, and △ N is 1(φ=0.1 °) time, f ₀Should get 180KHZ, corresponding φ is 2 π, shows to be 3600 just in time, get a decimal, but the phasing degree that direct representation goes out is 360.0 °.But, be 49.9HZ to f, if f ₀Still be 180KHZ, still corresponding φ is 2 π, shows that number is 360.0 no longer just, but 360.72 °.If f is 49HZ, 48HZ ┈, error will be bigger just.Adopt 3600 frequency multiplication phaselock techniques, can obtain f ₀Equal 3600f ₀By formula (3), even f departs from 50HZ, (because the scale-up factor of formula (3) is 1) that shown phase angle error always meets the demands.

In Fig. 1 and Fig. 2, U ₁Be tested loop terminal voltage, U ₂Be the terminal voltage that electric current of make-and-break produces at sampling loop, U ₃Be double power-supply system current supply circuit terminal voltage.Since after heavy current is connected, U ₁Almost nil, so, U among Fig. 1 ₁Be represented by dotted lines.

Working of an invention is realized by concrete structure block diagram shown in Figure 3 and Fig. 4 passage figure.

Instrument by three passages (18), (19), (20, gating circuit (4), (11), 3600 system counters (6), counting door (5), decoding gate display (7), 3600 frequency multiplication phaselocked loop major parts such as (17) are formed.

First passage, i.e. U ₁Passage is called voltage channel (18) again, comprises noise killer (13), attenuator (14), low-pass filter (15) and amplification shaping device (16).Wherein noise killer is a kind of π type LC low-pass filter, upper cut off frequency 1MHZ, and telefault two-wire and on FERRITE CORE requires to reduce as far as possible distributed capacitance.Attenuator is in the decay of measurement range ratio, and its output voltage normalizing is to the 0.2V(full scale).Low-pass filter is actually the low-pass active filter that is made of the in-phase proportion amplifier, and its closed loop gain is 10, and upper cut off frequency is 200HZ.The amplification shaping device closed loop gain is 30, and purpose is to improve the quality of shaping waveform.

Second passage, i.e. U ₂Passage is called current channel (19) again.It is except comprising U ₁Outside the content of passage, also comprise U ₃Passage begins to count and close the control circuit door 1(4 of counting door).Its input signal is to be obtained by current transformer.U ₂From occurring decaying to zero to DC component, approximately will be through the time of seven cycles.

In order to guarantee to measure the loop operate as normal, most electrical apparatus tests all have dual power supply system.In view of the dual power supply system frequency is identical, non-electric source for test purposes is relatively stable, and this instrument adopts non-electric source for test purposes power supply, and opens up new third channel, i.e. U ₃Passage is called accessory channel (20) again.It is except comprising U ₁Outside the content of passage, also comprise tetrad counter (being septenary counter) (9), 3600 frequency multiplication phaselocked loops (17).The time that septenary counter begins to count is depended on U ₂Bistable in the passage ₂(28) whether overturn gate ₂(11) whether open, just U ₂Whether have from negative to positive zero-crossing pulse.Counter is in case full seven zero-crossing pulses of meter, gate 1(4) just allow to close counting door (5).

The core of 3600 frequency multiplication phaselocked loops (17) is digital phase demodulation, voltage controlled oscillator (8) and 3600 to 1 frequency dividers (12 binary counters (12) among Fig. 3); Its output frequency f ₀Motor synchronizing is in electrical network f, and f ₀Equal 3600f.

In addition, guarantee fully that instrument impacts operate as normal under the interference at the exceedingly odious interference of electromagnetic field, electrical network, also must adopt strict multiple jamming countermeasure, as floating ground of instrument secondary shield technology, DC power supply, power supply noise killer etc.

Through after the above implementing method, the utility model can reach following the key technical indexes:

Measuring voltage: phasing degree scope between electric current: 000.0～360.0 °

Frequency range: 45～62HZ

Requirement to the input waveform: two channel input signal waveform distortions should be less than 1%

Precision: trial voltage each grade setting ± 20% change, and be not less than 200MS conduction time, instrument incoming line resistance is not more than 1 Ω, test current is in each grade specialized range, phase angle error is not more than ± 1 °

Definition: 0.1 °

Test loop voltage: 110～1200V

Instrument input terminal voltage U after the voltage divider dividing potential drop ₁: 22～240V

Test loop electric current: 1～100KA

Instrument input terminal voltage U after the shunt shunting ₂: 0.1～2V

The meaning of each reference signs is in the accompanying drawing:

1---passage ₁ 2---passage ₂ 3---passage ₃ 4,11---gate₁, every control ₂ 5---the counting door; 6---3600 system Counters; 7---decoding monitor; 8---digital phase detection, voltage controlled oscillator; 9---the tetrad counter; 1035---decoder₁, decoder₂ 12---12 system Counters; 13---noise killer; 14---attenuator; 15---low pass filter; 16---amplification shaping device; 17---3600 frequency-multiplication phase-locked loops; 18---voltage channel; 19---current channel; 20---accessory channel; 21,22,23,24---differential₁, differential₂, differential₃, differential₄ 25,26,25,26---buffer₁,

buffer

₂ 27,28,29,30---the bistable bistable₁, bistable₂, bistable₃, bistable₄ 31,32,33,34---phase inverter₁, phase inverter₂, phase inverter₃, phase inverter₄。

Claims

1, utilizes the preceding frequency pushing rate following principle of phase place, tester mainly is made up of voltage channel (18), current channel (19), accessory channel (20), 3600 frequencys multiplication phase-locked (17), low-pass filter (15), amplification shaping device (16), dual anti-interference rejector (13) and 3600 system counters (6) etc., finishes phasing degree test between voltage, electric current under the heavy current break-make condition.It is characterized in that:

A. accessory channel (20) is responsible for finishing the counting that is subjected to first self seven zero-crossing pulses from negative to positive zero-crossing pulse restriction, with U ₂Cooperate and close counting door (5).

B. can and the self synchronous 3600 frequency multiplication phaselocked loops (17) of mains frequency be connected between accessory channel and the counting door.

2, tester according to claim 1 is characterized in that 3600 frequency multiplication phaselocked loops (17) can give pulsed frequency f ₀Equal 3600 times of mains frequency f.

3, tester according to claim 1 is characterized in that anti-interference rejector (13) places current supply circuit and each feeder connection place simultaneously, and its upper cut off frequency is 1MHZ.

4, tester according to claim 1, it is characterized in that 3600 system counters (6) place counting door (5) after, can carry out automatic return-to-zero to 3600 input pulses, remaining pulse shows for decoding monitor (7) after the return-to-zero, the expression phasing degree of surveying.

5, tester according to claim 1 is characterized in that low-pass filter (15) upper cut off frequency is 200HZ, and amplification shaping device (16) enlargement factor is 10.