CN85107067B - Circuit for converting integer into residue code block - Google Patents
Circuit for converting integer into residue code block Download PDFInfo
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- CN85107067B CN85107067B CN85107067A CN85107067A CN85107067B CN 85107067 B CN85107067 B CN 85107067B CN 85107067 A CN85107067 A CN 85107067A CN 85107067 A CN85107067 A CN 85107067A CN 85107067 B CN85107067 B CN 85107067B
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- carry
- adder
- circuit
- addition
- add
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Abstract
A method and a circuit easy to realize in simple engineering are needed to convert binary integers to one group of large module residue codes in a one-to-one correspondence mode. The present invention provides an addition method and a concrete circuit for calculating residue codes. Binary integers are divided into two word segments for addition according to a definite rule, and the residue codes are obtained by correction. The word length of the codes is shortened by multilevel conversion. The circuit adopts a method for grouping and parallelly adding operation numbers and does not have a carry chain. The residue codes can be used for realizing fast parallel arithmetic, and the operational speed can be enhanced by 4 times to 8 times. The present invention is used for the error detection of CPU, and the error detection capability can be enhanced by 17 times to 1000 times.
Description
The present invention relates to bigit is transformed to correspondingly the translation circuit of one group of big modulus residue code.
Originate from " Chinese remainder theorem ", being proposed to adopt the residue code of a plurality of moduluses by people such as SVABoDA and YAKEIR is integer transform the long operands of a plurality of short words, the theory that realizes fast parallel arithmetic (is stated from " DIGITAL INFoRMAT.IDN SWANDLEV " book and IEEE TRANSACTToN oNELECTRoNIC CoMPUTERS, 1962.PP501-507).And this Study on Theory is being carried out in the world always over 25 years.But, in computer, use this theory, run into very big difficulty.Because integer is transformed to the residue code of a plurality of moduluses correspondingly, also do not find the transform method of simple and easy realization on the engineering.This is because adopt single little modulus residue code (as 15 yards of moulds, 7 yards of moulds etc.) can not accomplish unique corresponding with integer.Thereby can not be used for replacing integer to carry out concurrent operation, the residue check in the existing error correcting technique comes to this, and the raising of restriction error correcting capability.Adopt decimal number system and little modulus residue code to carry out conversion and arithmetical operation, required hardware configuration is very complicated, and can't with the active computer compatibility.Adopt common combinational logic encoder to ask residue code, encode, and the quantity of required hardware increases by index law with the increase of decimal integer figure place, do not have feasibility on the engineering all integers in the computer.
The objective of the invention is: propose on a kind of engineering method simple and that be easy to realize, this method can be transformed to any bigit in the computer and its unique one group big corresponding modulus residue code; And proposition realizes the physical circuit of this method.
One, a kind of addition method of asking residue code is proposed.Press M
i=2Si-K
i(S
i, K
iBeing positive integer with i) the rule modulus of getting residue code is M
i, integer is divided into two fields, the low level section adds high-order section or its integral multiple.The purpose of addition is to make " power " of original each numerical digit of high order field become 2
n* M
i(n is high-order section since 0 numerical digit sequence number), thus can " lose " high-order section.Again the carry of addition gained and addition " with " addition, if " result " equals M
iThen replace, just obtain the mould M of integer with " 0 "
iResidue code.
Two, a kind of circuit of realizing the parallel addition of no-carry chain grouping of this method is proposed.This circuit adopts multi-level conversion, promptly asks the residue code of residue code again with addition method, thereby increases the number of sign indicating number and shorten its word length by 2 exponential depth.
Divide into groups again for the length on the higher level " field ", adopt a plurality of adders to carry out concurrent operation, and each unit only carries out sum operation one time, and remaining operation realizes by " add carry circuit " and (logic determines) correcting circuit with parallel organization.Do not have carry chain in the circuit, the high-level carry that goes up each group all is that " memory " handled in the conversion on low level then earlier.And on low level, obtain each required residue code concurrently simultaneously.Like this, just being transformed to the multiple unit parallel work-flow of no-carry chain fast at many levels.
The present invention is owing to mainly adopt eight (or four) adders, and " add carry circuit " and correcting circuit are made up of common unit IC, so be easy to realize that structure is simple especially.So that four decimal numbers are asked residue code with interior integer is example, adopts the circuit of the present invention hardware more required than conventional coders to lack 1,000 times.Owing to can obtain one group of residue code correspondingly to all integers in the computer, become the shortening word length of several times, so adopt this residue code, the arithmetic speed that can improve computer arrives near 8 times (needing to increase addition unit) for 4 times.Owing to adopt partial circuit of the present invention, just can be in the hope of single big modulus residue code, so aspect the CPU error detection, can improve 17 times to 1,000 times of error detecing capabilities than the method for existing residue check.Owing to adopt the hardware configuration of the fast parallel operation of no-carry chain, can obtain higher conversion rate.
Circuit structure of the present invention is provided by accompanying drawing, describes the composition structure and the workflow of circuit in detail below in conjunction with accompanying drawing.This circuit comprises the two parts that carry out two hierarchical transformations.The composition of first is: (1) bigit is carried out branch field and grouping through input distributor RI.Deliver to adder Q then respectively
1, Q
2, Q
3And Q
4(2) Q
1And Q
2Parallel work-flow, remainder (residue code of first level) in the middle of being used to produce.Q
1Produce its low portion addition " with " with carry F, addition " with " deliver to and transmit passage M
1; Q
2Produce its high-order portion addition " with " with carry C, addition " with " deliver to and transmit passage M
2(3) " addition and " of low portion, high-order portion and F and the calibrated circuit PB of C produce correction parameter.(4) working pulse P
1During arrival, correction parameter is removed F trigger and C trigger.(5) Q
1Addition " with " through M
1After the correction parameter correction, the low level section b of remainder in the middle of the output
1(6) Q
2Addition " with " through M
2Obtain proofreading and correct the high-order section b of remainder in the middle of the output
h
Second portion comprises four independent parallel unit that produce residue code, (7) shift circuit M
3An operand displacement.(8) (operation) control signal S
1During arrival, send Q two operands (two " groups " being equivalent to integer) through displacement
3Addition, and obtain carry C
1(9) add carry circuit A
1Q
3" with " and C
1Output register R is delivered in addition
1With correcting circuit PB
2(10) working pulse P
2During arrival, PB
2The correction parameter that produces is delivered to R
1, to A
1Output proofread and correct.(11) R
1In obtain first residue code.
(12) control signal S
1During arrival, directly send Q operand
4Addition, and obtain carry C
2(13) add carry circuit A
2Q
4" with " and C
2Output register R is delivered in addition
2With correcting circuit PB
3(14) working pulse P
2During arrival, correction parameter is delivered to R
2, to A
2Output proofread and correct.(15) R
2In obtain second residue code.
(16) (operation) control signal S
2During arrival, b
1C send Q with carry
5Addition.(17) addition " with " deposit in output register R as the 3rd residue code
3In.
(18) b
hWith carry C through add carry circuit A
3Addition.(19) control signal S
2During arrival, b
hAdd C " with ", b
1And carry F send Q
6Addition, and obtain carry C
3(20) add carry circuit A
4Q
6" with " and C
3Output register R is delivered in addition then
4With correcting circuit PB
4(21) PB
4Produce two correction parameter K
SAnd K
R(22) working pulse P
2During arrival, correction parameter is delivered to R
4(23) 3
4In obtain the 4th residue code.
A in the accompanying drawing
1, A
2Two " add carry circuit " can.But will be Q
3" with " and C
1Send Q back to
3Addition again; Will be Q
4" with " and C
2Send Q back to
4Addition again can be saved device like this, but increases work tempo.Do not requiring the occasion of speed, A
3, A
4Also can (b
hDirectly send Q
6).But will be Q
6" with " and C
3Send Q back to
6, and also send Q C simultaneously
6Addition again; Also to change correcting circuit PB
4Preferably mix control signal generator (circuit is simple, so do not draw in the accompanying drawing), use entire circuit more convenient as an individual components.
Claims (13)
1, a kind of integer transform is the circuit of residue code character, and it is made up of with the second portion of asking the residue code character the first of remainder in the middle of asking, and it is characterized in that its first is made up of following array apparatus:
(1), the input integer is divided into field and is assigned to four adder (Q
1～Q
4) input distributor (RI),
(2), integer field is transformed to middle remainder low level section (b respectively
1) and high-order section (b
h) the parallel first adder (Q of no-carry chain grouping
1) and the second adder (Q
2),
(3), according to the first adder (Q
1) " with ", the second adder (Q
2) " with ", the first adder (Q
1) the carry (F) and the second adder (Q
2) carry (C) produce correction parameter so that to these " with " and the first correcting circuit (PB that proofreaies and correct of carry
1),
(4), proofread and correct the first adder (Q
1) " with " and the middle remainder low level of output section (b
1) first transmit passage (M
1),
(5), proofread and correct the second adder (Q
2) " with " and the high-order section of the middle remainder of output (b
h) second transmit passage (M
2),
Its second portion is made up of following array apparatus:
(6), integer field remainder conversion in the middle of ask, directly the third phase of addition adds device (Q
3) and the 4th adder (Q
4),
(7), third phase is added device (Q
3) " with " and its carry (C
1) at the first add carry circuit (A
1) middle addition, and according to the first add carry circuit (A
1) output and third phase add device (Q
3) carry (C
1) at the second correcting circuit (PB
2) the middle correction parameter that produces, to the first add carry circuit (A
1) output proofread and correct and obtain first residue code,
(8), the 4th adder (Q
4) " with " and its carry (C
2) at the second add carry circuit (A
2) middle addition, and according to the second add carry circuit (A
2) output and the 4th adder (Q
4) carry (C
2) at the 3rd correcting circuit (PB
3) the middle correction parameter that produces, to the second add carry circuit (A
2) output proofread and correct, obtain second residue code,
(9), middle remainder low level section (b
1) and the second adder (Q
2) the 5th adder (Q of carry (C) addition
5) directly export the 3rd residue code,
(10), the high-order section of middle remainder (b
h) and the second adder (Q
2) the 3rd add carry circuit (A of carry (C) addition
3), its output and middle remainder low level section (b
1) and the first adder (Q
1) carry (F) be input to the 6th adder (Q
6) in carry out addition,
(11), the 6th adder (Q
6) " with " and its carry (C
3) at the 4th add carry circuit (A
4) middle addition, and according to the 4th add carry circuit (A
4) output and the 6th adder (Q
6) carry (C
3) at the 4th correcting circuit (PB
4) the middle correction parameter that produces, to the 4th add carry circuit (A
4) output proofread and correct, obtain the 4th residue code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN85107067A CN85107067B (en) | 1985-09-27 | 1985-09-27 | Circuit for converting integer into residue code block |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN85107067A CN85107067B (en) | 1985-09-27 | 1985-09-27 | Circuit for converting integer into residue code block |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN85107067A CN85107067A (en) | 1986-09-03 |
| CN85107067B true CN85107067B (en) | 1988-03-16 |
Family
ID=4795430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN85107067A Expired CN85107067B (en) | 1985-09-27 | 1985-09-27 | Circuit for converting integer into residue code block |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN85107067B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100367223C (en) * | 2004-05-27 | 2008-02-06 | 国际商业机器公司 | Method and system for checking rotate, shift and sign extension functions using a modulo function |
-
1985
- 1985-09-27 CN CN85107067A patent/CN85107067B/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100367223C (en) * | 2004-05-27 | 2008-02-06 | 国际商业机器公司 | Method and system for checking rotate, shift and sign extension functions using a modulo function |
Also Published As
| Publication number | Publication date |
|---|---|
| CN85107067A (en) | 1986-09-03 |
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