CN85101066A

CN85101066A - Method by majority detection and correction error

Info

Publication number: CN85101066A
Application number: CN85101066.0A
Authority: CN
Inventors: 辻川宏俊; 丸山勉
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1985-04-01
Filing date: 1985-04-01
Publication date: 1987-01-10
Also published as: CN1007021B

Abstract

According to the present invention, each data amount is transmitted three times.Once be to transmit raw data, another time is the oppisite phase data that transmits raw data, and remaining once is the data that transmit all positions of displacement raw data.By inverse code data and position cyclic permutation data being converted to again their original form, receiver reconstitute data and survey these data and the raw data that transmits separately between majority.For example, utilize circulating register to draw a cyclic permutation data by right circulation of predetermined figure place or left circulation raw data.Receiver must carry out with the position of transmitter change the operation reciprocal position change operation.

Description

Method by majority detection and correction error

The error that takes place during Data transmission between two devices that the present invention relates to detect and proofread and correct, particularly detect by majority and the method for round-off error.

Error detection code such as CRC (CRC) are in being usually used in universal serial bus.According to error-detecting, receiver needs a transmitter that transmits identical data again.In common system, the method correction error that attempt is transmitted again with error-detecting and data.Some systems adopt the code of energy error recovery, and this ability is referred to as ECC.

In a lot of situations, the error that takes place in the data that transmit by universal serial bus is a faults, so the SEC/DED code of single-error correction and double error detection is enough to survey and correction error.Yet in parallel bus, because one and multidigit error may occur, so need different solutions.In these solutions, fairly simple and be the majority method of reproducing raw data reliably.Dispensing device (as CPU (central processing unit)) is sent to parallel bus with identical data repeatedly, and simultaneously, the receiving trap that links to each other with parallel bus (as printer) is compared to each other numerous data that receive, and reproduces raw data by majority.In the sort of situation, as described at the unexamined patented claim 55-107357 of the patented claim 54-3336 that has examined of Japanese publication and Japanese publication, by means of sending data and its anti-phase form can increase the error-detecting ability.

If in parallel bus, permanent fault appears in individual wire, and the majority scheme of prior art can not detect.Reason is that the identical data that comprises Permanent error (as always " 1 ") is transmitted repeatedly, and is therefore also reproduced as raw data when carrying out majority in receiver.Except that permanent fault, in the situation about breaking down in the individual wire long period, also be like this.

Therefore, task of the present invention provides with majority and detects and the method for correction error, even receiver appears forever in this method in parallel bus and/or during chromic trouble, also can detect error from the data that are transmitted.

According to the present invention, each data (byte data in the described below scheme) amount to and are transmitted three times.Once be to transmit raw data, another time is the oppisite phase data that transmits raw data, and remaining once is the data that transmit all positions of displacement raw data.By inverse code data and position cyclic permutation data being converted to again their original form, receiver reconstitute data and survey these data and the raw data that transmits separately between majority.For example, utilize circulating register to draw a cyclic permutation data by right circulation of predetermined figure place or left circulation raw data.Receiver must carry out with the position of transmitter change the operation reciprocal position change operation.

According to the present invention, if only mistake occurred in data, it is possible proofreading and correct this mistake fully by majority, and mistake is when appearing in the data of two or three sequential delivery, receiver also can correctly be surveyed (in some situation, also can proofread and correct) this mistake.

Fig. 1 has provided and can use system block diagram of the present invention.

Fig. 2 is the block scheme of data translator unit structure example in the expression controller.

Fig. 3 is the block scheme of Data Receiving part-structure example in the expression printer.

Fig. 1 provides and can use system architecture of the present invention.Use for example CPU (central processing unit) of parallel bus 10 interconnected controller 12(though it comprises) and printer 14, the present invention is limited by the combination of this device not only.When the byte with data D sent to printer 14, controller 12 produced inverse code data D by anti-phase D, by all position generation position cyclic permutation data D of cyclic permutation D ^*, and sequentially these data are sent in the parallel bus 10.Though among Fig. 1 with D, D and D ^*Order send, but also can adopt any one order.

Printer 14 receives respectively with D, D and D ^*Corresponding data A, B and C '.If A=D, B=D and C '=D ^*Just no problem, even but allow controller 12 and printer 14 be in the best environment, can not make parallel bus 10 avoid certain noise effect, in addition, in some circuit of parallel bus 10, may open circuit or short circuit.The mistake that is caused by noise temporarily makes individual bits or changes to " 1 " from " 0 ", perhaps changes to " 0 " from " 1 ".According to statistical law, most of mistakes are to change to " 1 " from " 0 ".If the influence of noise was limited in the delivery time of byte,, can obtain correct data by means of transmitting identical data D more than the secondary and in receiver, being adopted majority logic as what talk about in the prior art.Yet if the influence of noise extends to passing time when surpassing more than a byte, receiver can reproduce a misdata as correct data, for example occurs in when being among three data D ' two at least when same error.The present invention is by transmitting D, D and D ^*Replace transmitting three D and overcome this class phenomenon.

Printer 14 temporarily stored data A the reception byte and B and C ' be converted to their original form respectively.According to conversion, B is produced by anti-phase B, and C will change that the opposite operation of direction of operating is added on the C ' with the position of being carried out and produces in controller 12.If A=B, at least one is real among B=C and the A=C, and as D, otherwise a mistake has appearred in printer notification controller 12 comparing data for printer 14 so.

Fig. 2 expresses the structure example of data translator unit in the controller 12.It comprises three 20,22 and 24 and phase inverters 32 of register that have out

gate

26,28 and 30 respectively.Controller 12 is applied to the byte of data D that is transmitted on the internal bus 34.When D register 22 receives by the anti-phase data D of phase inverter 32, D register 20 and D ^*Register 24 receives original form of data D.D ^*Register 24 is the circulating registers with circulation passage 36, and passage 36 extends to the highest significant position position from the least significant bit (LSB) position.Work as D ^*When register 24 received data D, it was according to predetermined figure place n, by circulation passage 36 circulating shift data D.N can be 1 and the figure place of data D to subtract 1(be 7 in this case) between and comprise any one numeral of 1 and 7, for for simplicity, one of the right circulation of this hypothesis.

Corresponding to the first transmission clock pulse C ₁Time, the raw data D that out gate 26 will leave in the D register 20 outputs to parallel bus 10, corresponding to the second transmission clock pulse C ₂Time, out gate 28 will leave the oppisite phase data D output in the D register 22 in, and corresponding to the 3rd transmission clock pulse C ₃Time, out gate 30 will leave D in ^*Position cyclic permutation data D in the register 24 ^*Output.D, D and D ^*The output order of three data can be by changing the transmission clock pulse C that uses ₁, C ₂And C ₃Order and change.

Although in the example of Fig. 1, D ^*Register 24 is circulating registers, and it also can be used for changing neatly each bit position of data D.For example, the Gao Siwei of data D can exchange with low four, and importantly the i position of data D must become D ^*In except that the i position the position.

Fig. 3 has provided the structure example of Data Receiving part in the printer 14.It comprises three 40,42 and 44, one phase inverters 52 of register and majority logic circuits 54 of having

input gate

46,48 and 50 respectively.Printer 14 sequentially is input to A-register 40 by

input gate

46,48 and 50 with data A, B and the C ' that receives respectively, in B-register 42 and the C ' register 44.The data A that is input in the A-register 40 is sent in the majority logic circuit 54 with its original form.The data B that is input in the B-register 42 is anti-phase by phase inverter 52, is transferred to then in the majority logic circuit 54.Be input to the data C ' in C ' register 44, through circulation passage 56, after one of the left ring shift (or right ring shift 7), be sent in the majority logic circuit 54.As previously mentioned, C ' register 44 must be carried out with respect to using D in the controller 12 ^*The opposite operation of operation is changed in register 24 performed positions.

Majority logic circuit 54 compares three one by one and receives data A, B and C, if A=B, at least one is real words among B=C and the C=A, the data that it will compare are exported as D, if perhaps neither one is real words among the three, it points out to have taken place mistake, that is to say that all data A, B and C are different.Obviously, when having only a data generation mistake in A, B and three data of C, can obtain correct data by majority.Therefore, the certain situation of narrating below is a situation about going wrong in two or three data.

Suppose data D, D and D that slave controller 12 sends out ^*As follows:

D＝10010110

D＝01101001

D ^＊＝01001011

Suppose again from a left side, corresponding figure place is 0,1,2 ... 7.If the fault of " 1 " always appears in the line of traffic bit 0 in the parallel bus 10, the data that receive by printer 14 become as follows:

A＝10010110

B＝11101001

C′＝11001011

Convert B and C ' to their original form again, gained is as follows:

B＝00010110

C＝10010111

Wherein, A, B are different each other with C, so the majority logic wireline inspection goes out error.On the throne 1, position 4, position 6 or position occurred at 7 o'clock (in these positions each in three data, all have two be " 1 ") if be always the fault of " 1 ", so also only in data, produce mistake, still can obtain raw data by majority.

Secondly, suppose that some faults except that permanent fault are put 2 among data D and the D by force and shown " 1 ", then the data of printer 14 receptions are as follows:

A＝10110110

B＝01101001

C′＝01001011

B and C ' are converted to their original form again, and gained is as follows:

B＝10010110

C＝10010110

Therefrom can draw B=C, so majority logic 54 is exported comparing data as D.

When in two or three data, the multidigit mistake occurring, can adopt same principle.Thereby, to compare with the situation of a faults, the possibility that obtains correct D in this situation becomes smaller.

Claims

1, in a data transmission system, the data that transmit are installed second device by parallel bus from first, adopt the method for majority detection and correction error, it is characterized by: in said first device, form radix-minus-one complement data and position cyclic permutation data, the radix-minus-one complement data are by anti-phase the forming of raw data of transmitting, and cyclic permutation data in position form by permutated bits in above-mentioned raw data; Said raw data, radix-minus-one complement data and position cyclic permutation data sequentially are sent in second device by parallel bus; In second device, radix-minus-one complement data and position cyclic permutation data are converted to original form more respectively, are determining a majority in data converted and the raw data again.

2, the method for claim 1 is that said position cyclic permutation data by predetermined figure place, form according to predetermined direction ring shift raw data.

3, the method for claim 1 is said raw data, and said radix-minus-one complement data and said position cyclic permutation data sequentially are sent in said second device with any order.

4, the method for claim 1 is that said position cyclic permutation data are by predetermined figure place, and along the direction in contrast to said predetermined direction, ring shift is reduced in said second device.

5, the method for claim 1 is that said second device just receives comparing data as said raw data until after determining a comparative result at least between said recovering signal and the original signal.